Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24669

1

T5

2

T28

1

T32

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21430

1

T5

2

T28

1

T32

3

auto[ADC_CTRL_FILTER_COND_OUT]

3239

1

T14

9

T22

20

T24

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18975

1

T5

2

T28

1

T32

3

auto[1]

5694

1

T12

1

T14

11

T15

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20678

1

T12

3

T13

153

T14

17

auto[1]

3991

1

T5

2

T28

1

T32

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	10	1			T263	10		-	-		-	-
values[0]	36	1			T166	15		T194	1		T221	1
values[1]	581	1			T12	1		T56	1		T57	1
values[2]	614	1			T39	7		T57	1		T40	3
values[3]	604	1			T12	1		T14	9		T150	24
values[4]	2666	1			T15	17		T18	2		T20	26
values[5]	600	1			T21	5		T88	1		T91	13
values[6]	553	1			T82	44		T84	4		T90	20
values[7]	729	1			T22	1		T39	5		T81	8
values[8]	773	1			T22	20		T24	11		T79	8
values[9]	1228	1			T12	1		T14	2		T39	3
minimum	16275	1			T5	2		T28	1		T32	3

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	748	1			T12	1		T56	1		T57	2
values[1]	642	1			T12	1		T39	7		T40	3
values[2]	603	1			T14	9		T93	15		T150	24
values[3]	2646	1			T15	17		T18	2		T20	26
values[4]	584	1			T21	5		T88	1		T91	13
values[5]	666	1			T82	44		T84	4		T85	15
values[6]	703	1			T22	1		T24	11		T39	5
values[7]	674	1			T22	20		T87	10		T79	8
values[8]	889	1			T12	1		T14	2		T39	3
values[9]	218	1			T81	37		T116	7		T130	19
minimum	16296	1			T5	2		T28	1		T32	3

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21184

1

T5

2

T28

1

T32

3

auto[1]

3485

1

T14

3

T15

15

T22

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T12	1		T94	1		T104	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T56	1		T57	2		T83	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T12	1		T104	7		T102	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T39	6		T40	2		T41	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T93	1		T197	1		T96	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T14	5		T150	14		T88	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1355	1			T15	17		T18	2		T20	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T81	9		T88	1		T173	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T21	1		T91	13		T102	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T88	1		T173	1		T128	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T82	5		T102	15		T96	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T82	13		T84	1		T85	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T22	1		T91	3		T86	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T24	9		T39	3		T81	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T79	7		T94	4		T86	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T22	10		T87	8		T94	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T12	1		T14	2		T93	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T39	2		T87	8		T89	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T81	17		T116	5		T130	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T264	14		T255	12		T156	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16141	1			T13	153		T14	10		T16	120
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T220	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T94	2		T141	7		T239	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T101	7		T103	3		T115	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T102	5		T106	7		T99	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T39	1		T40	1		T41	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T93	14		T215	12		T130	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T14	4		T150	10		T103	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1052	1			T20	24		T87	7		T101	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T81	6		T173	6		T205	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T21	4		T102	12		T103	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T173	3		T238	3		T265	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T82	12		T102	11		T115	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T82	14		T84	3		T90	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T105	9		T120	17		T209	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T24	2		T39	2		T84	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T79	1		T94	2		T86	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T22	10		T87	2		T94	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T93	8		T82	11		T41	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T39	1		T87	8		T89	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T81	20		T116	2		T130	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T156	19		T262	4		T266	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T5	2		T28	1		T32	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T263	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T221	1		T263	7		T267	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T166	1		T194	1		T268	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T12	1		T94	1		T141	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T56	1		T57	1		T83	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T104	13		T235	1		T98	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T39	6		T57	1		T40	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T12	1		T197	1		T102	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T14	5		T150	14		T88	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1309	1			T15	17		T18	2		T20	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T81	9		T88	1		T83	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T21	1		T91	13		T101	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T88	1		T173	2		T129	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T82	5		T140	1		T204	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T82	13		T84	1		T90	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T22	1		T86	1		T102	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T39	3		T81	8		T84	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T79	7		T94	4		T91	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T22	10		T24	9		T94	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T12	1		T14	2		T81	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	432	1			T39	2		T87	16		T89	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16129	1			T13	153		T14	10		T16	120
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T267	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T166	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T94	2		T141	7		T239	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T101	7		T103	3		T115	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T99	8		T269	15		T123	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T39	1		T40	1		T41	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T102	5		T106	7		T130	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T14	4		T150	10		T202	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1033	1			T20	24		T93	14		T87	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T81	6		T103	11		T105	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T21	4		T101	1		T102	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T173	9		T205	8		T238	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T82	12		T204	7		T106	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T82	14		T84	3		T90	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T102	11		T115	21		T120	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T39	2		T84	15		T85	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T79	1		T94	2		T86	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T22	10		T24	2		T94	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T81	20		T93	8		T82	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T39	1		T87	10		T89	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T5	2		T28	1		T32	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T12	1		T94	3		T104	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T56	1		T57	2		T83	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T12	1		T104	1		T102	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T39	3		T40	2		T41	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T93	15		T197	1		T96	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T14	6		T150	11		T88	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1386	1			T15	2		T18	2		T20	26
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T81	7		T88	1		T173	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T21	5		T91	1		T102	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T88	1		T173	4		T128	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T82	13		T102	12		T96	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T82	15		T84	4		T85	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T22	1		T91	1		T86	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T24	8		T39	4		T81	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T79	7		T94	3		T86	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T22	11		T87	3		T94	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T12	1		T14	2		T93	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T39	3		T87	9		T89	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T81	21		T116	3		T130	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T264	1		T255	1		T156	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16276	1			T5	2		T28	1		T32	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T220	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T104	5		T141	12		T211	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T83	7		T101	9		T103	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T104	6		T102	4		T260	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T39	4		T40	1		T41	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T96	5		T215	10		T130	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T14	3		T150	13		T83	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1021	1			T15	15		T23	17		T46	30
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T81	8		T209	1		T270	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T91	12		T102	13		T103	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T128	9		T238	1		T271	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T82	4		T102	14		T96	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T82	12		T85	14		T90	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T91	2		T177	7		T105	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T24	3		T39	1		T81	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T79	1		T94	3		T86	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T22	9		T87	7		T94	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T82	9		T41	9		T195	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T87	7		T89	3		T218	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T81	16		T116	4		T130	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T264	13		T255	11		T156	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T125	11		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T220	8		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T263	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T221	1		T263	1		T267	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T166	15		T194	1		T268	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T12	1		T94	3		T141	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T56	1		T57	1		T83	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T104	2		T235	1		T98	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T39	3		T57	1		T40	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T12	1		T197	1		T102	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T14	6		T150	11		T88	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1367	1			T15	2		T18	2		T20	26
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T81	7		T88	1		T83	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T21	5		T91	1		T101	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T88	1		T173	11		T129	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T82	13		T140	1		T204	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T82	15		T84	4		T90	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T22	1		T86	1		T102	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T39	4		T81	1		T84	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T79	7		T94	3		T91	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T22	11		T24	8		T94	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T12	1		T14	2		T81	21
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	377	1			T39	3		T87	12		T89	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16275	1			T5	2		T28	1		T32	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T263	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T263	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T141	12		T211	2		T239	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T83	7		T101	9		T103	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T104	11		T260	2		T272	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T39	4		T40	1		T41	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T102	4		T96	5		T130	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T14	3		T150	13		T95	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	975	1			T15	15		T23	17		T46	30
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T81	8		T83	4		T103	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T91	12		T102	13		T103	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T238	1		T273	11		T274	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T82	4		T204	3		T241	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T82	12		T90	2		T128	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T102	14		T177	7		T96	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T39	1		T81	7		T84	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T79	1		T94	3		T91	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T22	9		T24	3		T94	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T81	16		T82	9		T41	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	342	1			T87	14		T89	3		T218	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21184

1

T5

2

T28

1

T32

3

auto[1]

auto[0]

3485

1

T14

3

T15

15

T22

9