Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24669

1

T5

2

T28

1

T32

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21494

1

T5

2

T28

1

T32

3

auto[ADC_CTRL_FILTER_COND_OUT]

3175

1

T12

2

T14

11

T21

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18960

1

T5

2

T28

1

T32

3

auto[1]

5709

1

T12

1

T14

2

T15

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20678

1

T12

3

T13

153

T14

17

auto[1]

3991

1

T5

2

T28

1

T32

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	28	1			T22	20		T94	6		T275	2
values[0]	52	1			T103	14		T238	2		T237	33
values[1]	534	1			T88	1		T195	2		T140	20
values[2]	767	1			T81	37		T87	16		T88	1
values[3]	584	1			T12	1		T81	8		T88	1
values[4]	594	1			T12	1		T24	11		T39	5
values[5]	517	1			T39	3		T57	1		T40	3
values[6]	777	1			T82	27		T41	19		T84	4
values[7]	598	1			T12	1		T22	1		T87	10
values[8]	627	1			T14	9		T56	1		T39	7
values[9]	3316	1			T14	2		T15	17		T18	2
minimum	16275	1			T5	2		T28	1		T32	3

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	780	1			T81	37		T88	2		T89	7
values[1]	725	1			T12	1		T81	8		T87	16
values[2]	655	1			T12	1		T39	5		T150	24
values[3]	523	1			T24	11		T39	3		T79	8
values[4]	499	1			T57	1		T82	27		T94	23
values[5]	678	1			T40	3		T41	19		T84	4
values[6]	2810	1			T15	17		T18	2		T20	26
values[7]	658	1			T12	1		T14	9		T81	15
values[8]	870	1			T14	2		T21	5		T57	1
values[9]	174	1			T22	20		T93	9		T86	14
minimum	16297	1			T5	2		T28	1		T32	3

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21184

1

T5

2

T28

1

T32

3

auto[1]

3485

1

T14

3

T15

15

T22

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T195	1		T201	1		T103	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T81	17		T88	2		T89	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T81	8		T87	8		T88	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T12	1		T85	15		T86	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T12	1		T39	3		T41	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T150	14		T95	8		T104	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T39	2		T79	7		T102	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T24	9		T218	4		T105	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T94	12		T102	14		T96	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T57	1		T82	13		T101	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T84	1		T90	11		T224	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T40	2		T41	10		T103	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1393	1			T15	17		T18	2		T20	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T22	1		T56	1		T87	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T81	9		T87	8		T82	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T12	1		T14	5		T94	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T82	5		T94	4		T83	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T14	2		T21	1		T57	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T246	13		T223	14		T258	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T22	10		T93	1		T86	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16148	1			T13	153		T14	10		T16	120
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T195	1		T201	1		T103	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T81	20		T89	2		T276	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T87	8		T173	3		T206	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T102	5		T103	3		T166	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T39	2		T41	4		T105	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T150	10		T238	3		T123	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T39	1		T79	1		T102	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T24	2		T105	14		T277	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T94	11		T102	12		T202	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T82	14		T101	1		T99	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T84	3		T90	13		T160	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T40	1		T41	9		T103	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1041	1			T20	24		T39	1		T136	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T87	2		T115	21		T161	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T81	6		T87	7		T82	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T14	4		T94	2		T173	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T82	12		T94	2		T101	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T21	4		T93	14		T84	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T246	11		T258	4		T278	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T22	10		T93	8		T86	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T5	2		T28	1		T32	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T94	4		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T22	10		T275	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T103	3		T238	1		T237	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T279	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T195	1		T140	10		T202	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T88	1		T120	1		T97	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T87	8		T201	1		T192	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T81	17		T88	1		T89	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T81	8		T88	1		T197	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T12	1		T95	8		T104	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T12	1		T39	3		T79	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T24	9		T150	14		T218	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T39	2		T94	12		T102	29
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T57	1		T40	2		T101	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T84	1		T90	11		T224	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T82	13		T41	10		T103	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T105	11		T139	1		T141	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T12	1		T22	1		T87	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T39	6		T81	9		T87	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T14	5		T56	1		T57	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1422	1			T15	17		T18	2		T20	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	379	1			T14	2		T21	1		T93	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16129	1			T13	153		T14	10		T16	120
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T94	2		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T22	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T103	11		T238	1		T237	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T195	1		T140	10		T202	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T208	1		T280	8		T281	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T87	8		T201	1		T236	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T81	20		T89	2		T102	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T173	3		T206	2		T205	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T103	3		T143	2		T238	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T39	2		T79	1		T41	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T24	2		T150	10		T277	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T39	1		T94	11		T102	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T40	1		T101	1		T105	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T84	3		T90	13		T160	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T82	14		T41	9		T103	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T105	9		T141	7		T107	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T87	2		T161	8		T236	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T39	1		T81	6		T87	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T14	4		T173	6		T115	22
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1096	1			T20	24		T82	12		T101	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	419	1			T21	4		T93	22		T94	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T5	2		T28	1		T32	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T195	2		T201	2		T103	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T81	21		T88	2		T89	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T81	1		T87	9		T88	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T12	1		T85	1		T86	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T12	1		T39	4		T41	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T150	11		T95	1		T104	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T39	3		T79	7		T102	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T24	8		T218	1		T105	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T94	12		T102	13		T96	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T57	1		T82	15		T101	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T84	4		T90	14		T224	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T40	2		T41	10		T103	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1378	1			T15	2		T18	2		T20	26
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T22	1		T56	1		T87	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T81	7		T87	8		T82	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T12	1		T14	6		T94	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T82	13		T94	3		T83	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	366	1			T14	2		T21	5		T57	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T246	12		T223	1		T258	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T22	11		T93	9		T86	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16282	1			T5	2		T28	1		T32	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T103	2		T96	5		T140	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T81	16		T89	3		T97	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T81	7		T87	7		T209	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T85	14		T102	4		T103	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T39	1		T41	2		T104	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T150	13		T95	7		T104	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T79	1		T102	14		T215	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T24	3		T218	3		T105	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T94	11		T102	13		T96	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T82	12		T109	15		T123	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T90	10		T128	8		T160	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T40	1		T41	9		T103	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1056	1			T15	15		T23	17		T46	30
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T87	7		T83	7		T95	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T81	8		T87	7		T82	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T14	3		T91	12		T211	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T82	4		T94	3		T83	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T84	13		T90	2		T91	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T246	12		T223	13		T258	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T22	9		T86	4		T115	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T264	13		T282	2		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T94	3		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T22	11		T275	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T103	12		T238	2		T237	19
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T279	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T195	2		T140	11		T202	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T88	1		T120	1		T97	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T87	9		T201	2		T192	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T81	21		T88	1		T89	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T81	1		T88	1		T197	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T12	1		T95	1		T104	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T12	1		T39	4		T79	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T24	8		T150	11		T218	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T39	3		T94	12		T102	25
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T57	1		T40	2		T101	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T84	4		T90	14		T224	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T82	15		T41	10		T103	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T105	10		T139	1		T141	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T12	1		T22	1		T87	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T39	3		T81	7		T87	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T14	6		T56	1		T57	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1455	1			T15	2		T18	2		T20	26
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	498	1			T14	2		T21	5		T93	24
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16275	1			T5	2		T28	1		T32	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T94	3		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T22	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T103	2		T237	14		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T140	9		T239	3		T188	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T97	1		T280	8		T281	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T87	7		T96	5		T209	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T81	16		T89	3		T85	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T81	7		T277	1		T203	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T95	7		T104	6		T177	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T39	1		T79	1		T41	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T24	3		T150	13		T218	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T94	11		T102	27		T220	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T40	1		T105	5		T241	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T90	10		T96	17		T128	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T82	12		T41	9		T103	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T105	10		T141	12		T107	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T87	7		T83	7		T95	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T39	4		T81	8		T87	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T14	3		T91	12		T115	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1063	1			T15	15		T23	17		T46	30
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T84	13		T90	2		T91	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21184

1

T5

2

T28

1

T32

3

auto[1]

auto[0]

3485

1

T14

3

T15

15

T22

9