Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24669

1

T5

2

T28

1

T32

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21465

1

T5

2

T28

1

T32

3

auto[ADC_CTRL_FILTER_COND_OUT]

3204

1

T12

2

T21

5

T22

20

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19082

1

T5

2

T28

1

T32

3

auto[1]

5587

1

T12

3

T14

2

T15

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20678

1

T12

3

T13

153

T14

17

auto[1]

3991

1

T5

2

T28

1

T32

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	335	1			T12	1		T21	5		T22	1
values[0]	2	1			T115	2		-	-		-	-
values[1]	768	1			T22	20		T56	1		T39	7
values[2]	420	1			T39	5		T81	15		T87	15
values[3]	855	1			T82	17		T83	8		T89	7
values[4]	575	1			T93	15		T87	10		T79	8
values[5]	574	1			T24	11		T39	3		T57	1
values[6]	622	1			T93	9		T82	27		T88	1
values[7]	689	1			T81	45		T94	23		T83	5
values[8]	2547	1			T12	1		T14	2		T15	17
values[9]	1007	1			T12	1		T14	9		T87	16
minimum	16275	1			T5	2		T28	1		T32	3

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	618	1			T56	1		T86	1		T104	7
values[1]	596	1			T39	5		T81	15		T87	15
values[2]	756	1			T82	17		T41	19		T83	8
values[3]	524	1			T93	15		T87	10		T79	8
values[4]	644	1			T24	11		T39	3		T57	1
values[5]	537	1			T93	9		T82	27		T88	1
values[6]	2755	1			T12	1		T15	17		T18	2
values[7]	534	1			T14	11		T102	26		T105	20
values[8]	1087	1			T12	2		T21	5		T22	1
values[9]	92	1			T222	1		T145	1		T227	19
minimum	16526	1			T5	2		T28	1		T32	3

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21184

1

T5

2

T28

1

T32

3

auto[1]

3485

1

T14

3

T15

15

T22

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T56	1		T86	1		T143	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T104	7		T212	1		T120	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T81	9		T120	1		T163	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T39	3		T87	8		T40	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T177	8		T224	1		T105	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T82	5		T41	10		T83	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T93	1		T79	7		T86	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T87	8		T96	12		T121	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T24	9		T57	1		T197	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T39	2		T150	14		T88	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T88	1		T90	11		T195	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T93	1		T82	13		T83	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1434	1			T12	1		T15	17		T18	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T218	4		T95	13		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T14	7		T102	14		T105	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T140	10		T141	13		T127	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	341	1			T22	1		T94	1		T84	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T12	2		T21	1		T87	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T222	1		T232	12		T243	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T145	1		T227	1		T231	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16183	1			T13	153		T14	10		T16	120
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T22	10		T39	6		T57	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T107	6		T130	11		T100	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T236	15		T269	15		T147	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T81	6		T163	1		T198	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T39	2		T87	7		T40	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T105	5		T116	3		T106	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T82	12		T41	9		T90	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T93	14		T79	1		T115	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T87	2		T107	3		T214	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T24	2		T85	1		T195	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T39	1		T150	10		T84	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T195	9		T173	9		T161	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T93	8		T82	14		T101	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1105	1			T20	24		T81	20		T94	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T166	14		T161	12		T163	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T14	4		T102	12		T105	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T140	10		T141	7		T143	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T94	2		T84	3		T101	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T21	4		T87	8		T82	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T229	4		T230	15		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T227	18		T231	1		T244	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T5	2		T28	1		T32	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T22	10		T39	1		T115	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T22	1		T85	15		T101	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T12	1		T21	1		T177	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T115	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T56	1		T128	9		T143	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T22	10		T39	6		T57	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T81	9		T86	1		T120	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T39	3		T87	8		T40	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T177	8		T224	1		T105	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T82	5		T83	8		T89	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T93	1		T79	7		T115	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T87	8		T41	10		T192	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T24	9		T57	1		T197	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T39	2		T150	14		T88	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T88	1		T90	11		T195	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T93	1		T82	13		T101	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T81	25		T94	12		T86	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T83	5		T218	4		T95	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1313	1			T12	1		T14	2		T15	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T140	10		T127	1		T166	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T14	5		T94	1		T84	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T12	1		T87	8		T82	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16129	1			T13	153		T14	10		T16	120
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T101	1		T161	12		T283	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T21	4		T103	11		T160	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T115	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T118	9		T107	6		T130	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T22	10		T39	1		T236	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T81	6		T163	1		T198	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T39	2		T87	7		T40	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T105	5		T116	3		T246	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T82	12		T89	2		T90	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T93	14		T79	1		T115	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T87	2		T41	9		T118	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T24	2		T85	1		T103	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T39	1		T150	10		T84	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T195	10		T173	3		T102	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T93	8		T82	14		T101	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T81	20		T94	11		T86	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T161	12		T163	10		T99	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	991	1			T20	24		T102	12		T201	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T140	10		T166	14		T143	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T14	4		T94	2		T84	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T87	8		T82	11		T90	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T5	2		T28	1		T32	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T56	1		T86	1		T143	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T104	1		T212	1		T120	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T81	7		T120	1		T163	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T39	4		T87	8		T40	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T177	1		T224	1		T105	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T82	13		T41	10		T83	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T93	15		T79	7		T86	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T87	3		T96	1		T121	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T24	8		T57	1		T197	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T39	3		T150	11		T88	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T88	1		T90	1		T195	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T93	9		T82	15		T83	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1454	1			T12	1		T15	2		T18	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T218	1		T95	1		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T14	8		T102	13		T105	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T140	11		T141	8		T127	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T22	1		T94	3		T84	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T12	2		T21	5		T87	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T222	1		T232	1		T243	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T145	1		T227	19		T231	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16335	1			T5	2		T28	1		T32	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T22	11		T39	3		T57	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T107	11		T130	7		T220	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T104	6		T236	14		T270	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T81	8		T223	13		T130	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T39	1		T87	7		T40	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T177	7		T140	6		T116	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T82	4		T41	9		T83	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T79	1		T115	13		T215	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T87	7		T96	11		T121	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T24	3		T102	4		T213	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T150	13		T84	13		T91	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T90	10		T195	1		T161	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T82	12		T83	4		T101	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1085	1			T15	15		T23	17		T46	30
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T218	3		T95	12		T163	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T14	3		T102	13		T105	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T140	9		T141	12		T240	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T85	14		T104	5		T105	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T87	7		T82	9		T90	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T232	11		T243	9		T229	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T244	11		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T128	8		T125	15		T284	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T22	9		T39	4		T121	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T22	1		T85	1		T101	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T12	1		T21	5		T177	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T115	2		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T56	1		T128	1		T143	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T22	11		T39	3		T57	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T81	7		T86	1		T120	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T39	4		T87	8		T40	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T177	1		T224	1		T105	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T82	13		T83	1		T89	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T93	15		T79	7		T115	22
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T87	3		T41	10		T192	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T24	8		T57	1		T197	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T39	3		T150	11		T88	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T88	1		T90	1		T195	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T93	9		T82	15		T101	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T81	22		T94	12		T86	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T83	1		T218	1		T95	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1322	1			T12	1		T14	2		T15	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T140	11		T127	1		T166	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T14	6		T94	3		T84	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T12	1		T87	9		T82	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16275	1			T5	2		T28	1		T32	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T85	14		T161	10		T241	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T177	12		T103	2		T96	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T128	8		T107	11		T130	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T22	9		T39	4		T104	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T81	8		T130	9		T237	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T39	1		T87	7		T40	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T177	7		T116	2		T246	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T82	4		T83	7		T89	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T79	1		T115	13		T140	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T87	7		T41	9		T96	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T24	3		T103	3		T204	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T150	13		T84	13		T91	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T90	10		T195	1		T102	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T82	12		T101	4		T116	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T81	23		T94	11		T86	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T83	4		T218	3		T95	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	982	1			T15	15		T23	17		T46	30
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T140	9		T240	13		T248	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T14	3		T104	5		T105	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T87	7		T82	9		T90	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21184

1

T5

2

T28

1

T32

3

auto[1]

auto[0]

3485

1

T14

3

T15

15

T22

9