Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24669

1

T5

2

T28

1

T32

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21329

1

T5

2

T28

1

T32

3

auto[ADC_CTRL_FILTER_COND_OUT]

3340

1

T12

3

T39

3

T57

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18824

1

T5

2

T28

1

T32

3

auto[1]

5845

1

T12

3

T13

5

T15

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20678

1

T12

3

T13

153

T14

17

auto[1]

3991

1

T5

2

T28

1

T32

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	641	1			T13	5		T14	2		T16	13
values[0]	24	1			T116	22		T98	1		T292	1
values[1]	561	1			T86	1		T95	13		T192	1
values[2]	2696	1			T12	1		T15	17		T18	2
values[3]	770	1			T14	9		T93	15		T82	27
values[4]	747	1			T39	10		T87	16		T90	24
values[5]	576	1			T88	1		T83	5		T85	2
values[6]	634	1			T12	1		T22	1		T82	21
values[7]	649	1			T39	5		T57	1		T81	45
values[8]	929	1			T12	1		T57	1		T81	15
values[9]	567	1			T21	5		T56	1		T93	9
minimum	15875	1			T5	2		T28	1		T32	3

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	617	1			T12	1		T24	11		T87	15
values[1]	2668	1			T14	9		T15	17		T18	2
values[2]	781	1			T39	3		T93	15		T82	27
values[3]	699	1			T39	7		T87	16		T88	1
values[4]	661	1			T82	21		T90	11		T91	16
values[5]	505	1			T12	1		T22	1		T87	10
values[6]	715	1			T39	5		T57	1		T81	45
values[7]	878	1			T12	1		T57	1		T81	15
values[8]	605	1			T14	2		T21	5		T22	20
values[9]	84	1			T193	12		T194	1		T100	16
minimum	16456	1			T5	2		T28	1		T32	3

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21184

1

T5

2

T28

1

T32

3

auto[1]

3485

1

T14

3

T15

15

T22

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T24	9		T82	5		T86	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T12	1		T87	8		T88	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1429	1			T14	5		T15	17		T18	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T88	1		T177	13		T127	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T82	13		T94	12		T213	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T39	2		T93	1		T94	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T39	6		T88	1		T83	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T87	8		T85	1		T90	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T91	16		T86	5		T104	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T82	10		T90	11		T105	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T22	1		T87	8		T197	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T12	1		T173	1		T102	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T39	3		T79	7		T150	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T57	1		T81	25		T83	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T81	9		T94	4		T41	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T12	1		T57	1		T90	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T14	2		T21	1		T22	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T93	1		T40	2		T101	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T194	1		T200	1		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T193	12		T100	9		T123	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16184	1			T13	153		T14	10		T16	120
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T192	1		T161	1		T98	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T24	2		T82	12		T201	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T87	7		T215	12		T163	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1089	1			T14	4		T20	24		T41	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T106	7		T293	6		T294	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T82	14		T94	11		T213	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T39	1		T93	14		T94	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T39	1		T105	5		T209	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T87	8		T85	1		T90	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T86	9		T102	12		T206	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T82	11		T105	14		T202	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T87	2		T236	11		T117	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T173	3		T102	11		T120	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T39	2		T79	1		T150	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T81	20		T89	2		T101	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T81	6		T94	2		T41	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T90	17		T103	3		T105	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T21	4		T22	10		T173	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T93	8		T40	1		T101	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T100	7		T123	10		T294	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T5	2		T28	1		T32	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T161	12		T99	15		T295	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	468	1			T13	5		T14	2		T16	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T40	2		T239	4		T100	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T116	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T98	1		T292	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T86	1		T212	1		T202	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T95	13		T192	1		T96	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1409	1			T15	17		T18	2		T20	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T12	1		T87	8		T88	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T14	5		T82	13		T94	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T93	1		T94	1		T84	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T39	6		T103	12		T105	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T39	2		T87	8		T90	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T88	1		T83	5		T91	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T85	1		T90	11		T202	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T22	1		T197	1		T91	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T12	1		T82	10		T102	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T39	3		T87	8		T79	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T57	1		T81	25		T83	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T81	9		T94	4		T96	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T12	1		T57	1		T89	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T21	1		T56	1		T41	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T93	1		T101	5		T104	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15729	1			T13	148		T14	10		T16	107
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T22	10		T238	3		T214	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T40	1		T239	4		T100	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T116	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T202	13		T118	18		T144	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T215	12		T161	12		T163	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1052	1			T20	24		T24	2		T82	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T87	7		T106	7		T237	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T14	4		T82	14		T94	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T93	14		T94	2		T84	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T39	1		T103	3		T105	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T39	1		T87	8		T90	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T86	9		T102	12		T204	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T85	1		T202	12		T296	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T206	2		T236	11		T207	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T82	11		T102	11		T105	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T39	2		T87	2		T79	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T81	20		T101	1		T173	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T81	6		T94	2		T116	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T89	2		T90	17		T105	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T21	4		T41	4		T173	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T93	8		T101	3		T141	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T5	2		T28	1		T32	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T24	8		T82	13		T86	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T12	1		T87	8		T88	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1438	1			T14	6		T15	2		T18	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T88	1		T177	1		T127	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T82	15		T94	12		T213	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T39	3		T93	15		T94	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T39	3		T88	1		T83	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T87	9		T85	2		T90	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T91	2		T86	10		T104	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T82	12		T90	1		T105	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T22	1		T87	3		T197	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T12	1		T173	4		T102	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T39	4		T79	7		T150	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T57	1		T81	22		T83	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T81	7		T94	3		T41	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T12	1		T57	1		T90	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T14	2		T21	5		T22	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T93	9		T40	2		T101	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T194	1		T200	1		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T193	1		T100	8		T123	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16331	1			T5	2		T28	1		T32	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T192	1		T161	13		T98	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T24	3		T82	4		T115	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T87	7		T95	12		T96	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1080	1			T14	3		T15	15		T23	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T177	12		T293	6		T294	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T82	12		T94	11		T213	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T84	13		T218	3		T101	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T39	4		T83	4		T116	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T87	7		T90	10		T160	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T91	14		T86	4		T104	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T82	9		T90	10		T105	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T87	7		T207	7		T217	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T102	14		T96	17		T120	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T39	1		T79	1		T150	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T81	23		T83	7		T89	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T81	8		T94	3		T41	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T90	2		T177	7		T103	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T22	9		T85	14		T95	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T40	1		T101	4		T104	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T193	11		T100	8		T123	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T116	11		T297	11		T298	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T295	10		T299	11		T300	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	494	1			T13	5		T14	2		T16	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T40	2		T239	5		T100	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T116	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T98	1		T292	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T86	1		T212	1		T202	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T95	1		T192	1		T96	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1402	1			T15	2		T18	2		T20	26
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T12	1		T87	8		T88	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T14	6		T82	15		T94	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T93	15		T94	3		T84	20
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T39	3		T103	4		T105	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T39	3		T87	9		T90	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T88	1		T83	1		T91	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T85	2		T90	1		T202	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T22	1		T197	1		T91	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T12	1		T82	12		T102	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T39	4		T87	3		T79	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T57	1		T81	22		T83	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T81	7		T94	3		T96	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T12	1		T57	1		T89	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T21	5		T56	1		T41	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T93	9		T101	4		T104	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15875	1			T5	2		T28	1		T32	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T22	9		T128	9		T238	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T40	1		T239	3		T100	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T116	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T297	11		T258	3		T301	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T95	12		T96	11		T215	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1059	1			T15	15		T23	17		T24	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T87	7		T223	13		T237	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T14	3		T82	12		T94	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T84	13		T218	3		T101	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T39	4		T103	11		T116	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T87	7		T90	10		T160	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T83	4		T91	2		T86	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T90	10		T296	11		T164	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T91	12		T207	7		T217	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T82	9		T102	14		T96	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T39	1		T87	7		T79	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T81	23		T83	7		T103	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T81	8		T94	3		T96	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T89	3		T90	2		T177	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T41	2		T85	14		T95	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T101	4		T104	6		T141	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21184

1

T5

2

T28

1

T32

3

auto[1]

auto[0]

3485

1

T14

3

T15

15

T22

9