Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24669

1

T5

2

T28

1

T32

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21434

1

T5

2

T28

1

T32

3

auto[ADC_CTRL_FILTER_COND_OUT]

3235

1

T12

2

T14

9

T21

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19070

1

T5

2

T28

1

T32

3

auto[1]

5599

1

T12

3

T14

9

T15

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20678

1

T12

3

T13

153

T14

17

auto[1]

3991

1

T5

2

T28

1

T32

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	7	1			T302	4		T303	3		-	-
values[0]	47	1			T236	1		T281	15		T304	24
values[1]	700	1			T24	11		T39	7		T87	16
values[2]	821	1			T56	1		T93	9		T82	27
values[3]	365	1			T81	8		T94	6		T88	1
values[4]	749	1			T87	15		T79	8		T84	4
values[5]	2546	1			T12	1		T15	17		T18	2
values[6]	661	1			T81	37		T93	15		T88	1
values[7]	645	1			T12	1		T22	21		T150	24
values[8]	649	1			T39	5		T81	15		T197	1
values[9]	1204	1			T12	1		T14	11		T21	5
minimum	16275	1			T5	2		T28	1		T32	3

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	974	1			T24	11		T39	7		T87	16
values[1]	696	1			T81	8		T93	9		T94	23
values[2]	439	1			T56	1		T94	9		T88	1
values[3]	2882	1			T12	1		T15	17		T18	2
values[4]	465	1			T39	3		T57	1		T93	15
values[5]	632	1			T81	37		T85	2		T91	13
values[6]	600	1			T12	1		T22	21		T150	24
values[7]	753	1			T39	5		T81	15		T40	3
values[8]	790	1			T14	11		T87	10		T82	17
values[9]	158	1			T12	1		T21	5		T57	1
minimum	16280	1			T5	2		T28	1		T32	3

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21184

1

T5

2

T28

1

T32

3

auto[1]

3485

1

T14

3

T15

15

T22

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T24	9		T87	8		T82	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T39	6		T82	10		T83	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T81	8		T93	1		T94	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T102	14		T96	6		T120	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T56	1		T94	5		T88	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T105	11		T140	1		T161	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1397	1			T12	1		T15	17		T18	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T79	7		T84	1		T90	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T57	1		T93	1		T127	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T39	2		T88	1		T236	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T204	8		T128	9		T129	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T81	17		T85	1		T91	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T22	1		T150	14		T88	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T12	1		T22	10		T84	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T39	3		T40	2		T85	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T81	9		T197	1		T102	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T14	2		T87	8		T82	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T14	5		T41	10		T101	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T57	1		T209	1		T99	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T12	1		T21	1		T211	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16130	1			T13	153		T14	10		T16	120
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T299	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T24	2		T87	8		T82	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T39	1		T82	11		T101	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T93	8		T94	11		T103	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T102	12		T120	17		T238	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T94	4		T195	9		T143	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T105	9		T161	8		T238	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1055	1			T20	24		T87	7		T173	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T79	1		T84	3		T166	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T93	14		T209	8		T116	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T39	1		T236	26		T208	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T204	7		T198	12		T146	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T81	20		T85	1		T195	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T150	10		T188	5		T116	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T22	10		T84	15		T115	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T39	2		T40	1		T90	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T81	6		T102	5		T115	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T87	2		T82	12		T89	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T14	4		T41	9		T101	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T209	12		T99	8		T217	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T21	4		T202	12		T208	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T5	2		T28	1		T32	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T299	1		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T303	2		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T302	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T236	1		T281	2		T304	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T275	2		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T24	9		T87	8		T41	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T39	6		T82	10		T83	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T56	1		T93	1		T82	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T102	14		T201	1		T96	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T81	8		T94	4		T88	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T105	11		T143	1		T241	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T87	8		T195	7		T173	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T79	7		T84	1		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1268	1			T12	1		T15	17		T18	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T39	2		T90	11		T127	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T93	1		T127	1		T128	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T81	17		T88	1		T85	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T22	1		T150	14		T88	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T12	1		T22	10		T84	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T39	3		T90	3		T86	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T81	9		T197	1		T96	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T14	2		T57	1		T87	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	338	1			T12	1		T14	5		T21	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16129	1			T13	153		T14	10		T16	120
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T303	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T281	13		T304	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T275	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T24	2		T87	8		T41	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T39	1		T82	11		T101	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T93	8		T82	14		T94	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T102	12		T201	1		T120	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T94	2		T143	2		T305	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T105	9		T99	15		T208	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T87	7		T195	9		T173	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T79	1		T84	3		T166	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1008	1			T20	24		T136	10		T137	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T39	1		T205	8		T236	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T93	14		T116	3		T277	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T81	20		T85	1		T195	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T150	10		T204	7		T116	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T22	10		T84	15		T209	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T39	2		T90	17		T103	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T81	6		T115	22		T117	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T87	2		T82	12		T40	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T14	4		T21	4		T41	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T5	2		T28	1		T32	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T24	8		T87	9		T82	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	359	1			T39	3		T82	12		T83	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T81	1		T93	9		T94	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T102	13		T96	1		T120	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T56	1		T94	6		T88	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T105	10		T140	1		T161	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1391	1			T12	1		T15	2		T18	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T79	7		T84	4		T90	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T57	1		T93	15		T127	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T39	3		T88	1		T236	28
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T204	12		T128	1		T129	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T81	21		T85	2		T91	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T22	1		T150	11		T88	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T12	1		T22	11		T84	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T39	4		T40	2		T85	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T81	7		T197	1		T102	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T14	2		T87	3		T82	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T14	6		T41	10		T101	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T57	1		T209	13		T99	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T12	1		T21	5		T211	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16278	1			T5	2		T28	1		T32	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T299	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T24	3		T87	7		T82	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T39	4		T82	9		T83	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T81	7		T94	11		T218	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T102	13		T96	5		T120	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T94	3		T83	4		T195	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T105	10		T161	2		T238	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1061	1			T15	15		T23	17		T46	30
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T79	1		T90	10		T160	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T209	1		T116	2		T277	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T236	14		T121	11		T264	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T204	3		T128	8		T241	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T81	16		T91	12		T95	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T150	13		T128	9		T188	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T22	9		T84	13		T104	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T39	1		T40	1		T85	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T81	8		T102	4		T96	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T87	7		T82	4		T89	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T14	3		T41	9		T101	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T217	3		T284	15		T303	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T211	2		T125	2		T306	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T303	2		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T302	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T236	1		T281	14		T304	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T275	6		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T24	8		T87	9		T41	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T39	3		T82	12		T83	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T56	1		T93	9		T82	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T102	13		T201	2		T96	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T81	1		T94	3		T88	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T105	10		T143	1		T241	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T87	8		T195	15		T173	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T79	7		T84	4		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1330	1			T12	1		T15	2		T18	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T39	3		T90	1		T127	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T93	15		T127	1		T128	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T81	21		T88	1		T85	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T22	1		T150	11		T88	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T12	1		T22	11		T84	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	322	1			T39	4		T90	18		T86	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T81	7		T197	1		T96	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	377	1			T14	2		T57	1		T87	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T12	1		T14	6		T21	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16275	1			T5	2		T28	1		T32	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T303	1		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T302	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T281	1		T304	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T24	3		T87	7		T41	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T39	4		T82	9		T83	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T82	12		T94	11		T91	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T102	13		T96	5		T120	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T81	7		T94	3		T83	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T105	10		T241	5		T123	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T87	7		T195	1		T115	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T79	1		T160	9		T161	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	946	1			T15	15		T23	17		T46	30
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T90	10		T121	17		T264	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T128	8		T241	10		T116	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T81	16		T91	12		T177	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T150	13		T204	3		T128	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T22	9		T84	13		T95	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T39	1		T90	2		T103	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T81	8		T96	17		T115	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T87	7		T82	4		T40	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T14	3		T41	9		T101	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21184

1

T5

2

T28

1

T32

3

auto[1]

auto[0]

3485

1

T14

3

T15

15

T22

9