Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.55 98.98 95.70 100.00 100.00 98.18 98.64 91.37


Total test records in report: 913
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T341 /workspace/coverage/default/2.adc_ctrl_clock_gating.3437225365 Dec 31 12:32:10 PM PST 23 Dec 31 12:35:31 PM PST 23 487755799934 ps
T772 /workspace/coverage/default/26.adc_ctrl_stress_all.2580478172 Dec 31 12:32:44 PM PST 23 Dec 31 12:40:16 PM PST 23 183645134122 ps
T773 /workspace/coverage/default/40.adc_ctrl_alert_test.1038190410 Dec 31 12:33:33 PM PST 23 Dec 31 12:33:39 PM PST 23 296802152 ps
T774 /workspace/coverage/default/14.adc_ctrl_poweron_counter.1171205346 Dec 31 12:32:12 PM PST 23 Dec 31 12:32:15 PM PST 23 3181359638 ps
T775 /workspace/coverage/default/38.adc_ctrl_stress_all.78750385 Dec 31 12:33:28 PM PST 23 Dec 31 12:39:27 PM PST 23 122758334281 ps
T776 /workspace/coverage/default/20.adc_ctrl_smoke.3958849936 Dec 31 12:32:57 PM PST 23 Dec 31 12:33:06 PM PST 23 5981097558 ps
T777 /workspace/coverage/default/0.adc_ctrl_filters_interrupt.1189544568 Dec 31 12:31:50 PM PST 23 Dec 31 12:50:45 PM PST 23 493701286564 ps
T778 /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.3804045673 Dec 31 12:32:56 PM PST 23 Dec 31 12:50:14 PM PST 23 486931366272 ps
T779 /workspace/coverage/default/20.adc_ctrl_lowpower_counter.2429647905 Dec 31 12:32:17 PM PST 23 Dec 31 12:33:26 PM PST 23 29984563422 ps
T780 /workspace/coverage/default/10.adc_ctrl_smoke.1250555890 Dec 31 12:32:30 PM PST 23 Dec 31 12:32:47 PM PST 23 5976569341 ps
T781 /workspace/coverage/default/7.adc_ctrl_fsm_reset.3155639360 Dec 31 12:32:33 PM PST 23 Dec 31 12:44:04 PM PST 23 139535735090 ps
T322 /workspace/coverage/default/14.adc_ctrl_filters_both.2530019283 Dec 31 12:32:11 PM PST 23 Dec 31 12:38:57 PM PST 23 335126626092 ps
T782 /workspace/coverage/default/34.adc_ctrl_filters_interrupt.1024478314 Dec 31 12:32:53 PM PST 23 Dec 31 12:45:18 PM PST 23 326216145045 ps
T783 /workspace/coverage/default/17.adc_ctrl_filters_interrupt.1817528705 Dec 31 12:32:27 PM PST 23 Dec 31 12:35:53 PM PST 23 327669730261 ps
T784 /workspace/coverage/default/6.adc_ctrl_fsm_reset.2712608359 Dec 31 12:32:05 PM PST 23 Dec 31 12:38:32 PM PST 23 110045794818 ps
T785 /workspace/coverage/default/25.adc_ctrl_filters_interrupt.2315915684 Dec 31 12:32:50 PM PST 23 Dec 31 12:46:39 PM PST 23 333362444687 ps
T229 /workspace/coverage/default/6.adc_ctrl_clock_gating.2166647606 Dec 31 12:32:00 PM PST 23 Dec 31 12:44:22 PM PST 23 505489063218 ps
T786 /workspace/coverage/default/27.adc_ctrl_filters_interrupt.1466607484 Dec 31 12:32:37 PM PST 23 Dec 31 12:46:17 PM PST 23 329832445194 ps
T787 /workspace/coverage/default/14.adc_ctrl_clock_gating.3909761697 Dec 31 12:32:17 PM PST 23 Dec 31 12:32:36 PM PST 23 163189515116 ps
T788 /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.2830969396 Dec 31 12:32:10 PM PST 23 Dec 31 12:34:37 PM PST 23 334048043913 ps
T199 /workspace/coverage/default/35.adc_ctrl_filters_polled.2233388592 Dec 31 12:33:01 PM PST 23 Dec 31 12:45:55 PM PST 23 329424619851 ps
T789 /workspace/coverage/default/21.adc_ctrl_filters_polled.455982859 Dec 31 12:32:35 PM PST 23 Dec 31 12:35:55 PM PST 23 332935165616 ps
T790 /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.2562287985 Dec 31 12:32:07 PM PST 23 Dec 31 12:37:54 PM PST 23 159069281109 ps
T791 /workspace/coverage/default/40.adc_ctrl_poweron_counter.2919343743 Dec 31 12:33:07 PM PST 23 Dec 31 12:33:15 PM PST 23 3940361615 ps
T792 /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.2557751174 Dec 31 12:33:43 PM PST 23 Dec 31 12:38:55 PM PST 23 658244888975 ps
T793 /workspace/coverage/default/2.adc_ctrl_filters_interrupt.1251741451 Dec 31 12:32:47 PM PST 23 Dec 31 12:42:55 PM PST 23 496975158407 ps
T794 /workspace/coverage/default/31.adc_ctrl_poweron_counter.2984407226 Dec 31 12:33:00 PM PST 23 Dec 31 12:33:04 PM PST 23 4062908964 ps
T795 /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.3015782459 Dec 31 12:33:21 PM PST 23 Dec 31 12:35:40 PM PST 23 91742309112 ps
T796 /workspace/coverage/default/4.adc_ctrl_poweron_counter.993720056 Dec 31 12:32:10 PM PST 23 Dec 31 12:32:15 PM PST 23 5059698750 ps
T797 /workspace/coverage/default/49.adc_ctrl_fsm_reset.4024011921 Dec 31 12:33:40 PM PST 23 Dec 31 12:41:15 PM PST 23 87813026604 ps
T798 /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.2087344618 Dec 31 12:33:15 PM PST 23 Dec 31 12:39:26 PM PST 23 158948027860 ps
T799 /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.3824202707 Dec 31 12:32:23 PM PST 23 Dec 31 12:37:04 PM PST 23 497120136040 ps
T279 /workspace/coverage/default/39.adc_ctrl_stress_all.2917006320 Dec 31 12:33:33 PM PST 23 Dec 31 12:37:58 PM PST 23 531014533457 ps
T800 /workspace/coverage/default/8.adc_ctrl_clock_gating.621316139 Dec 31 12:32:18 PM PST 23 Dec 31 12:40:56 PM PST 23 516150408160 ps
T801 /workspace/coverage/default/31.adc_ctrl_clock_gating.3080229487 Dec 31 12:32:38 PM PST 23 Dec 31 12:35:18 PM PST 23 327722867524 ps
T802 /workspace/coverage/default/11.adc_ctrl_filters_polled.543151181 Dec 31 12:31:59 PM PST 23 Dec 31 12:36:56 PM PST 23 491794920924 ps
T803 /workspace/coverage/default/26.adc_ctrl_alert_test.279385309 Dec 31 12:32:43 PM PST 23 Dec 31 12:32:45 PM PST 23 353783617 ps
T804 /workspace/coverage/default/25.adc_ctrl_stress_all.1420507264 Dec 31 12:33:44 PM PST 23 Dec 31 12:41:59 PM PST 23 94555367163 ps
T805 /workspace/coverage/default/46.adc_ctrl_alert_test.1018285354 Dec 31 12:33:51 PM PST 23 Dec 31 12:33:54 PM PST 23 486592796 ps
T230 /workspace/coverage/default/23.adc_ctrl_filters_interrupt.1385544009 Dec 31 12:32:37 PM PST 23 Dec 31 12:45:56 PM PST 23 329154966228 ps
T806 /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.2686012831 Dec 31 12:32:42 PM PST 23 Dec 31 12:35:49 PM PST 23 163766571927 ps
T807 /workspace/coverage/default/43.adc_ctrl_filters_wakeup.3491797125 Dec 31 12:33:09 PM PST 23 Dec 31 12:35:51 PM PST 23 326459026094 ps
T808 /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.2210415024 Dec 31 12:31:50 PM PST 23 Dec 31 12:34:59 PM PST 23 165618789938 ps
T809 /workspace/coverage/default/17.adc_ctrl_stress_all.3431069277 Dec 31 12:32:24 PM PST 23 Dec 31 12:39:38 PM PST 23 333946875220 ps
T810 /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.3252572746 Dec 31 12:32:56 PM PST 23 Dec 31 12:42:30 PM PST 23 497794470929 ps
T285 /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.1469603358 Dec 31 12:33:43 PM PST 23 Dec 31 12:37:41 PM PST 23 124338947501 ps
T287 /workspace/coverage/default/39.adc_ctrl_filters_interrupt.2517458998 Dec 31 12:33:18 PM PST 23 Dec 31 12:43:09 PM PST 23 493963821831 ps
T189 /workspace/coverage/default/25.adc_ctrl_fsm_reset.2519660316 Dec 31 12:32:41 PM PST 23 Dec 31 12:39:40 PM PST 23 97567219314 ps
T811 /workspace/coverage/default/33.adc_ctrl_fsm_reset.1802857214 Dec 31 12:33:07 PM PST 23 Dec 31 12:44:20 PM PST 23 119267745104 ps
T267 /workspace/coverage/default/9.adc_ctrl_filters_interrupt.337642957 Dec 31 12:32:12 PM PST 23 Dec 31 12:34:47 PM PST 23 337839070666 ps
T812 /workspace/coverage/default/20.adc_ctrl_fsm_reset.2903236943 Dec 31 12:32:47 PM PST 23 Dec 31 12:38:32 PM PST 23 83026637632 ps
T813 /workspace/coverage/default/19.adc_ctrl_poweron_counter.1531089004 Dec 31 12:32:40 PM PST 23 Dec 31 12:32:44 PM PST 23 4109542904 ps
T814 /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.1988970550 Dec 31 12:34:13 PM PST 23 Dec 31 12:37:30 PM PST 23 329288665781 ps
T210 /workspace/coverage/default/7.adc_ctrl_filters_interrupt.1203384354 Dec 31 12:31:48 PM PST 23 Dec 31 12:32:18 PM PST 23 159812456775 ps
T815 /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.853933885 Dec 31 12:32:48 PM PST 23 Dec 31 12:50:26 PM PST 23 491478815643 ps
T816 /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.3889281839 Dec 31 12:33:38 PM PST 23 Dec 31 12:36:46 PM PST 23 498562709896 ps
T817 /workspace/coverage/default/21.adc_ctrl_lowpower_counter.2783983899 Dec 31 12:32:43 PM PST 23 Dec 31 12:33:13 PM PST 23 37356431279 ps
T289 /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.2570806567 Dec 31 12:32:00 PM PST 23 Dec 31 12:34:03 PM PST 23 129744305151 ps
T190 /workspace/coverage/default/42.adc_ctrl_fsm_reset.2506799176 Dec 31 12:33:29 PM PST 23 Dec 31 12:41:08 PM PST 23 143260802269 ps
T291 /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.543139655 Dec 31 12:32:55 PM PST 23 Dec 31 12:39:00 PM PST 23 120739557163 ps
T818 /workspace/coverage/default/45.adc_ctrl_poweron_counter.511372955 Dec 31 12:33:44 PM PST 23 Dec 31 12:33:48 PM PST 23 3420313739 ps
T819 /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.593460358 Dec 31 12:33:12 PM PST 23 Dec 31 12:39:45 PM PST 23 323638695794 ps
T820 /workspace/coverage/default/3.adc_ctrl_filters_interrupt.2730422618 Dec 31 12:33:32 PM PST 23 Dec 31 12:35:12 PM PST 23 481992027517 ps
T821 /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.3807131281 Dec 31 12:32:42 PM PST 23 Dec 31 12:42:09 PM PST 23 497118780433 ps
T822 /workspace/coverage/default/7.adc_ctrl_smoke.1569268213 Dec 31 12:32:14 PM PST 23 Dec 31 12:32:24 PM PST 23 6072649669 ps
T823 /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.2583299040 Dec 31 12:32:49 PM PST 23 Dec 31 12:34:30 PM PST 23 161794158766 ps
T824 /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.3041205849 Dec 31 12:33:40 PM PST 23 Dec 31 12:35:08 PM PST 23 29381280178 ps
T825 /workspace/coverage/default/14.adc_ctrl_smoke.3772232016 Dec 31 12:32:14 PM PST 23 Dec 31 12:32:21 PM PST 23 5962906852 ps
T826 /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.3590455164 Dec 31 12:33:04 PM PST 23 Dec 31 12:45:10 PM PST 23 324362788548 ps
T827 /workspace/coverage/default/43.adc_ctrl_filters_interrupt.548523100 Dec 31 12:33:26 PM PST 23 Dec 31 12:35:28 PM PST 23 169708970826 ps
T828 /workspace/coverage/default/33.adc_ctrl_clock_gating.804714179 Dec 31 12:32:49 PM PST 23 Dec 31 12:37:37 PM PST 23 489137121875 ps
T829 /workspace/coverage/default/7.adc_ctrl_stress_all.638591434 Dec 31 12:32:13 PM PST 23 Dec 31 12:43:06 PM PST 23 499615455687 ps
T830 /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.4136768077 Dec 31 12:33:27 PM PST 23 Dec 31 12:46:01 PM PST 23 324375995319 ps
T831 /workspace/coverage/default/6.adc_ctrl_poweron_counter.3225865884 Dec 31 12:32:42 PM PST 23 Dec 31 12:32:44 PM PST 23 4940642834 ps
T832 /workspace/coverage/default/2.adc_ctrl_lowpower_counter.1814412534 Dec 31 12:32:13 PM PST 23 Dec 31 12:32:36 PM PST 23 40811142196 ps
T833 /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.403448294 Dec 31 12:32:55 PM PST 23 Dec 31 12:34:42 PM PST 23 168993669381 ps
T834 /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.3018547958 Dec 31 12:32:35 PM PST 23 Dec 31 12:34:14 PM PST 23 164959049269 ps
T330 /workspace/coverage/default/23.adc_ctrl_stress_all.3866097077 Dec 31 12:32:39 PM PST 23 Dec 31 12:43:50 PM PST 23 322100220782 ps
T275 /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.2305193234 Dec 31 12:32:41 PM PST 23 Dec 31 12:39:25 PM PST 23 332173757241 ps
T835 /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.2041547102 Dec 31 12:32:38 PM PST 23 Dec 31 12:34:21 PM PST 23 33196008857 ps
T836 /workspace/coverage/default/16.adc_ctrl_poweron_counter.2566840009 Dec 31 12:32:14 PM PST 23 Dec 31 12:32:19 PM PST 23 5013049339 ps
T837 /workspace/coverage/default/42.adc_ctrl_lowpower_counter.567701121 Dec 31 12:33:19 PM PST 23 Dec 31 12:35:12 PM PST 23 46573270047 ps
T838 /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.1308326124 Dec 31 12:32:57 PM PST 23 Dec 31 12:36:27 PM PST 23 227330338333 ps
T839 /workspace/coverage/default/31.adc_ctrl_lowpower_counter.1104304505 Dec 31 12:32:58 PM PST 23 Dec 31 12:33:44 PM PST 23 36551140760 ps
T840 /workspace/coverage/default/26.adc_ctrl_smoke.1371124897 Dec 31 12:32:50 PM PST 23 Dec 31 12:32:54 PM PST 23 6117422300 ps
T200 /workspace/coverage/default/2.adc_ctrl_filters_polled.2309114427 Dec 31 12:33:25 PM PST 23 Dec 31 12:51:27 PM PST 23 490718361624 ps
T841 /workspace/coverage/default/4.adc_ctrl_filters_both.1619404041 Dec 31 12:32:05 PM PST 23 Dec 31 12:37:55 PM PST 23 160921188845 ps
T842 /workspace/coverage/default/22.adc_ctrl_fsm_reset.3851210586 Dec 31 12:32:36 PM PST 23 Dec 31 12:36:46 PM PST 23 63783236540 ps
T843 /workspace/coverage/default/20.adc_ctrl_filters_wakeup.3488189692 Dec 31 12:32:49 PM PST 23 Dec 31 12:35:47 PM PST 23 174102972438 ps
T844 /workspace/coverage/default/9.adc_ctrl_lowpower_counter.3305909710 Dec 31 12:32:13 PM PST 23 Dec 31 12:33:48 PM PST 23 39594194771 ps
T845 /workspace/coverage/default/13.adc_ctrl_fsm_reset.2111033991 Dec 31 12:32:11 PM PST 23 Dec 31 12:42:54 PM PST 23 115086260128 ps
T846 /workspace/coverage/default/44.adc_ctrl_fsm_reset.52224560 Dec 31 12:33:23 PM PST 23 Dec 31 12:39:36 PM PST 23 98540478766 ps
T847 /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.1553274311 Dec 31 12:33:11 PM PST 23 Dec 31 12:34:06 PM PST 23 100599392761 ps
T349 /workspace/coverage/default/10.adc_ctrl_fsm_reset.661727723 Dec 31 12:32:13 PM PST 23 Dec 31 12:43:52 PM PST 23 134113245241 ps
T848 /workspace/coverage/default/30.adc_ctrl_filters_polled.2742797473 Dec 31 12:33:00 PM PST 23 Dec 31 12:35:01 PM PST 23 159897763710 ps
T849 /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.2985462922 Dec 31 12:32:59 PM PST 23 Dec 31 12:45:10 PM PST 23 327011315346 ps
T850 /workspace/coverage/default/33.adc_ctrl_lowpower_counter.3952876318 Dec 31 12:33:21 PM PST 23 Dec 31 12:33:51 PM PST 23 47116844803 ps
T851 /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.3909960561 Dec 31 12:33:06 PM PST 23 Dec 31 12:35:56 PM PST 23 166872837044 ps
T852 /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.3448764334 Dec 31 12:32:16 PM PST 23 Dec 31 12:33:51 PM PST 23 157674116845 ps
T853 /workspace/coverage/default/13.adc_ctrl_filters_wakeup.498223516 Dec 31 12:32:49 PM PST 23 Dec 31 12:37:30 PM PST 23 506737491758 ps
T854 /workspace/coverage/default/37.adc_ctrl_clock_gating.1583667613 Dec 31 12:33:02 PM PST 23 Dec 31 12:40:59 PM PST 23 489645881194 ps
T855 /workspace/coverage/default/46.adc_ctrl_filters_polled.3641221554 Dec 31 12:33:36 PM PST 23 Dec 31 12:35:22 PM PST 23 160013712620 ps
T856 /workspace/coverage/default/0.adc_ctrl_poweron_counter.2465927970 Dec 31 12:32:13 PM PST 23 Dec 31 12:32:27 PM PST 23 5227380854 ps
T857 /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.1320735552 Dec 31 12:33:00 PM PST 23 Dec 31 12:36:03 PM PST 23 328968629157 ps
T858 /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.1600243115 Dec 31 12:33:47 PM PST 23 Dec 31 12:37:52 PM PST 23 494639207417 ps
T859 /workspace/coverage/default/28.adc_ctrl_filters_wakeup.2061296989 Dec 31 12:32:59 PM PST 23 Dec 31 12:34:44 PM PST 23 187674497268 ps
T860 /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.1944211098 Dec 31 12:32:28 PM PST 23 Dec 31 12:39:01 PM PST 23 163061223989 ps
T861 /workspace/coverage/default/47.adc_ctrl_poweron_counter.210543178 Dec 31 12:33:53 PM PST 23 Dec 31 12:34:07 PM PST 23 5286993774 ps
T862 /workspace/coverage/default/37.adc_ctrl_smoke.2525935029 Dec 31 12:33:00 PM PST 23 Dec 31 12:33:17 PM PST 23 6117719051 ps
T863 /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.3444048772 Dec 31 12:33:05 PM PST 23 Dec 31 12:35:08 PM PST 23 329638476906 ps
T864 /workspace/coverage/default/14.adc_ctrl_fsm_reset.3772934856 Dec 31 12:32:28 PM PST 23 Dec 31 12:44:22 PM PST 23 125027738932 ps
T865 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.4099113701 Dec 31 12:43:42 PM PST 23 Dec 31 12:43:44 PM PST 23 390289879 ps
T866 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2064094941 Dec 31 12:43:30 PM PST 23 Dec 31 12:43:32 PM PST 23 487411210 ps
T867 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1258560399 Dec 31 12:43:30 PM PST 23 Dec 31 12:43:32 PM PST 23 389459341 ps
T868 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.4101822938 Dec 31 12:43:18 PM PST 23 Dec 31 12:43:20 PM PST 23 2637311436 ps
T869 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3621678844 Dec 31 12:43:13 PM PST 23 Dec 31 12:43:15 PM PST 23 486478300 ps
T74 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.762073363 Dec 31 12:43:16 PM PST 23 Dec 31 12:43:18 PM PST 23 540955222 ps
T870 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.4180642740 Dec 31 12:43:55 PM PST 23 Dec 31 12:44:10 PM PST 23 543018058 ps
T871 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2902659518 Dec 31 12:43:23 PM PST 23 Dec 31 12:43:26 PM PST 23 1289048364 ps
T872 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.2386545462 Dec 31 12:43:14 PM PST 23 Dec 31 12:43:16 PM PST 23 493336485 ps
T873 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2404681603 Dec 31 12:43:24 PM PST 23 Dec 31 12:43:26 PM PST 23 446995432 ps
T874 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.1081720068 Dec 31 12:43:56 PM PST 23 Dec 31 12:44:10 PM PST 23 486638154 ps
T875 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3895800413 Dec 31 12:43:16 PM PST 23 Dec 31 12:43:18 PM PST 23 451044182 ps
T876 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.182995514 Dec 31 12:42:48 PM PST 23 Dec 31 12:43:00 PM PST 23 8445454827 ps
T76 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1153644826 Dec 31 12:42:42 PM PST 23 Dec 31 12:42:46 PM PST 23 1239112824 ps
T877 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.287095356 Dec 31 12:43:30 PM PST 23 Dec 31 12:43:33 PM PST 23 533027476 ps
T878 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1075612243 Dec 31 12:43:16 PM PST 23 Dec 31 12:43:18 PM PST 23 470503455 ps
T879 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1564609998 Dec 31 12:43:51 PM PST 23 Dec 31 12:43:58 PM PST 23 623012065 ps
T880 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1556120888 Dec 31 12:43:12 PM PST 23 Dec 31 12:43:13 PM PST 23 538695083 ps
T881 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.314346948 Dec 31 12:43:14 PM PST 23 Dec 31 12:43:16 PM PST 23 566994079 ps
T882 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2959374148 Dec 31 12:43:14 PM PST 23 Dec 31 12:43:18 PM PST 23 437652973 ps
T883 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3974186406 Dec 31 12:43:12 PM PST 23 Dec 31 12:43:14 PM PST 23 441558528 ps
T884 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.2200793532 Dec 31 12:43:24 PM PST 23 Dec 31 12:43:26 PM PST 23 378784866 ps
T885 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3626602818 Dec 31 12:43:47 PM PST 23 Dec 31 12:43:49 PM PST 23 393289784 ps
T886 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.2874846788 Dec 31 12:43:49 PM PST 23 Dec 31 12:43:56 PM PST 23 554905468 ps
T887 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1392399860 Dec 31 12:43:54 PM PST 23 Dec 31 12:44:06 PM PST 23 465800121 ps
T888 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.271587607 Dec 31 12:43:12 PM PST 23 Dec 31 12:43:13 PM PST 23 424343100 ps
T889 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1468453262 Dec 31 12:43:38 PM PST 23 Dec 31 12:43:43 PM PST 23 451117529 ps
T890 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1842938818 Dec 31 12:43:40 PM PST 23 Dec 31 12:43:43 PM PST 23 586950893 ps
T891 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.4266550914 Dec 31 12:43:11 PM PST 23 Dec 31 12:43:14 PM PST 23 556208341 ps
T892 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.21325844 Dec 31 12:43:13 PM PST 23 Dec 31 12:43:17 PM PST 23 4163377038 ps
T893 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1436223429 Dec 31 12:43:34 PM PST 23 Dec 31 12:43:39 PM PST 23 4899050431 ps
T894 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2198574269 Dec 31 12:43:43 PM PST 23 Dec 31 12:43:45 PM PST 23 505312019 ps
T895 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3239662538 Dec 31 12:43:18 PM PST 23 Dec 31 12:43:20 PM PST 23 374006280 ps
T896 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3976753284 Dec 31 12:43:13 PM PST 23 Dec 31 12:43:25 PM PST 23 4521750408 ps
T897 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1551095604 Dec 31 12:42:45 PM PST 23 Dec 31 12:42:47 PM PST 23 563724449 ps
T898 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1815246255 Dec 31 12:43:46 PM PST 23 Dec 31 12:43:58 PM PST 23 4522651475 ps
T899 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1070262281 Dec 31 12:42:43 PM PST 23 Dec 31 12:42:46 PM PST 23 904762235 ps
T900 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2640839979 Dec 31 12:42:41 PM PST 23 Dec 31 12:42:44 PM PST 23 1623503918 ps
T901 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2458999902 Dec 31 12:43:22 PM PST 23 Dec 31 12:43:24 PM PST 23 409623844 ps
T902 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3128514620 Dec 31 12:43:16 PM PST 23 Dec 31 12:43:18 PM PST 23 455713653 ps
T903 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1533602913 Dec 31 12:43:19 PM PST 23 Dec 31 12:43:20 PM PST 23 681284580 ps
T344 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.417203863 Dec 31 12:43:28 PM PST 23 Dec 31 12:43:41 PM PST 23 8309328340 ps
T904 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.4234530832 Dec 31 12:43:24 PM PST 23 Dec 31 12:43:27 PM PST 23 1897457613 ps
T905 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.717789400 Dec 31 12:43:15 PM PST 23 Dec 31 12:43:17 PM PST 23 518986826 ps
T906 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3264152646 Dec 31 12:43:24 PM PST 23 Dec 31 12:43:36 PM PST 23 5109025947 ps
T907 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2929051262 Dec 31 12:43:30 PM PST 23 Dec 31 12:43:33 PM PST 23 2317820731 ps
T908 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.65429368 Dec 31 12:43:32 PM PST 23 Dec 31 12:43:34 PM PST 23 535815154 ps
T909 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1891560526 Dec 31 12:43:33 PM PST 23 Dec 31 12:43:37 PM PST 23 279073684 ps
T910 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1128782266 Dec 31 12:43:28 PM PST 23 Dec 31 12:43:48 PM PST 23 5081650414 ps
T911 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.436730432 Dec 31 12:43:22 PM PST 23 Dec 31 12:43:26 PM PST 23 478170496 ps
T912 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.2412871947 Dec 31 12:42:46 PM PST 23 Dec 31 12:42:47 PM PST 23 402686065 ps
T913 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1826772650 Dec 31 12:43:19 PM PST 23 Dec 31 12:43:22 PM PST 23 519876262 ps

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1665381530
Short name T1
Test name
Test status
Simulation time 4468649043 ps
CPU time 4.4 seconds
Started Dec 31 12:43:46 PM PST 23
Finished Dec 31 12:43:51 PM PST 23
Peak memory 200796 kb
Host smart-0572c0a5-d1c7-46d7-9964-b86ab3a83468
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665381530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.1665381530
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.3732633488
Short name T14
Test name
Test status
Simulation time 123694906485 ps
CPU time 57.17 seconds
Started Dec 31 12:32:44 PM PST 23
Finished Dec 31 12:33:43 PM PST 23
Peak memory 209060 kb
Host smart-6121e288-5c5e-4517-a40a-f1385c2d99c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732633488 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.3732633488
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.729185507
Short name T39
Test name
Test status
Simulation time 105197112741 ps
CPU time 214.51 seconds
Started Dec 31 12:32:17 PM PST 23
Finished Dec 31 12:35:54 PM PST 23
Peak memory 211748 kb
Host smart-fa37e072-b8ba-42f9-a488-e67163065cd8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729185507 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.729185507
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.1927536236
Short name T6
Test name
Test status
Simulation time 370261228 ps
CPU time 1.01 seconds
Started Dec 31 12:43:46 PM PST 23
Finished Dec 31 12:43:48 PM PST 23
Peak memory 200532 kb
Host smart-0a17f4e5-ecdf-4adc-8ade-5ab0b2aaf759
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927536236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.1927536236
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.4075379460
Short name T87
Test name
Test status
Simulation time 486658810149 ps
CPU time 203.22 seconds
Started Dec 31 12:32:32 PM PST 23
Finished Dec 31 12:35:57 PM PST 23
Peak memory 200780 kb
Host smart-238f4ea5-4ea1-4432-a3ca-989a89b429af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075379460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.4075379460
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.2929227668
Short name T47
Test name
Test status
Simulation time 536435232 ps
CPU time 0.99 seconds
Started Dec 31 12:43:33 PM PST 23
Finished Dec 31 12:43:37 PM PST 23
Peak memory 200424 kb
Host smart-a9ed7f4d-b263-4a14-a07f-77a0115e76bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929227668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.2929227668
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.3884558811
Short name T94
Test name
Test status
Simulation time 490503109528 ps
CPU time 292.52 seconds
Started Dec 31 12:32:33 PM PST 23
Finished Dec 31 12:37:27 PM PST 23
Peak memory 200676 kb
Host smart-de26f732-dd6c-4952-9513-b2d76d48e25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884558811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.3884558811
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.643316248
Short name T22
Test name
Test status
Simulation time 338179086663 ps
CPU time 70.53 seconds
Started Dec 31 12:33:41 PM PST 23
Finished Dec 31 12:34:53 PM PST 23
Peak memory 200860 kb
Host smart-5366ecd9-64e9-469e-b59a-720234492fb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643316248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all.
643316248
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.13911173
Short name T82
Test name
Test status
Simulation time 483302437472 ps
CPU time 92.86 seconds
Started Dec 31 12:33:41 PM PST 23
Finished Dec 31 12:35:15 PM PST 23
Peak memory 200768 kb
Host smart-be999a14-e981-40ac-8f9b-0285adc99b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13911173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.13911173
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.1802916900
Short name T102
Test name
Test status
Simulation time 493120533951 ps
CPU time 1001.91 seconds
Started Dec 31 12:32:11 PM PST 23
Finished Dec 31 12:48:54 PM PST 23
Peak memory 200736 kb
Host smart-72a0018c-72d2-4036-baf8-581794783a5e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802916900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.1802916900
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.440109255
Short name T123
Test name
Test status
Simulation time 500970400624 ps
CPU time 120.87 seconds
Started Dec 31 12:32:59 PM PST 23
Finished Dec 31 12:35:01 PM PST 23
Peak memory 200760 kb
Host smart-20a3c8a9-43c5-489b-9828-91a3a68d437c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440109255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gati
ng.440109255
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.73742521
Short name T84
Test name
Test status
Simulation time 422389078975 ps
CPU time 518.72 seconds
Started Dec 31 12:33:27 PM PST 23
Finished Dec 31 12:42:12 PM PST 23
Peak memory 201172 kb
Host smart-d289d372-f8dd-49f8-ad87-aa905280e880
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73742521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all.73742521
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.298957268
Short name T116
Test name
Test status
Simulation time 505335671935 ps
CPU time 873.69 seconds
Started Dec 31 12:32:15 PM PST 23
Finished Dec 31 12:46:51 PM PST 23
Peak memory 200788 kb
Host smart-742591c0-1e62-4b5d-98da-9fd326678791
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298957268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gati
ng.298957268
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.487018280
Short name T130
Test name
Test status
Simulation time 492320363304 ps
CPU time 115.06 seconds
Started Dec 31 12:33:18 PM PST 23
Finished Dec 31 12:35:16 PM PST 23
Peak memory 200796 kb
Host smart-fab67600-5d4e-4867-b45d-1f9bf2c6c598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487018280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.487018280
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1313119336
Short name T29
Test name
Test status
Simulation time 557539655 ps
CPU time 3.57 seconds
Started Dec 31 12:43:27 PM PST 23
Finished Dec 31 12:43:37 PM PST 23
Peak memory 200804 kb
Host smart-bae8c26e-5c57-4e43-b8d6-fedfc2072c9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313119336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.1313119336
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.1816924978
Short name T103
Test name
Test status
Simulation time 492450543031 ps
CPU time 670.88 seconds
Started Dec 31 12:33:18 PM PST 23
Finished Dec 31 12:44:32 PM PST 23
Peak memory 200780 kb
Host smart-1614132e-c5d8-43bc-babf-98b975b83974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816924978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.1816924978
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.694999379
Short name T81
Test name
Test status
Simulation time 490368647740 ps
CPU time 540.07 seconds
Started Dec 31 12:33:36 PM PST 23
Finished Dec 31 12:42:39 PM PST 23
Peak memory 200756 kb
Host smart-a611644d-6324-48a7-b958-83623deb36fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694999379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.694999379
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.1308818555
Short name T12
Test name
Test status
Simulation time 487572238335 ps
CPU time 1120.2 seconds
Started Dec 31 12:32:46 PM PST 23
Finished Dec 31 12:51:28 PM PST 23
Peak memory 200828 kb
Host smart-57ad0bbf-de02-4305-906f-6509364202f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308818555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.1308818555
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.661814385
Short name T101
Test name
Test status
Simulation time 487120268723 ps
CPU time 186.74 seconds
Started Dec 31 12:32:59 PM PST 23
Finished Dec 31 12:36:07 PM PST 23
Peak memory 200724 kb
Host smart-598562a8-e868-4196-bbc0-b46b588005f1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661814385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gati
ng.661814385
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.557933470
Short name T2
Test name
Test status
Simulation time 27276759360 ps
CPU time 56.69 seconds
Started Dec 31 12:42:47 PM PST 23
Finished Dec 31 12:43:49 PM PST 23
Peak memory 200780 kb
Host smart-68a090ff-7ae8-4d8e-b1f4-a3a1de824612
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557933470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_b
ash.557933470
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.3930652236
Short name T258
Test name
Test status
Simulation time 328145572372 ps
CPU time 97.77 seconds
Started Dec 31 12:32:00 PM PST 23
Finished Dec 31 12:33:39 PM PST 23
Peak memory 200780 kb
Host smart-93a5b664-6631-49d6-b7c1-cd43ba219f01
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930652236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.3930652236
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.3334681523
Short name T244
Test name
Test status
Simulation time 521796862989 ps
CPU time 283.64 seconds
Started Dec 31 12:32:38 PM PST 23
Finished Dec 31 12:37:22 PM PST 23
Peak memory 200796 kb
Host smart-0349c96c-26b3-4ea6-b147-f74f54ed91da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334681523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.3334681523
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.1991476119
Short name T236
Test name
Test status
Simulation time 509114728458 ps
CPU time 1123.2 seconds
Started Dec 31 12:33:14 PM PST 23
Finished Dec 31 12:52:01 PM PST 23
Peak memory 200708 kb
Host smart-d3913ff4-0d09-44d1-b9c8-f8878a6bd675
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991476119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.1991476119
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.87874048
Short name T38
Test name
Test status
Simulation time 4231419797 ps
CPU time 5.35 seconds
Started Dec 31 12:33:09 PM PST 23
Finished Dec 31 12:33:21 PM PST 23
Peak memory 215848 kb
Host smart-0ca4f628-4166-497d-bbfe-9a632333d8c9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87874048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.87874048
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.458012665
Short name T238
Test name
Test status
Simulation time 181730238881 ps
CPU time 383.47 seconds
Started Dec 31 12:33:21 PM PST 23
Finished Dec 31 12:39:46 PM PST 23
Peak memory 217712 kb
Host smart-660f1c5c-eee5-4a2a-a3ff-823d1ef88d8a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458012665 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.458012665
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.3359239649
Short name T107
Test name
Test status
Simulation time 326637820453 ps
CPU time 768.96 seconds
Started Dec 31 12:32:32 PM PST 23
Finished Dec 31 12:45:23 PM PST 23
Peak memory 200796 kb
Host smart-eed1692f-1ecc-4787-95c4-caec3bed7742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359239649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.3359239649
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.1133058997
Short name T321
Test name
Test status
Simulation time 345396513438 ps
CPU time 163 seconds
Started Dec 31 12:32:52 PM PST 23
Finished Dec 31 12:35:36 PM PST 23
Peak memory 200820 kb
Host smart-e4c14f2d-0aa8-44b9-9dd4-9cbe5b6ca738
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133058997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.1133058997
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.2781059812
Short name T120
Test name
Test status
Simulation time 492020151970 ps
CPU time 118.03 seconds
Started Dec 31 12:32:42 PM PST 23
Finished Dec 31 12:34:41 PM PST 23
Peak memory 200704 kb
Host smart-fffddeba-c8b6-43a7-b1cc-f279e228a29e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781059812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.2781059812
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.1416061943
Short name T166
Test name
Test status
Simulation time 283746343212 ps
CPU time 547.38 seconds
Started Dec 31 12:32:46 PM PST 23
Finished Dec 31 12:41:56 PM PST 23
Peak memory 217540 kb
Host smart-5c047b23-8ab0-482f-9fcb-7950f6fe0847
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416061943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.1416061943
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.110520085
Short name T27
Test name
Test status
Simulation time 591577463 ps
CPU time 2.82 seconds
Started Dec 31 12:42:53 PM PST 23
Finished Dec 31 12:42:57 PM PST 23
Peak memory 200788 kb
Host smart-a6141316-07de-45ec-95ca-02afc03eb97f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110520085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.110520085
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.708395953
Short name T96
Test name
Test status
Simulation time 500959180434 ps
CPU time 333.66 seconds
Started Dec 31 12:32:12 PM PST 23
Finished Dec 31 12:37:48 PM PST 23
Peak memory 200832 kb
Host smart-2dc05372-529a-4b1d-a57d-de6513dfe505
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708395953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_w
akeup.708395953
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.518954134
Short name T248
Test name
Test status
Simulation time 333148989809 ps
CPU time 196.8 seconds
Started Dec 31 12:33:02 PM PST 23
Finished Dec 31 12:36:20 PM PST 23
Peak memory 200160 kb
Host smart-7a31e8d6-da0a-4e15-bdff-7e72656a3196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518954134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.518954134
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.1235314684
Short name T266
Test name
Test status
Simulation time 673212516324 ps
CPU time 591.02 seconds
Started Dec 31 12:32:32 PM PST 23
Finished Dec 31 12:42:25 PM PST 23
Peak memory 209368 kb
Host smart-078e3970-a0ec-469b-9d61-355386aaf693
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235314684 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.1235314684
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.3002418419
Short name T325
Test name
Test status
Simulation time 494889633458 ps
CPU time 75.43 seconds
Started Dec 31 12:33:09 PM PST 23
Finished Dec 31 12:34:31 PM PST 23
Peak memory 200696 kb
Host smart-d4d7f866-f265-4002-b421-612e6ab21c62
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002418419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.3002418419
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.1229337039
Short name T311
Test name
Test status
Simulation time 489219991531 ps
CPU time 176.18 seconds
Started Dec 31 12:33:42 PM PST 23
Finished Dec 31 12:36:39 PM PST 23
Peak memory 200720 kb
Host smart-1050293d-709c-4253-bf1c-7a5b269d8d77
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229337039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.1229337039
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.2867342258
Short name T125
Test name
Test status
Simulation time 492403871012 ps
CPU time 1172.19 seconds
Started Dec 31 12:33:14 PM PST 23
Finished Dec 31 12:52:50 PM PST 23
Peak memory 200732 kb
Host smart-52914588-2272-43e5-a527-14bda8c5a7f1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867342258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.2867342258
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.1188002597
Short name T99
Test name
Test status
Simulation time 502966818913 ps
CPU time 1133.44 seconds
Started Dec 31 12:32:52 PM PST 23
Finished Dec 31 12:51:46 PM PST 23
Peak memory 200784 kb
Host smart-6cf6bacb-a9f3-408a-a156-3d83c29a9950
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188002597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.1188002597
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.122967478
Short name T148
Test name
Test status
Simulation time 167443998305 ps
CPU time 393.14 seconds
Started Dec 31 12:32:47 PM PST 23
Finished Dec 31 12:39:22 PM PST 23
Peak memory 199192 kb
Host smart-dd473bcf-beb7-42dc-9b13-6d629938c1af
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122967478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.a
dc_ctrl_filters_wakeup_fixed.122967478
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.1902251220
Short name T198
Test name
Test status
Simulation time 489137693464 ps
CPU time 603.17 seconds
Started Dec 31 12:32:06 PM PST 23
Finished Dec 31 12:42:10 PM PST 23
Peak memory 200716 kb
Host smart-52c8ed0c-0156-4a97-aaaf-c97d93817aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902251220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.1902251220
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.591448614
Short name T141
Test name
Test status
Simulation time 288102429444 ps
CPU time 566.52 seconds
Started Dec 31 12:32:30 PM PST 23
Finished Dec 31 12:41:59 PM PST 23
Peak memory 201224 kb
Host smart-b7c2f692-ff1b-422f-8a5b-fe773278a2ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591448614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all.
591448614
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.3432783953
Short name T127
Test name
Test status
Simulation time 487029762745 ps
CPU time 291.33 seconds
Started Dec 31 12:32:26 PM PST 23
Finished Dec 31 12:37:19 PM PST 23
Peak memory 200896 kb
Host smart-f83942e6-06cd-4c92-b880-3ee35e698c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432783953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.3432783953
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.540707833
Short name T85
Test name
Test status
Simulation time 328691720896 ps
CPU time 196.77 seconds
Started Dec 31 12:32:49 PM PST 23
Finished Dec 31 12:36:08 PM PST 23
Peak memory 200716 kb
Host smart-e4304a84-908a-4469-b405-4b3a4dfa23c0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540707833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gati
ng.540707833
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.649766489
Short name T263
Test name
Test status
Simulation time 512243825762 ps
CPU time 297.5 seconds
Started Dec 31 12:33:19 PM PST 23
Finished Dec 31 12:38:19 PM PST 23
Peak memory 200848 kb
Host smart-730890b4-8477-4917-ac3e-3a091f82c590
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649766489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_
wakeup.649766489
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.2166647606
Short name T229
Test name
Test status
Simulation time 505489063218 ps
CPU time 740.91 seconds
Started Dec 31 12:32:00 PM PST 23
Finished Dec 31 12:44:22 PM PST 23
Peak memory 200792 kb
Host smart-04c0c022-e6c2-43ea-a0c6-5947b621ab6e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166647606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.2166647606
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.2989816240
Short name T273
Test name
Test status
Simulation time 499476354785 ps
CPU time 1152.3 seconds
Started Dec 31 12:32:31 PM PST 23
Finished Dec 31 12:51:45 PM PST 23
Peak memory 200900 kb
Host smart-1cd92feb-57ac-43d4-bb60-983d0773bbc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989816240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.2989816240
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.2917006320
Short name T279
Test name
Test status
Simulation time 531014533457 ps
CPU time 260.42 seconds
Started Dec 31 12:33:33 PM PST 23
Finished Dec 31 12:37:58 PM PST 23
Peak memory 200732 kb
Host smart-3e415232-e725-46db-8971-1c4bd289e6e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917006320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.2917006320
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.2103757742
Short name T303
Test name
Test status
Simulation time 94158270353 ps
CPU time 81.69 seconds
Started Dec 31 12:33:38 PM PST 23
Finished Dec 31 12:35:02 PM PST 23
Peak memory 209444 kb
Host smart-ca6f182e-221a-414c-bcc1-f5aac73f64b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103757742 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.2103757742
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.134448760
Short name T115
Test name
Test status
Simulation time 494864308774 ps
CPU time 762.38 seconds
Started Dec 31 12:31:47 PM PST 23
Finished Dec 31 12:44:35 PM PST 23
Peak memory 200752 kb
Host smart-e51b8edf-9f23-4f28-88c6-ef91d05e2026
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134448760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gatin
g.134448760
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.2305193234
Short name T275
Test name
Test status
Simulation time 332173757241 ps
CPU time 403.43 seconds
Started Dec 31 12:32:41 PM PST 23
Finished Dec 31 12:39:25 PM PST 23
Peak memory 209384 kb
Host smart-f3c55533-f9e3-4656-b9d3-85162ab3a65c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305193234 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.2305193234
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.3978586978
Short name T203
Test name
Test status
Simulation time 360950353343 ps
CPU time 820.4 seconds
Started Dec 31 12:32:12 PM PST 23
Finished Dec 31 12:45:53 PM PST 23
Peak memory 200716 kb
Host smart-fa6c0be6-ad46-43a7-866e-ef9028c21d1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978586978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.3978586978
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.1623454297
Short name T220
Test name
Test status
Simulation time 490373179348 ps
CPU time 1109.07 seconds
Started Dec 31 12:32:33 PM PST 23
Finished Dec 31 12:51:05 PM PST 23
Peak memory 200788 kb
Host smart-8aed0ede-d277-4d0f-a9ef-ee012f0d58a9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623454297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.1623454297
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.3706324874
Short name T246
Test name
Test status
Simulation time 164205567005 ps
CPU time 101.95 seconds
Started Dec 31 12:33:06 PM PST 23
Finished Dec 31 12:34:51 PM PST 23
Peak memory 200788 kb
Host smart-93796354-3347-42d8-8389-3cef975480fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706324874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.3706324874
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.2185356127
Short name T185
Test name
Test status
Simulation time 128531011282 ps
CPU time 490.16 seconds
Started Dec 31 12:32:45 PM PST 23
Finished Dec 31 12:40:58 PM PST 23
Peak memory 201200 kb
Host smart-dc80f201-d97c-4d01-a71f-7394f9c77845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185356127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.2185356127
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.3362688607
Short name T247
Test name
Test status
Simulation time 491163471734 ps
CPU time 282.1 seconds
Started Dec 31 12:33:06 PM PST 23
Finished Dec 31 12:37:49 PM PST 23
Peak memory 200716 kb
Host smart-fb1c0747-f907-4cec-95e4-757dc54e2689
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362688607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.3362688607
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.1791334379
Short name T299
Test name
Test status
Simulation time 332047745176 ps
CPU time 86.34 seconds
Started Dec 31 12:32:33 PM PST 23
Finished Dec 31 12:34:00 PM PST 23
Peak memory 200736 kb
Host smart-916cf0f8-f5c7-4f8f-8df4-f85ef91f47d5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791334379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.1791334379
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.2453557511
Short name T251
Test name
Test status
Simulation time 497436961458 ps
CPU time 1175.42 seconds
Started Dec 31 12:32:18 PM PST 23
Finished Dec 31 12:51:56 PM PST 23
Peak memory 200712 kb
Host smart-05bb3581-d9b7-4e76-ac56-8503baf5265b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453557511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.2453557511
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.2309114427
Short name T200
Test name
Test status
Simulation time 490718361624 ps
CPU time 1075.09 seconds
Started Dec 31 12:33:25 PM PST 23
Finished Dec 31 12:51:27 PM PST 23
Peak memory 200436 kb
Host smart-79752172-8c14-430d-94a5-6e9b93af752d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309114427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.2309114427
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.795937279
Short name T233
Test name
Test status
Simulation time 486272350213 ps
CPU time 1047.68 seconds
Started Dec 31 12:32:43 PM PST 23
Finished Dec 31 12:50:13 PM PST 23
Peak memory 200680 kb
Host smart-556b3c02-acb5-47ea-ad7b-65b3325d796e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795937279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gati
ng.795937279
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.25184237
Short name T231
Test name
Test status
Simulation time 498112529122 ps
CPU time 398.36 seconds
Started Dec 31 12:33:03 PM PST 23
Finished Dec 31 12:39:42 PM PST 23
Peak memory 200704 kb
Host smart-b0683f15-9e33-4fc1-a1f9-725046d74e53
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25184237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gatin
g.25184237
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.3905508463
Short name T270
Test name
Test status
Simulation time 325548250932 ps
CPU time 174.26 seconds
Started Dec 31 12:32:59 PM PST 23
Finished Dec 31 12:35:55 PM PST 23
Peak memory 200736 kb
Host smart-5f785345-4940-4477-890c-9f4c1802e658
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905508463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.3905508463
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.545473117
Short name T338
Test name
Test status
Simulation time 155388161664 ps
CPU time 138.34 seconds
Started Dec 31 12:32:11 PM PST 23
Finished Dec 31 12:34:30 PM PST 23
Peak memory 209376 kb
Host smart-bb10b341-d13b-445c-af0f-b95f4b2a5976
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545473117 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.545473117
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.2832064936
Short name T304
Test name
Test status
Simulation time 487316069169 ps
CPU time 97.95 seconds
Started Dec 31 12:33:00 PM PST 23
Finished Dec 31 12:34:40 PM PST 23
Peak memory 200796 kb
Host smart-0bea8af8-7fba-449d-a190-4596afc578a9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832064936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.2832064936
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.854873089
Short name T177
Test name
Test status
Simulation time 344477416687 ps
CPU time 219.99 seconds
Started Dec 31 12:32:29 PM PST 23
Finished Dec 31 12:36:12 PM PST 23
Peak memory 200688 kb
Host smart-e3d947bb-e3b5-4d22-b4ec-f5177fb00986
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854873089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_w
akeup.854873089
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.1069747347
Short name T48
Test name
Test status
Simulation time 493351570 ps
CPU time 1.76 seconds
Started Dec 31 12:32:34 PM PST 23
Finished Dec 31 12:32:37 PM PST 23
Peak memory 200524 kb
Host smart-159f7929-88bf-4a0f-be55-7cb444be4166
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069747347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.1069747347
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.414445905
Short name T302
Test name
Test status
Simulation time 166417970101 ps
CPU time 101.66 seconds
Started Dec 31 12:32:19 PM PST 23
Finished Dec 31 12:34:07 PM PST 23
Peak memory 200760 kb
Host smart-ae5172ed-7fc5-4698-963a-b7d36d883b44
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414445905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_
wakeup.414445905
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.2300093818
Short name T255
Test name
Test status
Simulation time 329003681272 ps
CPU time 216.32 seconds
Started Dec 31 12:32:34 PM PST 23
Finished Dec 31 12:36:12 PM PST 23
Peak memory 200716 kb
Host smart-e50365e1-2e2b-469b-84e4-c8db38852d12
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300093818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.2300093818
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.272922729
Short name T191
Test name
Test status
Simulation time 169267333326 ps
CPU time 210.14 seconds
Started Dec 31 12:33:05 PM PST 23
Finished Dec 31 12:36:37 PM PST 23
Peak memory 200672 kb
Host smart-99e16232-d741-4f79-8f7c-4b6d9419526e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272922729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_
wakeup.272922729
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.3985049600
Short name T114
Test name
Test status
Simulation time 106779922323 ps
CPU time 410.9 seconds
Started Dec 31 12:33:17 PM PST 23
Finished Dec 31 12:40:12 PM PST 23
Peak memory 201136 kb
Host smart-374ec21c-393e-4b4d-b618-7ae6eb5ece9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985049600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.3985049600
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.926526745
Short name T315
Test name
Test status
Simulation time 494005070223 ps
CPU time 300.45 seconds
Started Dec 31 12:33:51 PM PST 23
Finished Dec 31 12:38:53 PM PST 23
Peak memory 200792 kb
Host smart-8b07d9a2-e795-4ef4-9b7e-e45d880aac86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926526745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.926526745
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3636964544
Short name T26
Test name
Test status
Simulation time 574368624 ps
CPU time 2.48 seconds
Started Dec 31 12:43:12 PM PST 23
Finished Dec 31 12:43:16 PM PST 23
Peak memory 217092 kb
Host smart-35bbeafe-e328-4a76-a39d-79e492e50dfb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636964544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.3636964544
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3495450690
Short name T372
Test name
Test status
Simulation time 431727985 ps
CPU time 1.62 seconds
Started Dec 31 12:43:32 PM PST 23
Finished Dec 31 12:43:34 PM PST 23
Peak memory 200380 kb
Host smart-9f47b34a-732e-4143-a027-d0f3f2e03974
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495450690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.3495450690
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.1623829787
Short name T446
Test name
Test status
Simulation time 337625789634 ps
CPU time 414.21 seconds
Started Dec 31 12:32:11 PM PST 23
Finished Dec 31 12:39:06 PM PST 23
Peak memory 200748 kb
Host smart-71e0c97b-f270-4d56-bebe-53dffc251cb2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623829787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.1623829787
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.4050043715
Short name T181
Test name
Test status
Simulation time 74707787068 ps
CPU time 230.82 seconds
Started Dec 31 12:32:49 PM PST 23
Finished Dec 31 12:36:41 PM PST 23
Peak memory 201224 kb
Host smart-33b51235-7571-4338-babb-69e1ca9352ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050043715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.4050043715
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.1097652830
Short name T98
Test name
Test status
Simulation time 489790014931 ps
CPU time 608.29 seconds
Started Dec 31 12:32:48 PM PST 23
Finished Dec 31 12:42:58 PM PST 23
Peak memory 200800 kb
Host smart-ac2a22e8-5bcf-4db4-b4fa-232892d42354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097652830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.1097652830
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.2519660316
Short name T189
Test name
Test status
Simulation time 97567219314 ps
CPU time 417.85 seconds
Started Dec 31 12:32:41 PM PST 23
Finished Dec 31 12:39:40 PM PST 23
Peak memory 201240 kb
Host smart-3b6a5725-444b-4dde-859f-5e00e4a7cdb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519660316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.2519660316
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.1744646242
Short name T314
Test name
Test status
Simulation time 379443265719 ps
CPU time 422.77 seconds
Started Dec 31 12:32:52 PM PST 23
Finished Dec 31 12:39:56 PM PST 23
Peak memory 200764 kb
Host smart-d5ce0b2c-51d3-4914-ab28-f1b10481a4e5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744646242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.1744646242
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.2106830355
Short name T221
Test name
Test status
Simulation time 333080608804 ps
CPU time 267.17 seconds
Started Dec 31 12:33:16 PM PST 23
Finished Dec 31 12:37:48 PM PST 23
Peak memory 200684 kb
Host smart-ae1e6b6f-0a92-407b-9310-5f984648082a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106830355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.2106830355
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3252618725
Short name T345
Test name
Test status
Simulation time 4252120461 ps
CPU time 6.15 seconds
Started Dec 31 12:43:46 PM PST 23
Finished Dec 31 12:43:53 PM PST 23
Peak memory 200812 kb
Host smart-5e8c3795-edb8-4154-8c83-974b1d0aa9fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252618725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.3252618725
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.417203863
Short name T344
Test name
Test status
Simulation time 8309328340 ps
CPU time 11.98 seconds
Started Dec 31 12:43:28 PM PST 23
Finished Dec 31 12:43:41 PM PST 23
Peak memory 200868 kb
Host smart-289ec821-dbf1-4a92-8cd2-b59c9ca5f3a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417203863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_in
tg_err.417203863
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.2431330528
Short name T16
Test name
Test status
Simulation time 77035764636 ps
CPU time 257.49 seconds
Started Dec 31 12:32:02 PM PST 23
Finished Dec 31 12:36:21 PM PST 23
Peak memory 201220 kb
Host smart-4bbf3a4e-93b0-433b-82cd-c28a43c83db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431330528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.2431330528
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.3502081402
Short name T121
Test name
Test status
Simulation time 480780203028 ps
CPU time 1091.29 seconds
Started Dec 31 12:32:24 PM PST 23
Finished Dec 31 12:50:39 PM PST 23
Peak memory 200740 kb
Host smart-55cba1b4-70e5-4cbf-8c0c-fca7cdce1f47
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502081402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.3502081402
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.3967219660
Short name T323
Test name
Test status
Simulation time 485428785842 ps
CPU time 1165.92 seconds
Started Dec 31 12:32:39 PM PST 23
Finished Dec 31 12:52:06 PM PST 23
Peak memory 200752 kb
Host smart-dd77c4fd-37b0-4d2e-be4d-fcde250c9ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967219660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.3967219660
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.3213797791
Short name T282
Test name
Test status
Simulation time 33854440511 ps
CPU time 79.1 seconds
Started Dec 31 12:32:36 PM PST 23
Finished Dec 31 12:33:56 PM PST 23
Peak memory 209468 kb
Host smart-d7a9d7ed-0a4a-465a-b687-e4d09635417a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213797791 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.3213797791
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.3437225365
Short name T341
Test name
Test status
Simulation time 487755799934 ps
CPU time 200.41 seconds
Started Dec 31 12:32:10 PM PST 23
Finished Dec 31 12:35:31 PM PST 23
Peak memory 200704 kb
Host smart-817e40c7-4e52-4269-acc3-387a17ec8f35
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437225365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.3437225365
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.1723492268
Short name T164
Test name
Test status
Simulation time 337265975837 ps
CPU time 244.41 seconds
Started Dec 31 12:33:22 PM PST 23
Finished Dec 31 12:37:28 PM PST 23
Peak memory 209208 kb
Host smart-7b04ff24-27f4-425a-8924-b58a1bd8a781
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723492268 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.1723492268
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.3310853366
Short name T276
Test name
Test status
Simulation time 70145639574 ps
CPU time 107.87 seconds
Started Dec 31 12:32:17 PM PST 23
Finished Dec 31 12:34:08 PM PST 23
Peak memory 216868 kb
Host smart-60954b8c-9bfb-419e-9462-8039ffda57e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310853366 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.3310853366
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.3255721292
Short name T214
Test name
Test status
Simulation time 491953623801 ps
CPU time 614.75 seconds
Started Dec 31 12:33:32 PM PST 23
Finished Dec 31 12:43:53 PM PST 23
Peak memory 200756 kb
Host smart-fa743696-d120-45bb-95c1-d99d8d0d251d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255721292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.3255721292
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.1677958997
Short name T187
Test name
Test status
Simulation time 76909529934 ps
CPU time 284.57 seconds
Started Dec 31 12:33:45 PM PST 23
Finished Dec 31 12:38:34 PM PST 23
Peak memory 201100 kb
Host smart-2dc940b6-bd9c-4809-ae72-e93c82533ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677958997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.1677958997
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.3034267567
Short name T245
Test name
Test status
Simulation time 340244227891 ps
CPU time 423.58 seconds
Started Dec 31 12:33:38 PM PST 23
Finished Dec 31 12:40:44 PM PST 23
Peak memory 200680 kb
Host smart-cf78e191-e296-4bcb-a41d-5f8195b79631
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034267567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.3034267567
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.3032897971
Short name T135
Test name
Test status
Simulation time 494646293535 ps
CPU time 262.13 seconds
Started Dec 31 12:33:48 PM PST 23
Finished Dec 31 12:38:12 PM PST 23
Peak memory 200772 kb
Host smart-1f27d298-64ea-465a-ac5e-53560e40446e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032897971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.3032897971
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.2221274670
Short name T118
Test name
Test status
Simulation time 500089503463 ps
CPU time 1143.15 seconds
Started Dec 31 12:33:38 PM PST 23
Finished Dec 31 12:52:43 PM PST 23
Peak memory 200744 kb
Host smart-6eadf0b0-0994-45ea-827c-2b5e5b1ce5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221274670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.2221274670
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.1203384354
Short name T210
Test name
Test status
Simulation time 159812456775 ps
CPU time 29.3 seconds
Started Dec 31 12:31:48 PM PST 23
Finished Dec 31 12:32:18 PM PST 23
Peak memory 200740 kb
Host smart-0c9a65b0-c226-4d2c-8893-7c6faa150492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203384354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.1203384354
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.337642957
Short name T267
Test name
Test status
Simulation time 337839070666 ps
CPU time 153.66 seconds
Started Dec 31 12:32:12 PM PST 23
Finished Dec 31 12:34:47 PM PST 23
Peak memory 200784 kb
Host smart-33890715-4ef4-4491-80d0-8dee5ef184ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337642957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.337642957
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1153644826
Short name T76
Test name
Test status
Simulation time 1239112824 ps
CPU time 2.6 seconds
Started Dec 31 12:42:42 PM PST 23
Finished Dec 31 12:42:46 PM PST 23
Peak memory 200628 kb
Host smart-3ad4727d-10c6-4418-968a-d6463f822379
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153644826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.1153644826
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3380867783
Short name T36
Test name
Test status
Simulation time 26965445589 ps
CPU time 43.46 seconds
Started Dec 31 12:42:58 PM PST 23
Finished Dec 31 12:43:42 PM PST 23
Peak memory 200764 kb
Host smart-5c1c320b-5c48-4de5-9967-0f314d31db31
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380867783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.3380867783
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.38508398
Short name T376
Test name
Test status
Simulation time 1162432702 ps
CPU time 1.38 seconds
Started Dec 31 12:42:44 PM PST 23
Finished Dec 31 12:42:47 PM PST 23
Peak memory 200372 kb
Host smart-9b655ebe-0300-451f-8ca7-820da9384c4c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38508398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_res
et.38508398
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1070262281
Short name T899
Test name
Test status
Simulation time 904762235 ps
CPU time 1 seconds
Started Dec 31 12:42:43 PM PST 23
Finished Dec 31 12:42:46 PM PST 23
Peak memory 200608 kb
Host smart-0f57ef81-e5f9-4129-bfb3-d2e21bc264d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070262281 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.1070262281
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1551095604
Short name T897
Test name
Test status
Simulation time 563724449 ps
CPU time 1.05 seconds
Started Dec 31 12:42:45 PM PST 23
Finished Dec 31 12:42:47 PM PST 23
Peak memory 200384 kb
Host smart-9a1ee4ed-24e9-489c-9c26-ab1f87d6acd0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551095604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.1551095604
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1024188204
Short name T398
Test name
Test status
Simulation time 426335809 ps
CPU time 1.07 seconds
Started Dec 31 12:42:43 PM PST 23
Finished Dec 31 12:42:45 PM PST 23
Peak memory 200200 kb
Host smart-fe090af4-a085-4e72-b88d-6b3768278393
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024188204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.1024188204
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2640839979
Short name T900
Test name
Test status
Simulation time 1623503918 ps
CPU time 2.4 seconds
Started Dec 31 12:42:41 PM PST 23
Finished Dec 31 12:42:44 PM PST 23
Peak memory 200452 kb
Host smart-260ccbc5-5119-4554-a772-c503b75f34a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640839979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.2640839979
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.899547416
Short name T379
Test name
Test status
Simulation time 832390510 ps
CPU time 2.5 seconds
Started Dec 31 12:42:39 PM PST 23
Finished Dec 31 12:42:42 PM PST 23
Peak memory 217096 kb
Host smart-9c3f07c1-f7ec-4bfc-8cf7-13e589407a1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899547416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.899547416
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2441832448
Short name T387
Test name
Test status
Simulation time 8506211249 ps
CPU time 6.08 seconds
Started Dec 31 12:43:12 PM PST 23
Finished Dec 31 12:43:19 PM PST 23
Peak memory 200824 kb
Host smart-2b3ab0a8-7f45-4c7c-ba51-5150b0fe1342
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441832448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.2441832448
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3056456174
Short name T73
Test name
Test status
Simulation time 518838438 ps
CPU time 2.38 seconds
Started Dec 31 12:42:43 PM PST 23
Finished Dec 31 12:42:46 PM PST 23
Peak memory 200784 kb
Host smart-f6ab26c5-a206-4bbf-bcfe-a9984e1962be
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056456174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.3056456174
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2909418259
Short name T352
Test name
Test status
Simulation time 52403591850 ps
CPU time 59.73 seconds
Started Dec 31 12:43:13 PM PST 23
Finished Dec 31 12:44:14 PM PST 23
Peak memory 200724 kb
Host smart-cb943ab9-5918-407c-9901-db2d6959b31c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909418259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.2909418259
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.913761394
Short name T71
Test name
Test status
Simulation time 1013968741 ps
CPU time 3.02 seconds
Started Dec 31 12:42:43 PM PST 23
Finished Dec 31 12:42:47 PM PST 23
Peak memory 200496 kb
Host smart-a7af370c-81aa-4020-9741-58a76ea0203a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913761394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_re
set.913761394
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3843331170
Short name T400
Test name
Test status
Simulation time 554310364 ps
CPU time 1.31 seconds
Started Dec 31 12:43:23 PM PST 23
Finished Dec 31 12:43:25 PM PST 23
Peak memory 200656 kb
Host smart-0deb95a1-899e-41be-94d6-b7ee23320467
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843331170 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.3843331170
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.717789400
Short name T905
Test name
Test status
Simulation time 518986826 ps
CPU time 1.34 seconds
Started Dec 31 12:43:15 PM PST 23
Finished Dec 31 12:43:17 PM PST 23
Peak memory 200384 kb
Host smart-2d9c9d0d-5dd3-452f-b98f-1b9d45ecfce3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717789400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.717789400
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.2412871947
Short name T912
Test name
Test status
Simulation time 402686065 ps
CPU time 0.85 seconds
Started Dec 31 12:42:46 PM PST 23
Finished Dec 31 12:42:47 PM PST 23
Peak memory 200068 kb
Host smart-8f173176-d748-4d2a-94ee-b06ca5a51ba2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412871947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.2412871947
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.201836325
Short name T374
Test name
Test status
Simulation time 2712200581 ps
CPU time 3.05 seconds
Started Dec 31 12:43:20 PM PST 23
Finished Dec 31 12:43:24 PM PST 23
Peak memory 200624 kb
Host smart-24dcbbc2-af70-4c0f-a984-618a54c7d0df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201836325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ct
rl_same_csr_outstanding.201836325
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.226148634
Short name T364
Test name
Test status
Simulation time 490890686 ps
CPU time 2.85 seconds
Started Dec 31 12:42:50 PM PST 23
Finished Dec 31 12:42:54 PM PST 23
Peak memory 200792 kb
Host smart-8dddd613-a1c6-4ec0-b07e-b0cc2e851b11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226148634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.226148634
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1832757497
Short name T44
Test name
Test status
Simulation time 4508248522 ps
CPU time 11.94 seconds
Started Dec 31 12:42:44 PM PST 23
Finished Dec 31 12:42:57 PM PST 23
Peak memory 200876 kb
Host smart-ea7eb537-9426-498d-88fe-eb74b7567b0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832757497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.1832757497
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.287095356
Short name T877
Test name
Test status
Simulation time 533027476 ps
CPU time 1.33 seconds
Started Dec 31 12:43:30 PM PST 23
Finished Dec 31 12:43:33 PM PST 23
Peak memory 200608 kb
Host smart-bca73ef3-00d2-4431-a46b-7208b4558a60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287095356 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.287095356
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.4271988492
Short name T75
Test name
Test status
Simulation time 424707885 ps
CPU time 0.94 seconds
Started Dec 31 12:43:33 PM PST 23
Finished Dec 31 12:43:37 PM PST 23
Peak memory 200488 kb
Host smart-bbad0c86-9df2-44f3-93f8-2be49d7aaf10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271988492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.4271988492
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.407018748
Short name T411
Test name
Test status
Simulation time 304279405 ps
CPU time 0.76 seconds
Started Dec 31 12:43:15 PM PST 23
Finished Dec 31 12:43:17 PM PST 23
Peak memory 200240 kb
Host smart-fde17186-d3b5-4fea-ac8e-4c7e345e2d91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407018748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.407018748
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.1497116545
Short name T377
Test name
Test status
Simulation time 4807405721 ps
CPU time 11.17 seconds
Started Dec 31 12:43:15 PM PST 23
Finished Dec 31 12:43:27 PM PST 23
Peak memory 200764 kb
Host smart-f1a2de38-3e21-4452-8665-74e38c8af197
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497116545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.1497116545
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1468453262
Short name T889
Test name
Test status
Simulation time 451117529 ps
CPU time 3.32 seconds
Started Dec 31 12:43:38 PM PST 23
Finished Dec 31 12:43:43 PM PST 23
Peak memory 200792 kb
Host smart-b86c2562-8db4-49aa-a5bf-8f1f86360024
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468453262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.1468453262
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1172070333
Short name T402
Test name
Test status
Simulation time 4309129583 ps
CPU time 11.48 seconds
Started Dec 31 12:43:30 PM PST 23
Finished Dec 31 12:43:42 PM PST 23
Peak memory 200860 kb
Host smart-dca26a70-0f99-4261-8b9f-55915f5549a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172070333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.1172070333
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1842938818
Short name T890
Test name
Test status
Simulation time 586950893 ps
CPU time 1.49 seconds
Started Dec 31 12:43:40 PM PST 23
Finished Dec 31 12:43:43 PM PST 23
Peak memory 200576 kb
Host smart-f43c7ee4-6e56-4510-b314-8309f766b2d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842938818 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.1842938818
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3809900895
Short name T67
Test name
Test status
Simulation time 368965468 ps
CPU time 0.95 seconds
Started Dec 31 12:43:33 PM PST 23
Finished Dec 31 12:43:41 PM PST 23
Peak memory 200556 kb
Host smart-b60e65d8-1464-4933-ab97-c3b6532b0543
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809900895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.3809900895
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3621678844
Short name T869
Test name
Test status
Simulation time 486478300 ps
CPU time 0.94 seconds
Started Dec 31 12:43:13 PM PST 23
Finished Dec 31 12:43:15 PM PST 23
Peak memory 200144 kb
Host smart-2f11f968-1379-448c-8fe9-f4cc6f010d39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621678844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.3621678844
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2992704668
Short name T78
Test name
Test status
Simulation time 3036429958 ps
CPU time 7.76 seconds
Started Dec 31 12:43:13 PM PST 23
Finished Dec 31 12:43:22 PM PST 23
Peak memory 200560 kb
Host smart-30f64229-b8a6-4634-bc79-f2ceb309404e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992704668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.2992704668
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2902659518
Short name T871
Test name
Test status
Simulation time 1289048364 ps
CPU time 1.47 seconds
Started Dec 31 12:43:23 PM PST 23
Finished Dec 31 12:43:26 PM PST 23
Peak memory 200784 kb
Host smart-2c5a29f9-7d2e-40a3-8e49-a49c24369002
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902659518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.2902659518
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.625313893
Short name T399
Test name
Test status
Simulation time 353356998 ps
CPU time 0.92 seconds
Started Dec 31 12:43:18 PM PST 23
Finished Dec 31 12:43:20 PM PST 23
Peak memory 200608 kb
Host smart-101c0f68-e757-4a8e-a485-719ab8b0a5a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625313893 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.625313893
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3974186406
Short name T883
Test name
Test status
Simulation time 441558528 ps
CPU time 1.67 seconds
Started Dec 31 12:43:12 PM PST 23
Finished Dec 31 12:43:14 PM PST 23
Peak memory 200540 kb
Host smart-b29b5681-1f0c-461a-a70b-151a9179cc1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974186406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.3974186406
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1075612243
Short name T878
Test name
Test status
Simulation time 470503455 ps
CPU time 1.21 seconds
Started Dec 31 12:43:16 PM PST 23
Finished Dec 31 12:43:18 PM PST 23
Peak memory 200240 kb
Host smart-6a0b3f76-020e-459b-bb11-8a5db6a79fd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075612243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.1075612243
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.1299482023
Short name T381
Test name
Test status
Simulation time 2250099745 ps
CPU time 8.25 seconds
Started Dec 31 12:43:31 PM PST 23
Finished Dec 31 12:43:47 PM PST 23
Peak memory 200536 kb
Host smart-f9839e37-4cfe-4994-bb4a-e3e30a079524
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299482023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.1299482023
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.2969258566
Short name T365
Test name
Test status
Simulation time 674621779 ps
CPU time 3.48 seconds
Started Dec 31 12:43:30 PM PST 23
Finished Dec 31 12:43:35 PM PST 23
Peak memory 200752 kb
Host smart-c5cb6d38-50d0-4dae-8806-8db5db3c275e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969258566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.2969258566
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1815246255
Short name T898
Test name
Test status
Simulation time 4522651475 ps
CPU time 12 seconds
Started Dec 31 12:43:46 PM PST 23
Finished Dec 31 12:43:58 PM PST 23
Peak memory 200804 kb
Host smart-b7792ceb-34f6-4282-b02e-44f6d7a55d88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815246255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.1815246255
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3239662538
Short name T895
Test name
Test status
Simulation time 374006280 ps
CPU time 1.65 seconds
Started Dec 31 12:43:18 PM PST 23
Finished Dec 31 12:43:20 PM PST 23
Peak memory 200608 kb
Host smart-77eb0fb9-001e-488b-b1f6-1c665944cc3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239662538 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.3239662538
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.410084234
Short name T64
Test name
Test status
Simulation time 524310707 ps
CPU time 1.02 seconds
Started Dec 31 12:43:17 PM PST 23
Finished Dec 31 12:43:19 PM PST 23
Peak memory 200484 kb
Host smart-8054e0b9-70b7-44b2-b452-4160c251a93c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410084234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.410084234
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.4142544757
Short name T388
Test name
Test status
Simulation time 326827130 ps
CPU time 1.39 seconds
Started Dec 31 12:43:17 PM PST 23
Finished Dec 31 12:43:19 PM PST 23
Peak memory 200424 kb
Host smart-d1386321-13a0-485d-9fb8-0c398c5ad5f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142544757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.4142544757
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.4234530832
Short name T904
Test name
Test status
Simulation time 1897457613 ps
CPU time 1.74 seconds
Started Dec 31 12:43:24 PM PST 23
Finished Dec 31 12:43:27 PM PST 23
Peak memory 200456 kb
Host smart-7c180170-4c43-4d8d-b7dc-4403547b31c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234530832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.4234530832
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3976753284
Short name T896
Test name
Test status
Simulation time 4521750408 ps
CPU time 11.85 seconds
Started Dec 31 12:43:13 PM PST 23
Finished Dec 31 12:43:25 PM PST 23
Peak memory 200848 kb
Host smart-768c35fb-2ec9-444a-915f-9854e617f86f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976753284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.3976753284
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3128514620
Short name T902
Test name
Test status
Simulation time 455713653 ps
CPU time 1.1 seconds
Started Dec 31 12:43:16 PM PST 23
Finished Dec 31 12:43:18 PM PST 23
Peak memory 200584 kb
Host smart-b180a8bc-3594-40e2-b96e-060fb42256a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128514620 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.3128514620
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.762073363
Short name T74
Test name
Test status
Simulation time 540955222 ps
CPU time 1.19 seconds
Started Dec 31 12:43:16 PM PST 23
Finished Dec 31 12:43:18 PM PST 23
Peak memory 200524 kb
Host smart-e06818a0-f7fd-4ee1-a396-cb079764bba6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762073363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.762073363
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.831756150
Short name T383
Test name
Test status
Simulation time 345677460 ps
CPU time 1.39 seconds
Started Dec 31 12:43:02 PM PST 23
Finished Dec 31 12:43:04 PM PST 23
Peak memory 200160 kb
Host smart-50ab12a3-b931-4270-b733-a1eaa983ee80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831756150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.831756150
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1436223429
Short name T893
Test name
Test status
Simulation time 4899050431 ps
CPU time 2.3 seconds
Started Dec 31 12:43:34 PM PST 23
Finished Dec 31 12:43:39 PM PST 23
Peak memory 200796 kb
Host smart-e8790347-e4c4-4c31-9d05-5d2b0b7fb84e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436223429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.1436223429
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2959374148
Short name T882
Test name
Test status
Simulation time 437652973 ps
CPU time 2.93 seconds
Started Dec 31 12:43:14 PM PST 23
Finished Dec 31 12:43:18 PM PST 23
Peak memory 200684 kb
Host smart-9518eec9-4d74-4c89-a264-28a2b63db5ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959374148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.2959374148
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3317843138
Short name T358
Test name
Test status
Simulation time 577151635 ps
CPU time 2.09 seconds
Started Dec 31 12:43:19 PM PST 23
Finished Dec 31 12:43:22 PM PST 23
Peak memory 200576 kb
Host smart-888b0d05-97d2-45c4-b59b-24eacd825ef0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317843138 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.3317843138
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3285132738
Short name T362
Test name
Test status
Simulation time 494269280 ps
CPU time 0.98 seconds
Started Dec 31 12:43:25 PM PST 23
Finished Dec 31 12:43:27 PM PST 23
Peak memory 200480 kb
Host smart-94579224-8608-4c5a-96f2-8a75d42f5403
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285132738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.3285132738
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2891539914
Short name T31
Test name
Test status
Simulation time 2040027534 ps
CPU time 4.33 seconds
Started Dec 31 12:43:47 PM PST 23
Finished Dec 31 12:43:52 PM PST 23
Peak memory 200500 kb
Host smart-37ecb4b9-d146-4836-b982-4e3323bc89fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891539914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.2891539914
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.2535705319
Short name T361
Test name
Test status
Simulation time 441856399 ps
CPU time 2.3 seconds
Started Dec 31 12:43:20 PM PST 23
Finished Dec 31 12:43:23 PM PST 23
Peak memory 200764 kb
Host smart-63291802-b9a9-4516-b2fc-d48f3316569e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535705319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.2535705319
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3223951879
Short name T343
Test name
Test status
Simulation time 8039009369 ps
CPU time 19.41 seconds
Started Dec 31 12:43:05 PM PST 23
Finished Dec 31 12:43:25 PM PST 23
Peak memory 200812 kb
Host smart-4a5c3717-e500-42bb-8eb6-e74589394f26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223951879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.3223951879
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1826772650
Short name T913
Test name
Test status
Simulation time 519876262 ps
CPU time 1.97 seconds
Started Dec 31 12:43:19 PM PST 23
Finished Dec 31 12:43:22 PM PST 23
Peak memory 200572 kb
Host smart-fdfc1ae5-c440-4669-982f-15a564e1e4e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826772650 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.1826772650
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2345086439
Short name T30
Test name
Test status
Simulation time 596154798 ps
CPU time 0.92 seconds
Started Dec 31 12:43:20 PM PST 23
Finished Dec 31 12:43:21 PM PST 23
Peak memory 200528 kb
Host smart-6f17555f-41c8-4b43-ba83-35894aa1aa14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345086439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.2345086439
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1556120888
Short name T880
Test name
Test status
Simulation time 538695083 ps
CPU time 0.94 seconds
Started Dec 31 12:43:12 PM PST 23
Finished Dec 31 12:43:13 PM PST 23
Peak memory 200224 kb
Host smart-c35f61fc-2003-43e8-805b-3570c29c4dd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556120888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.1556120888
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1128782266
Short name T910
Test name
Test status
Simulation time 5081650414 ps
CPU time 19 seconds
Started Dec 31 12:43:28 PM PST 23
Finished Dec 31 12:43:48 PM PST 23
Peak memory 200656 kb
Host smart-6559d4fe-f186-4637-92a8-206365d7c822
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128782266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.1128782266
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.1437352693
Short name T61
Test name
Test status
Simulation time 534890015 ps
CPU time 2.85 seconds
Started Dec 31 12:43:30 PM PST 23
Finished Dec 31 12:43:34 PM PST 23
Peak memory 200800 kb
Host smart-fb598147-3ea8-4235-ae3e-211a9d08eb1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437352693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.1437352693
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.2874846788
Short name T886
Test name
Test status
Simulation time 554905468 ps
CPU time 2.11 seconds
Started Dec 31 12:43:49 PM PST 23
Finished Dec 31 12:43:56 PM PST 23
Peak memory 200648 kb
Host smart-1ac2219c-1e15-44bd-8f7c-35cc5a62d9ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874846788 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.2874846788
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1891560526
Short name T909
Test name
Test status
Simulation time 279073684 ps
CPU time 1.35 seconds
Started Dec 31 12:43:33 PM PST 23
Finished Dec 31 12:43:37 PM PST 23
Peak memory 200508 kb
Host smart-c6dd60b1-67d9-4025-9c8f-06ee9c583d01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891560526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.1891560526
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.4180642740
Short name T870
Test name
Test status
Simulation time 543018058 ps
CPU time 0.87 seconds
Started Dec 31 12:43:55 PM PST 23
Finished Dec 31 12:44:10 PM PST 23
Peak memory 200456 kb
Host smart-d043b9fb-e207-495a-8052-ca5a1b49455d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180642740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.4180642740
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.550395416
Short name T37
Test name
Test status
Simulation time 2654986750 ps
CPU time 6.09 seconds
Started Dec 31 12:43:30 PM PST 23
Finished Dec 31 12:43:37 PM PST 23
Peak memory 200592 kb
Host smart-33b32875-98eb-40a0-b00b-5dcf26b87db7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550395416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_c
trl_same_csr_outstanding.550395416
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2887362486
Short name T58
Test name
Test status
Simulation time 890023774 ps
CPU time 2.43 seconds
Started Dec 31 12:43:12 PM PST 23
Finished Dec 31 12:43:16 PM PST 23
Peak memory 200808 kb
Host smart-212f60e8-e2d2-42db-8433-dda22b23e9ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887362486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.2887362486
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.21325844
Short name T892
Test name
Test status
Simulation time 4163377038 ps
CPU time 3.47 seconds
Started Dec 31 12:43:13 PM PST 23
Finished Dec 31 12:43:17 PM PST 23
Peak memory 200732 kb
Host smart-d7ad18ba-739f-4b0c-ac59-99691fe8bdc8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21325844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_int
g_err.21325844
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.741790012
Short name T10
Test name
Test status
Simulation time 433505846 ps
CPU time 0.94 seconds
Started Dec 31 12:43:23 PM PST 23
Finished Dec 31 12:43:25 PM PST 23
Peak memory 200552 kb
Host smart-85e8f2d3-49c5-4ad4-96e8-30e8516bb971
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741790012 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.741790012
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.3476483247
Short name T393
Test name
Test status
Simulation time 495398545 ps
CPU time 1.07 seconds
Started Dec 31 12:43:47 PM PST 23
Finished Dec 31 12:43:49 PM PST 23
Peak memory 200232 kb
Host smart-9f212b9e-b727-465c-b03d-e1cb1ac03b34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476483247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.3476483247
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2459986059
Short name T396
Test name
Test status
Simulation time 3044088240 ps
CPU time 12.19 seconds
Started Dec 31 12:43:33 PM PST 23
Finished Dec 31 12:43:47 PM PST 23
Peak memory 200788 kb
Host smart-581cd527-d966-43f3-84ef-90e0bf7cdffb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459986059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.2459986059
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.436730432
Short name T911
Test name
Test status
Simulation time 478170496 ps
CPU time 2.82 seconds
Started Dec 31 12:43:22 PM PST 23
Finished Dec 31 12:43:26 PM PST 23
Peak memory 200752 kb
Host smart-0a2f40c1-d50e-4820-b310-13060c71a834
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436730432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.436730432
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.499983950
Short name T34
Test name
Test status
Simulation time 7945969844 ps
CPU time 19.34 seconds
Started Dec 31 12:43:50 PM PST 23
Finished Dec 31 12:44:13 PM PST 23
Peak memory 200788 kb
Host smart-29b3afc4-7c82-4ba9-8fef-9e098fe89e54
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499983950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_in
tg_err.499983950
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2064094941
Short name T866
Test name
Test status
Simulation time 487411210 ps
CPU time 1.11 seconds
Started Dec 31 12:43:30 PM PST 23
Finished Dec 31 12:43:32 PM PST 23
Peak memory 200524 kb
Host smart-e931d898-8a0b-41db-afcd-f81bfc505c2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064094941 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.2064094941
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3092323195
Short name T363
Test name
Test status
Simulation time 409602766 ps
CPU time 0.92 seconds
Started Dec 31 12:43:29 PM PST 23
Finished Dec 31 12:43:31 PM PST 23
Peak memory 200540 kb
Host smart-c82837aa-30a5-4deb-939c-57c6692c7020
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092323195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.3092323195
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1392399860
Short name T887
Test name
Test status
Simulation time 465800121 ps
CPU time 0.88 seconds
Started Dec 31 12:43:54 PM PST 23
Finished Dec 31 12:44:06 PM PST 23
Peak memory 200428 kb
Host smart-241a0933-313c-437c-84b5-52fc04606705
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392399860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.1392399860
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2929051262
Short name T907
Test name
Test status
Simulation time 2317820731 ps
CPU time 2.16 seconds
Started Dec 31 12:43:30 PM PST 23
Finished Dec 31 12:43:33 PM PST 23
Peak memory 200604 kb
Host smart-60f8ac38-5104-4c48-b64a-081a54a8437e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929051262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.2929051262
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1564609998
Short name T879
Test name
Test status
Simulation time 623012065 ps
CPU time 3.45 seconds
Started Dec 31 12:43:51 PM PST 23
Finished Dec 31 12:43:58 PM PST 23
Peak memory 200768 kb
Host smart-09e77d31-07f4-472c-a3ae-a43300d321eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564609998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.1564609998
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1663638648
Short name T414
Test name
Test status
Simulation time 8598715745 ps
CPU time 12.41 seconds
Started Dec 31 12:43:44 PM PST 23
Finished Dec 31 12:43:57 PM PST 23
Peak memory 200812 kb
Host smart-736e9f74-bed2-43c0-907e-cb02e168b919
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663638648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.1663638648
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1166080387
Short name T11
Test name
Test status
Simulation time 772390355 ps
CPU time 2.98 seconds
Started Dec 31 12:43:33 PM PST 23
Finished Dec 31 12:43:39 PM PST 23
Peak memory 200732 kb
Host smart-652adebd-d392-4b3f-b28b-0ee0b570e128
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166080387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.1166080387
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1533602913
Short name T903
Test name
Test status
Simulation time 681284580 ps
CPU time 1.06 seconds
Started Dec 31 12:43:19 PM PST 23
Finished Dec 31 12:43:20 PM PST 23
Peak memory 200560 kb
Host smart-7815b9e6-29c9-4706-b202-249f3356160c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533602913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.1533602913
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3597967901
Short name T43
Test name
Test status
Simulation time 534002669 ps
CPU time 2.1 seconds
Started Dec 31 12:42:53 PM PST 23
Finished Dec 31 12:42:56 PM PST 23
Peak memory 200612 kb
Host smart-31383dc7-a6e4-4d21-8d81-89a2baa76476
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597967901 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.3597967901
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1258560399
Short name T867
Test name
Test status
Simulation time 389459341 ps
CPU time 1.57 seconds
Started Dec 31 12:43:30 PM PST 23
Finished Dec 31 12:43:32 PM PST 23
Peak memory 200540 kb
Host smart-6bd75914-2d07-49b7-9bd0-4237d67a0301
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258560399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.1258560399
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.271587607
Short name T888
Test name
Test status
Simulation time 424343100 ps
CPU time 0.74 seconds
Started Dec 31 12:43:12 PM PST 23
Finished Dec 31 12:43:13 PM PST 23
Peak memory 200228 kb
Host smart-844e2090-bf51-4bcb-b2fd-bb41a5914477
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271587607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.271587607
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.478523483
Short name T7
Test name
Test status
Simulation time 4517827147 ps
CPU time 5.89 seconds
Started Dec 31 12:43:00 PM PST 23
Finished Dec 31 12:43:07 PM PST 23
Peak memory 200736 kb
Host smart-66cc9695-a8ab-43da-bf8a-d02cd455bd63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478523483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ct
rl_same_csr_outstanding.478523483
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2678991895
Short name T366
Test name
Test status
Simulation time 4477938996 ps
CPU time 6.99 seconds
Started Dec 31 12:42:58 PM PST 23
Finished Dec 31 12:43:06 PM PST 23
Peak memory 200728 kb
Host smart-b5825582-564f-47b5-9650-2cc5f51e9cee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678991895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.2678991895
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.65429368
Short name T908
Test name
Test status
Simulation time 535815154 ps
CPU time 0.99 seconds
Started Dec 31 12:43:32 PM PST 23
Finished Dec 31 12:43:34 PM PST 23
Peak memory 200240 kb
Host smart-f83f1a5f-6c83-4c73-b876-6b987cb4eb31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65429368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.65429368
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.387581205
Short name T353
Test name
Test status
Simulation time 348715758 ps
CPU time 1.04 seconds
Started Dec 31 12:43:52 PM PST 23
Finished Dec 31 12:44:00 PM PST 23
Peak memory 200284 kb
Host smart-845f32d9-3fe4-4947-9fd0-7e8ff7245f19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387581205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.387581205
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.3450019078
Short name T407
Test name
Test status
Simulation time 552825170 ps
CPU time 0.91 seconds
Started Dec 31 12:43:44 PM PST 23
Finished Dec 31 12:43:46 PM PST 23
Peak memory 200204 kb
Host smart-87081f99-33c2-4242-bb8c-8cdc41349f8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450019078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.3450019078
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3152240773
Short name T370
Test name
Test status
Simulation time 348881330 ps
CPU time 0.8 seconds
Started Dec 31 12:43:58 PM PST 23
Finished Dec 31 12:44:10 PM PST 23
Peak memory 200276 kb
Host smart-da065eea-e110-43eb-918b-f8f299ac0f15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152240773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.3152240773
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3459753289
Short name T355
Test name
Test status
Simulation time 542285694 ps
CPU time 0.81 seconds
Started Dec 31 12:43:40 PM PST 23
Finished Dec 31 12:43:43 PM PST 23
Peak memory 200196 kb
Host smart-45b1216c-1d9d-4332-bf99-2b516b2088a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459753289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.3459753289
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.3583430868
Short name T368
Test name
Test status
Simulation time 350035000 ps
CPU time 1.4 seconds
Started Dec 31 12:43:36 PM PST 23
Finished Dec 31 12:43:44 PM PST 23
Peak memory 200424 kb
Host smart-02f8950e-92b5-4325-af00-5f092788dcf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583430868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.3583430868
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.377955377
Short name T28
Test name
Test status
Simulation time 506053723 ps
CPU time 1.14 seconds
Started Dec 31 12:43:48 PM PST 23
Finished Dec 31 12:43:50 PM PST 23
Peak memory 200108 kb
Host smart-49cfe172-69aa-4408-975a-3125359cda4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377955377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.377955377
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.1395930143
Short name T401
Test name
Test status
Simulation time 460675091 ps
CPU time 0.94 seconds
Started Dec 31 12:44:03 PM PST 23
Finished Dec 31 12:44:14 PM PST 23
Peak memory 200304 kb
Host smart-2f066c68-d560-423a-ac87-b4ddfe3ed036
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395930143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.1395930143
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.1081720068
Short name T874
Test name
Test status
Simulation time 486638154 ps
CPU time 1 seconds
Started Dec 31 12:43:56 PM PST 23
Finished Dec 31 12:44:10 PM PST 23
Peak memory 200140 kb
Host smart-d0aeef5e-99d7-4ed9-9f41-c04ec3c1d21a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081720068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.1081720068
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.2109364951
Short name T354
Test name
Test status
Simulation time 289906872 ps
CPU time 1.02 seconds
Started Dec 31 12:43:40 PM PST 23
Finished Dec 31 12:43:43 PM PST 23
Peak memory 200268 kb
Host smart-d099dca8-f1e0-4ff9-a562-25fcbde0f938
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109364951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.2109364951
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2009358875
Short name T70
Test name
Test status
Simulation time 876919876 ps
CPU time 2.64 seconds
Started Dec 31 12:42:49 PM PST 23
Finished Dec 31 12:42:52 PM PST 23
Peak memory 200740 kb
Host smart-5a4db7de-e14d-4ec3-acf8-3413dfae313b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009358875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.2009358875
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.4235574273
Short name T68
Test name
Test status
Simulation time 19003613185 ps
CPU time 45.05 seconds
Started Dec 31 12:43:15 PM PST 23
Finished Dec 31 12:44:00 PM PST 23
Peak memory 200800 kb
Host smart-fd77c455-d844-4ef6-843b-1c5f9bf65e2f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235574273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.4235574273
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.441173586
Short name T389
Test name
Test status
Simulation time 866840435 ps
CPU time 1.65 seconds
Started Dec 31 12:43:14 PM PST 23
Finished Dec 31 12:43:16 PM PST 23
Peak memory 200468 kb
Host smart-ff57442e-22d3-4658-9ce5-710ac073f956
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441173586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_re
set.441173586
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.1603156589
Short name T392
Test name
Test status
Simulation time 527448209 ps
CPU time 1.9 seconds
Started Dec 31 12:42:51 PM PST 23
Finished Dec 31 12:42:53 PM PST 23
Peak memory 200564 kb
Host smart-982b687d-3dab-4da0-8a98-54cc834a6d73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603156589 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.1603156589
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.676471046
Short name T395
Test name
Test status
Simulation time 475790129 ps
CPU time 1.73 seconds
Started Dec 31 12:42:58 PM PST 23
Finished Dec 31 12:43:01 PM PST 23
Peak memory 200484 kb
Host smart-6e566495-4aae-4b05-9cdd-cdd4c3ec7145
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676471046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.676471046
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2863408640
Short name T409
Test name
Test status
Simulation time 311100789 ps
CPU time 0.91 seconds
Started Dec 31 12:43:19 PM PST 23
Finished Dec 31 12:43:21 PM PST 23
Peak memory 200224 kb
Host smart-35e972c5-1820-4b90-9162-3b39782eccf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863408640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.2863408640
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2437955275
Short name T66
Test name
Test status
Simulation time 4262195251 ps
CPU time 13.8 seconds
Started Dec 31 12:43:23 PM PST 23
Finished Dec 31 12:43:37 PM PST 23
Peak memory 200812 kb
Host smart-63084709-3c8f-41fc-819c-fd8a4494e2f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437955275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.2437955275
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2133905467
Short name T397
Test name
Test status
Simulation time 566892379 ps
CPU time 1.22 seconds
Started Dec 31 12:42:47 PM PST 23
Finished Dec 31 12:42:49 PM PST 23
Peak memory 200604 kb
Host smart-1fcf5e0e-3903-46da-95eb-1aea2cd431d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133905467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.2133905467
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.182995514
Short name T876
Test name
Test status
Simulation time 8445454827 ps
CPU time 11.08 seconds
Started Dec 31 12:42:48 PM PST 23
Finished Dec 31 12:43:00 PM PST 23
Peak memory 200868 kb
Host smart-b85cfd02-e766-4e71-832b-97526f5db989
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182995514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_int
g_err.182995514
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.34619508
Short name T32
Test name
Test status
Simulation time 322576960 ps
CPU time 1 seconds
Started Dec 31 12:43:54 PM PST 23
Finished Dec 31 12:44:06 PM PST 23
Peak memory 200188 kb
Host smart-c95edec5-71cc-4730-9644-30c4c84d3c54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34619508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.34619508
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.280771032
Short name T391
Test name
Test status
Simulation time 410999797 ps
CPU time 1.53 seconds
Started Dec 31 12:43:47 PM PST 23
Finished Dec 31 12:43:50 PM PST 23
Peak memory 200476 kb
Host smart-e2ce8a78-0769-40d8-b481-ec6b2df7a1f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280771032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.280771032
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1140303391
Short name T4
Test name
Test status
Simulation time 509286612 ps
CPU time 1.21 seconds
Started Dec 31 12:44:06 PM PST 23
Finished Dec 31 12:44:18 PM PST 23
Peak memory 200252 kb
Host smart-494a12f5-5b64-47df-b839-320792673668
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140303391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.1140303391
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3876325328
Short name T373
Test name
Test status
Simulation time 329698702 ps
CPU time 1.04 seconds
Started Dec 31 12:43:23 PM PST 23
Finished Dec 31 12:43:25 PM PST 23
Peak memory 200216 kb
Host smart-b1a8db7d-b298-49c7-b60b-eea1069cf1be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876325328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.3876325328
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.2200793532
Short name T884
Test name
Test status
Simulation time 378784866 ps
CPU time 1.5 seconds
Started Dec 31 12:43:24 PM PST 23
Finished Dec 31 12:43:26 PM PST 23
Peak memory 200220 kb
Host smart-487d14ff-4f00-4c05-b3fb-cc7dc8c442f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200793532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.2200793532
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2611636421
Short name T394
Test name
Test status
Simulation time 393153237 ps
CPU time 1.05 seconds
Started Dec 31 12:43:30 PM PST 23
Finished Dec 31 12:43:32 PM PST 23
Peak memory 200148 kb
Host smart-fc92f92d-277e-4356-a065-457070d35b25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611636421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.2611636421
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3895800413
Short name T875
Test name
Test status
Simulation time 451044182 ps
CPU time 1.68 seconds
Started Dec 31 12:43:16 PM PST 23
Finished Dec 31 12:43:18 PM PST 23
Peak memory 200412 kb
Host smart-2612ecdc-6a34-4ff3-a26a-538828268a4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895800413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.3895800413
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3760973289
Short name T378
Test name
Test status
Simulation time 364626007 ps
CPU time 1.48 seconds
Started Dec 31 12:43:51 PM PST 23
Finished Dec 31 12:43:56 PM PST 23
Peak memory 200376 kb
Host smart-7bf49494-1bf2-4d83-98d9-491df71740e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760973289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.3760973289
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.3639528741
Short name T5
Test name
Test status
Simulation time 472321069 ps
CPU time 1.67 seconds
Started Dec 31 12:43:47 PM PST 23
Finished Dec 31 12:43:50 PM PST 23
Peak memory 200276 kb
Host smart-a64a5112-57a0-4de3-9840-800802c43db0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639528741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.3639528741
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1282208162
Short name T356
Test name
Test status
Simulation time 725928349 ps
CPU time 1.84 seconds
Started Dec 31 12:43:20 PM PST 23
Finished Dec 31 12:43:22 PM PST 23
Peak memory 200748 kb
Host smart-36722ccf-c05d-4c23-b9fc-ffdf34201095
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282208162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.1282208162
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.644543336
Short name T69
Test name
Test status
Simulation time 905704236 ps
CPU time 5.61 seconds
Started Dec 31 12:43:21 PM PST 23
Finished Dec 31 12:43:27 PM PST 23
Peak memory 200972 kb
Host smart-307796dd-6074-4057-8722-28d3f1305f5e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644543336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_b
ash.644543336
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2004030466
Short name T359
Test name
Test status
Simulation time 753364853 ps
CPU time 1.01 seconds
Started Dec 31 12:43:32 PM PST 23
Finished Dec 31 12:43:34 PM PST 23
Peak memory 200556 kb
Host smart-3049160a-06e8-4f7b-b3aa-5f8609b54267
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004030466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.2004030466
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.359100540
Short name T9
Test name
Test status
Simulation time 645014196 ps
CPU time 1.2 seconds
Started Dec 31 12:43:13 PM PST 23
Finished Dec 31 12:43:15 PM PST 23
Peak memory 200596 kb
Host smart-704c1d8e-367d-48c5-94bd-4426050f269d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359100540 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.359100540
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1395842152
Short name T3
Test name
Test status
Simulation time 350083461 ps
CPU time 0.89 seconds
Started Dec 31 12:43:43 PM PST 23
Finished Dec 31 12:43:45 PM PST 23
Peak memory 200484 kb
Host smart-ec3b73ac-5032-4afe-8872-77196e2499d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395842152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.1395842152
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2198354516
Short name T360
Test name
Test status
Simulation time 293746254 ps
CPU time 1.3 seconds
Started Dec 31 12:43:27 PM PST 23
Finished Dec 31 12:43:29 PM PST 23
Peak memory 200156 kb
Host smart-3af46f69-f1d9-40db-8d01-9b43a39b06c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198354516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.2198354516
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.4116081653
Short name T357
Test name
Test status
Simulation time 2510708423 ps
CPU time 5.73 seconds
Started Dec 31 12:43:31 PM PST 23
Finished Dec 31 12:43:38 PM PST 23
Peak memory 200608 kb
Host smart-bedd85d7-2123-4846-b420-569201e1883c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116081653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.4116081653
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2941975540
Short name T62
Test name
Test status
Simulation time 1046661991 ps
CPU time 3.03 seconds
Started Dec 31 12:43:07 PM PST 23
Finished Dec 31 12:43:11 PM PST 23
Peak memory 216468 kb
Host smart-94cc22e7-d960-4261-a898-d517fd676276
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941975540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.2941975540
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2844219771
Short name T63
Test name
Test status
Simulation time 8317256432 ps
CPU time 10.71 seconds
Started Dec 31 12:43:21 PM PST 23
Finished Dec 31 12:43:32 PM PST 23
Peak memory 200776 kb
Host smart-583db83b-3651-4ee6-97a1-83af172acd91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844219771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.2844219771
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1182451873
Short name T380
Test name
Test status
Simulation time 513953512 ps
CPU time 0.8 seconds
Started Dec 31 12:43:23 PM PST 23
Finished Dec 31 12:43:25 PM PST 23
Peak memory 200212 kb
Host smart-c6b83ad6-e7d6-47e8-bc19-8ec105189663
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182451873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.1182451873
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2404681603
Short name T873
Test name
Test status
Simulation time 446995432 ps
CPU time 0.89 seconds
Started Dec 31 12:43:24 PM PST 23
Finished Dec 31 12:43:26 PM PST 23
Peak memory 200228 kb
Host smart-aff2e6c9-cc27-436c-ab4b-2dcb9e8d89f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404681603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.2404681603
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2717662542
Short name T369
Test name
Test status
Simulation time 437263805 ps
CPU time 1.55 seconds
Started Dec 31 12:43:29 PM PST 23
Finished Dec 31 12:43:32 PM PST 23
Peak memory 200208 kb
Host smart-ca4804f4-aaf5-4ab3-ae9e-329148ed4a20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717662542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.2717662542
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2458999902
Short name T901
Test name
Test status
Simulation time 409623844 ps
CPU time 1.67 seconds
Started Dec 31 12:43:22 PM PST 23
Finished Dec 31 12:43:24 PM PST 23
Peak memory 200188 kb
Host smart-96621da7-8c22-4874-9f38-ba3a270b2b8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458999902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.2458999902
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.4099113701
Short name T865
Test name
Test status
Simulation time 390289879 ps
CPU time 0.69 seconds
Started Dec 31 12:43:42 PM PST 23
Finished Dec 31 12:43:44 PM PST 23
Peak memory 200248 kb
Host smart-83f97c5a-1dd3-4446-9ba4-401cc235b681
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099113701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.4099113701
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.4159423725
Short name T384
Test name
Test status
Simulation time 287059639 ps
CPU time 1.32 seconds
Started Dec 31 12:43:23 PM PST 23
Finished Dec 31 12:43:25 PM PST 23
Peak memory 200236 kb
Host smart-a4dd5a13-3ca7-46dc-9606-9dcde4f1d1fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159423725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.4159423725
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3626602818
Short name T885
Test name
Test status
Simulation time 393289784 ps
CPU time 1.23 seconds
Started Dec 31 12:43:47 PM PST 23
Finished Dec 31 12:43:49 PM PST 23
Peak memory 200216 kb
Host smart-dc7446d4-82f6-491a-aa74-a30f6bf26dd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626602818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.3626602818
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.1914377003
Short name T351
Test name
Test status
Simulation time 327471316 ps
CPU time 1.02 seconds
Started Dec 31 12:43:19 PM PST 23
Finished Dec 31 12:43:20 PM PST 23
Peak memory 200152 kb
Host smart-12cae475-a86e-4d5a-b364-a17cbd301e91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914377003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.1914377003
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2198574269
Short name T894
Test name
Test status
Simulation time 505312019 ps
CPU time 0.66 seconds
Started Dec 31 12:43:43 PM PST 23
Finished Dec 31 12:43:45 PM PST 23
Peak memory 200384 kb
Host smart-0b3eccd3-9d9a-4687-96a5-0facad08dcb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198574269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.2198574269
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.1347688425
Short name T77
Test name
Test status
Simulation time 475354012 ps
CPU time 0.91 seconds
Started Dec 31 12:43:30 PM PST 23
Finished Dec 31 12:43:37 PM PST 23
Peak memory 200232 kb
Host smart-4d4847d1-3c70-4a6f-b406-cb90f93529ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347688425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.1347688425
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1028586532
Short name T390
Test name
Test status
Simulation time 458717554 ps
CPU time 1.24 seconds
Started Dec 31 12:43:45 PM PST 23
Finished Dec 31 12:43:47 PM PST 23
Peak memory 200608 kb
Host smart-392f657f-3a5e-45ce-821b-255ac6f37941
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028586532 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.1028586532
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.771538262
Short name T72
Test name
Test status
Simulation time 494442127 ps
CPU time 1.32 seconds
Started Dec 31 12:43:27 PM PST 23
Finished Dec 31 12:43:29 PM PST 23
Peak memory 200484 kb
Host smart-30159c65-e483-4112-82cf-c1473a4d009b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771538262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.771538262
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.522282743
Short name T406
Test name
Test status
Simulation time 443125995 ps
CPU time 1.52 seconds
Started Dec 31 12:43:25 PM PST 23
Finished Dec 31 12:43:27 PM PST 23
Peak memory 200184 kb
Host smart-891eb79a-c6ce-44a3-9a24-770cc7e95f16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522282743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.522282743
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3264152646
Short name T906
Test name
Test status
Simulation time 5109025947 ps
CPU time 10.94 seconds
Started Dec 31 12:43:24 PM PST 23
Finished Dec 31 12:43:36 PM PST 23
Peak memory 200760 kb
Host smart-70ef267c-65c4-4a46-a8ef-702c82a2b926
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264152646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.3264152646
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1666154411
Short name T386
Test name
Test status
Simulation time 420771031 ps
CPU time 2.69 seconds
Started Dec 31 12:43:40 PM PST 23
Finished Dec 31 12:43:44 PM PST 23
Peak memory 216980 kb
Host smart-b6263691-da01-4d0d-a2d6-061634605977
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666154411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.1666154411
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.503534347
Short name T59
Test name
Test status
Simulation time 8878317996 ps
CPU time 12.29 seconds
Started Dec 31 12:43:48 PM PST 23
Finished Dec 31 12:44:11 PM PST 23
Peak memory 200808 kb
Host smart-8089b120-8b1c-42b8-a4c1-303736d3254c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503534347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_int
g_err.503534347
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3556255498
Short name T382
Test name
Test status
Simulation time 564117454 ps
CPU time 1.09 seconds
Started Dec 31 12:43:12 PM PST 23
Finished Dec 31 12:43:15 PM PST 23
Peak memory 200564 kb
Host smart-95112416-e422-402c-a868-8e37ec219309
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556255498 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.3556255498
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.2571731068
Short name T412
Test name
Test status
Simulation time 523683836 ps
CPU time 1.76 seconds
Started Dec 31 12:43:34 PM PST 23
Finished Dec 31 12:43:38 PM PST 23
Peak memory 200472 kb
Host smart-a4f5a23f-d0f5-4e59-bc1b-8cae17f2de7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571731068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.2571731068
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3719428048
Short name T403
Test name
Test status
Simulation time 519582014 ps
CPU time 1.79 seconds
Started Dec 31 12:43:57 PM PST 23
Finished Dec 31 12:44:11 PM PST 23
Peak memory 200260 kb
Host smart-7722f403-cf9b-4213-9b76-2695fe23f489
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719428048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.3719428048
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.842453156
Short name T65
Test name
Test status
Simulation time 2685213724 ps
CPU time 13.26 seconds
Started Dec 31 12:43:32 PM PST 23
Finished Dec 31 12:43:47 PM PST 23
Peak memory 200684 kb
Host smart-9d3c5d5d-32e4-4055-a354-ccc8874b054c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842453156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ct
rl_same_csr_outstanding.842453156
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1913078064
Short name T25
Test name
Test status
Simulation time 891535656 ps
CPU time 2.93 seconds
Started Dec 31 12:43:59 PM PST 23
Finished Dec 31 12:44:12 PM PST 23
Peak memory 200820 kb
Host smart-2268b1fc-a4d0-4468-801f-4994db32c5be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913078064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.1913078064
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.967447899
Short name T367
Test name
Test status
Simulation time 8365689851 ps
CPU time 21.43 seconds
Started Dec 31 12:43:22 PM PST 23
Finished Dec 31 12:43:44 PM PST 23
Peak memory 200788 kb
Host smart-0a14d8cb-4823-4f70-a647-af8a880e75a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967447899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_int
g_err.967447899
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.314346948
Short name T881
Test name
Test status
Simulation time 566994079 ps
CPU time 1.11 seconds
Started Dec 31 12:43:14 PM PST 23
Finished Dec 31 12:43:16 PM PST 23
Peak memory 200636 kb
Host smart-9a71f278-ac2e-4cf4-a4b9-fc17e3eae7fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314346948 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.314346948
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.4266550914
Short name T891
Test name
Test status
Simulation time 556208341 ps
CPU time 2.09 seconds
Started Dec 31 12:43:11 PM PST 23
Finished Dec 31 12:43:14 PM PST 23
Peak memory 200496 kb
Host smart-54c09093-1539-49bd-b263-481ccbf511e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266550914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.4266550914
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.573752472
Short name T385
Test name
Test status
Simulation time 410894706 ps
CPU time 1.06 seconds
Started Dec 31 12:43:52 PM PST 23
Finished Dec 31 12:44:00 PM PST 23
Peak memory 200248 kb
Host smart-a33bb954-2277-467e-9fed-2a4fd021d3a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573752472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.573752472
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.4101822938
Short name T868
Test name
Test status
Simulation time 2637311436 ps
CPU time 1.69 seconds
Started Dec 31 12:43:18 PM PST 23
Finished Dec 31 12:43:20 PM PST 23
Peak memory 200600 kb
Host smart-01132f50-7de2-4332-97ab-d3c3f51245d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101822938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.4101822938
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.994685114
Short name T408
Test name
Test status
Simulation time 321423206 ps
CPU time 2.89 seconds
Started Dec 31 12:43:23 PM PST 23
Finished Dec 31 12:43:27 PM PST 23
Peak memory 216928 kb
Host smart-87220a7f-79b5-4ff6-9637-f38bbf21a260
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994685114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.994685114
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1326432142
Short name T60
Test name
Test status
Simulation time 8273197896 ps
CPU time 19.56 seconds
Started Dec 31 12:42:55 PM PST 23
Finished Dec 31 12:43:15 PM PST 23
Peak memory 200824 kb
Host smart-b28a0310-f09d-4602-8df3-3ccd4b7cc48b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326432142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.1326432142
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.2305276258
Short name T33
Test name
Test status
Simulation time 493291225 ps
CPU time 1.95 seconds
Started Dec 31 12:43:20 PM PST 23
Finished Dec 31 12:43:23 PM PST 23
Peak memory 200548 kb
Host smart-573027eb-c7e3-4088-878d-560bf8557c1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305276258 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.2305276258
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2246094962
Short name T405
Test name
Test status
Simulation time 525423605 ps
CPU time 1.91 seconds
Started Dec 31 12:43:08 PM PST 23
Finished Dec 31 12:43:10 PM PST 23
Peak memory 200544 kb
Host smart-95b314fd-30dd-43db-a10d-b8b353a3ab41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246094962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.2246094962
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.2386545462
Short name T872
Test name
Test status
Simulation time 493336485 ps
CPU time 0.77 seconds
Started Dec 31 12:43:14 PM PST 23
Finished Dec 31 12:43:16 PM PST 23
Peak memory 200172 kb
Host smart-f92659dd-72b7-42e9-8264-07543731f125
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386545462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.2386545462
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3630489947
Short name T371
Test name
Test status
Simulation time 1786604533 ps
CPU time 3.25 seconds
Started Dec 31 12:43:18 PM PST 23
Finished Dec 31 12:43:22 PM PST 23
Peak memory 200480 kb
Host smart-18699e95-f4e8-4b76-a8bb-f95ce18a4eb7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630489947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.3630489947
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.276666622
Short name T413
Test name
Test status
Simulation time 1017589020 ps
CPU time 1.42 seconds
Started Dec 31 12:43:32 PM PST 23
Finished Dec 31 12:43:35 PM PST 23
Peak memory 200764 kb
Host smart-f107f2ff-310f-4da1-bf74-00c54a15ce80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276666622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.276666622
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2221714708
Short name T35
Test name
Test status
Simulation time 4304144054 ps
CPU time 6.25 seconds
Started Dec 31 12:43:57 PM PST 23
Finished Dec 31 12:44:15 PM PST 23
Peak memory 200856 kb
Host smart-64e621f1-dd82-4b55-8f4c-04c0b05575e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221714708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.2221714708
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1434450723
Short name T42
Test name
Test status
Simulation time 399406778 ps
CPU time 1.14 seconds
Started Dec 31 12:43:26 PM PST 23
Finished Dec 31 12:43:27 PM PST 23
Peak memory 200560 kb
Host smart-112b55db-a4cd-453e-a59c-f90be5d61f58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434450723 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.1434450723
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.4028855288
Short name T8
Test name
Test status
Simulation time 388046772 ps
CPU time 1.72 seconds
Started Dec 31 12:43:07 PM PST 23
Finished Dec 31 12:43:09 PM PST 23
Peak memory 200472 kb
Host smart-94ac6149-50a0-49ab-8faa-10f68e803464
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028855288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.4028855288
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3657808556
Short name T404
Test name
Test status
Simulation time 302882452 ps
CPU time 1.35 seconds
Started Dec 31 12:43:16 PM PST 23
Finished Dec 31 12:43:18 PM PST 23
Peak memory 200408 kb
Host smart-16ecf50f-ef67-4631-9940-2f54bfe78b7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657808556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.3657808556
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2059865636
Short name T375
Test name
Test status
Simulation time 3876911712 ps
CPU time 15.51 seconds
Started Dec 31 12:43:09 PM PST 23
Finished Dec 31 12:43:25 PM PST 23
Peak memory 200772 kb
Host smart-1b3d1f20-1f59-4adc-8f11-7bb3f9e8048a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059865636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.2059865636
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.917015192
Short name T410
Test name
Test status
Simulation time 8542218720 ps
CPU time 13.1 seconds
Started Dec 31 12:43:24 PM PST 23
Finished Dec 31 12:43:38 PM PST 23
Peak memory 200748 kb
Host smart-9cb79946-f83e-4c67-9f0b-82c1a054f96e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917015192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_int
g_err.917015192
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.1362316190
Short name T475
Test name
Test status
Simulation time 440667052 ps
CPU time 1.66 seconds
Started Dec 31 12:31:54 PM PST 23
Finished Dec 31 12:31:57 PM PST 23
Peak memory 200484 kb
Host smart-85e1873c-303f-4078-b8ee-6443f7a67e47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362316190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.1362316190
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.3067121959
Short name T216
Test name
Test status
Simulation time 159816151957 ps
CPU time 56.73 seconds
Started Dec 31 12:31:47 PM PST 23
Finished Dec 31 12:32:45 PM PST 23
Peak memory 200768 kb
Host smart-37b879aa-f0ea-42b0-a8f1-bef78a47b6bf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067121959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.3067121959
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.2421693857
Short name T707
Test name
Test status
Simulation time 484659246772 ps
CPU time 1177.87 seconds
Started Dec 31 12:31:45 PM PST 23
Finished Dec 31 12:51:24 PM PST 23
Peak memory 200792 kb
Host smart-2f9b7dcf-6e06-4c64-b8e0-80ad68f309b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421693857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.2421693857
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.1189544568
Short name T777
Test name
Test status
Simulation time 493701286564 ps
CPU time 1132.64 seconds
Started Dec 31 12:31:50 PM PST 23
Finished Dec 31 12:50:45 PM PST 23
Peak memory 200784 kb
Host smart-ebadf2f8-e727-4959-b90e-304a7ccddce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189544568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.1189544568
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.2562287985
Short name T790
Test name
Test status
Simulation time 159069281109 ps
CPU time 345.02 seconds
Started Dec 31 12:32:07 PM PST 23
Finished Dec 31 12:37:54 PM PST 23
Peak memory 200740 kb
Host smart-278a8a47-7012-44ea-9aeb-32c52e55da33
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562287985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.2562287985
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.3187859875
Short name T225
Test name
Test status
Simulation time 167116461893 ps
CPU time 94.13 seconds
Started Dec 31 12:31:48 PM PST 23
Finished Dec 31 12:33:23 PM PST 23
Peak memory 200708 kb
Host smart-c5027c7f-8b52-4d0b-9718-54e8e95545c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187859875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.3187859875
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.1374068589
Short name T571
Test name
Test status
Simulation time 500976963019 ps
CPU time 292.21 seconds
Started Dec 31 12:32:02 PM PST 23
Finished Dec 31 12:36:56 PM PST 23
Peak memory 200720 kb
Host smart-17ebbff3-dc76-41ae-b599-182cf6e00ade
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374068589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.1374068589
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.1383716021
Short name T301
Test name
Test status
Simulation time 489802783079 ps
CPU time 532.42 seconds
Started Dec 31 12:32:05 PM PST 23
Finished Dec 31 12:40:59 PM PST 23
Peak memory 200692 kb
Host smart-f1021455-3bbc-4f7d-ad64-90a723eba306
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383716021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.1383716021
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.1334852508
Short name T752
Test name
Test status
Simulation time 484607664238 ps
CPU time 262.18 seconds
Started Dec 31 12:32:04 PM PST 23
Finished Dec 31 12:36:27 PM PST 23
Peak memory 200736 kb
Host smart-dc49b4a8-5fa7-4cdb-8f90-5ba9432b940d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334852508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.1334852508
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.3482669627
Short name T432
Test name
Test status
Simulation time 31562745842 ps
CPU time 68.86 seconds
Started Dec 31 12:32:10 PM PST 23
Finished Dec 31 12:33:20 PM PST 23
Peak memory 200536 kb
Host smart-ee649965-77d9-4066-86cc-7bbd51438237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482669627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.3482669627
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.2465927970
Short name T856
Test name
Test status
Simulation time 5227380854 ps
CPU time 11.79 seconds
Started Dec 31 12:32:13 PM PST 23
Finished Dec 31 12:32:27 PM PST 23
Peak memory 200564 kb
Host smart-fb577e57-b7b7-4874-b823-511bc2e57e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465927970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.2465927970
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.2907494397
Short name T52
Test name
Test status
Simulation time 7551592072 ps
CPU time 9.1 seconds
Started Dec 31 12:32:04 PM PST 23
Finished Dec 31 12:32:14 PM PST 23
Peak memory 216788 kb
Host smart-b105c235-8790-497f-ac88-ee0d16dfea59
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907494397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.2907494397
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.3514737745
Short name T431
Test name
Test status
Simulation time 5956524055 ps
CPU time 4.34 seconds
Started Dec 31 12:31:57 PM PST 23
Finished Dec 31 12:32:02 PM PST 23
Peak memory 200632 kb
Host smart-489f3c7c-3d70-4f91-a8b7-3eb03abcf6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514737745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.3514737745
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.1536278054
Short name T333
Test name
Test status
Simulation time 380173477936 ps
CPU time 801.49 seconds
Started Dec 31 12:32:04 PM PST 23
Finished Dec 31 12:45:26 PM PST 23
Peak memory 217468 kb
Host smart-64ddf50c-b19d-48dc-ba17-e3fd86388192
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536278054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
1536278054
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.912290213
Short name T644
Test name
Test status
Simulation time 61862533042 ps
CPU time 154.73 seconds
Started Dec 31 12:32:05 PM PST 23
Finished Dec 31 12:34:41 PM PST 23
Peak memory 200896 kb
Host smart-fe589dbc-94d4-4def-b07d-a24d8fb82b58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912290213 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.912290213
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.3810531348
Short name T609
Test name
Test status
Simulation time 309345768 ps
CPU time 1.11 seconds
Started Dec 31 12:32:54 PM PST 23
Finished Dec 31 12:32:57 PM PST 23
Peak memory 200504 kb
Host smart-5c4ff023-9004-4fd3-9fb4-93bb81c42be2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810531348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.3810531348
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.12082355
Short name T687
Test name
Test status
Simulation time 168160031245 ps
CPU time 400.52 seconds
Started Dec 31 12:33:08 PM PST 23
Finished Dec 31 12:39:51 PM PST 23
Peak memory 200808 kb
Host smart-a988c6b9-da3a-4cc2-94dd-d9ef972a73fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12082355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.12082355
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.2492724779
Short name T205
Test name
Test status
Simulation time 163622289241 ps
CPU time 378.89 seconds
Started Dec 31 12:31:35 PM PST 23
Finished Dec 31 12:37:57 PM PST 23
Peak memory 200680 kb
Host smart-18bb8576-9588-4eea-bef0-374059907c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492724779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.2492724779
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.1897562457
Short name T566
Test name
Test status
Simulation time 501042202108 ps
CPU time 1244.38 seconds
Started Dec 31 12:32:07 PM PST 23
Finished Dec 31 12:52:53 PM PST 23
Peak memory 200780 kb
Host smart-cd2a48c7-7f4a-4864-9d28-13c920dcbefc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897562457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.1897562457
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.3719352184
Short name T129
Test name
Test status
Simulation time 328974101348 ps
CPU time 185.6 seconds
Started Dec 31 12:31:59 PM PST 23
Finished Dec 31 12:35:06 PM PST 23
Peak memory 200700 kb
Host smart-d442c16e-6a30-4b63-9fc0-33ce9dca7023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719352184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.3719352184
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.2823695545
Short name T126
Test name
Test status
Simulation time 331726687771 ps
CPU time 116.49 seconds
Started Dec 31 12:31:57 PM PST 23
Finished Dec 31 12:33:55 PM PST 23
Peak memory 200736 kb
Host smart-6af8ef69-2545-4037-8e83-45312735480b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823695545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.2823695545
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.597646485
Short name T83
Test name
Test status
Simulation time 326721609110 ps
CPU time 673.35 seconds
Started Dec 31 12:31:31 PM PST 23
Finished Dec 31 12:42:51 PM PST 23
Peak memory 200680 kb
Host smart-7ff2f5e0-6bbe-4fb1-b4db-610562d413ef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597646485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_w
akeup.597646485
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.1801956584
Short name T520
Test name
Test status
Simulation time 76388051189 ps
CPU time 294.32 seconds
Started Dec 31 12:32:23 PM PST 23
Finished Dec 31 12:37:21 PM PST 23
Peak memory 201172 kb
Host smart-ac6c1fca-6166-4052-81cf-253cddbe375f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801956584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.1801956584
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.173921037
Short name T622
Test name
Test status
Simulation time 46169794843 ps
CPU time 53.41 seconds
Started Dec 31 12:31:56 PM PST 23
Finished Dec 31 12:32:50 PM PST 23
Peak memory 200576 kb
Host smart-2c718c08-3dc4-4fca-951a-a7603b335a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173921037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.173921037
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.1019526017
Short name T667
Test name
Test status
Simulation time 4411087423 ps
CPU time 3.07 seconds
Started Dec 31 12:32:29 PM PST 23
Finished Dec 31 12:32:35 PM PST 23
Peak memory 200536 kb
Host smart-dbfed058-984e-421a-8c72-5ae6e170de27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019526017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.1019526017
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.3243544624
Short name T55
Test name
Test status
Simulation time 7866998230 ps
CPU time 17.65 seconds
Started Dec 31 12:32:30 PM PST 23
Finished Dec 31 12:32:50 PM PST 23
Peak memory 215932 kb
Host smart-d0aa8d84-6037-4cf7-8ef5-bb57d9895b09
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243544624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.3243544624
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.3654667810
Short name T562
Test name
Test status
Simulation time 5497548918 ps
CPU time 3.95 seconds
Started Dec 31 12:32:00 PM PST 23
Finished Dec 31 12:32:05 PM PST 23
Peak memory 200512 kb
Host smart-fc14b550-4f3d-4bdd-ac84-46357f4f6f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654667810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.3654667810
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.2313733221
Short name T159
Test name
Test status
Simulation time 9651852021 ps
CPU time 10.98 seconds
Started Dec 31 12:32:04 PM PST 23
Finished Dec 31 12:32:24 PM PST 23
Peak memory 200572 kb
Host smart-5bb2c490-2c8b-48b2-88c2-aa5ccc92ba65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313733221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
2313733221
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.3364489164
Short name T305
Test name
Test status
Simulation time 31955535604 ps
CPU time 71.79 seconds
Started Dec 31 12:32:02 PM PST 23
Finished Dec 31 12:33:15 PM PST 23
Peak memory 209404 kb
Host smart-a1beba99-5fee-4dde-8a9e-a1f6ff01a3cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364489164 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.3364489164
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.3788443127
Short name T463
Test name
Test status
Simulation time 319250460 ps
CPU time 0.81 seconds
Started Dec 31 12:32:13 PM PST 23
Finished Dec 31 12:32:15 PM PST 23
Peak memory 200528 kb
Host smart-608be869-3f4f-4c20-b411-9f6dce94c380
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788443127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.3788443127
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.3794021064
Short name T564
Test name
Test status
Simulation time 159375578330 ps
CPU time 97.97 seconds
Started Dec 31 12:32:16 PM PST 23
Finished Dec 31 12:33:56 PM PST 23
Peak memory 200724 kb
Host smart-82ae78a1-7170-4135-ba6c-533fb3b61b92
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794021064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.3794021064
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.886013118
Short name T262
Test name
Test status
Simulation time 325877054338 ps
CPU time 186.74 seconds
Started Dec 31 12:32:16 PM PST 23
Finished Dec 31 12:35:25 PM PST 23
Peak memory 200696 kb
Host smart-fe4048eb-eac1-46ea-b002-5ce3b5d13465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886013118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.886013118
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.2812830506
Short name T493
Test name
Test status
Simulation time 161634899866 ps
CPU time 191.45 seconds
Started Dec 31 12:32:30 PM PST 23
Finished Dec 31 12:35:44 PM PST 23
Peak memory 200664 kb
Host smart-52ac5218-3e4e-466e-9539-48304ba3c64f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812830506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.2812830506
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.2683358281
Short name T771
Test name
Test status
Simulation time 168185502616 ps
CPU time 106.84 seconds
Started Dec 31 12:32:14 PM PST 23
Finished Dec 31 12:34:02 PM PST 23
Peak memory 200704 kb
Host smart-12a4794d-2446-4285-9b70-cf87a5f11aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683358281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.2683358281
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.3282207926
Short name T759
Test name
Test status
Simulation time 154206722208 ps
CPU time 352.85 seconds
Started Dec 31 12:32:03 PM PST 23
Finished Dec 31 12:37:57 PM PST 23
Peak memory 200672 kb
Host smart-3f36f777-0905-411f-b1d2-c144f7d69876
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282207926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.3282207926
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.943104620
Short name T603
Test name
Test status
Simulation time 166376942901 ps
CPU time 387.58 seconds
Started Dec 31 12:32:05 PM PST 23
Finished Dec 31 12:38:34 PM PST 23
Peak memory 200712 kb
Host smart-d7546ae5-d390-4baa-b3c2-dfd5abb9c2d3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943104620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
adc_ctrl_filters_wakeup_fixed.943104620
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.661727723
Short name T349
Test name
Test status
Simulation time 134113245241 ps
CPU time 697.19 seconds
Started Dec 31 12:32:13 PM PST 23
Finished Dec 31 12:43:52 PM PST 23
Peak memory 201180 kb
Host smart-f8582857-f602-46a6-be93-c8594da24864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661727723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.661727723
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.1335375626
Short name T113
Test name
Test status
Simulation time 27105176979 ps
CPU time 34.32 seconds
Started Dec 31 12:32:11 PM PST 23
Finished Dec 31 12:32:46 PM PST 23
Peak memory 200504 kb
Host smart-99353200-90fc-4583-a9ad-121f5ef085ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335375626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.1335375626
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.795727582
Short name T544
Test name
Test status
Simulation time 5368868265 ps
CPU time 8.77 seconds
Started Dec 31 12:32:06 PM PST 23
Finished Dec 31 12:32:16 PM PST 23
Peak memory 200560 kb
Host smart-9f9f3154-bcf4-4cbd-9a1a-3d9f870f3d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795727582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.795727582
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.1250555890
Short name T780
Test name
Test status
Simulation time 5976569341 ps
CPU time 14.09 seconds
Started Dec 31 12:32:30 PM PST 23
Finished Dec 31 12:32:47 PM PST 23
Peak memory 200604 kb
Host smart-3de43f47-c550-4722-afdc-2b1e17a4cbb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250555890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.1250555890
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.3062917241
Short name T261
Test name
Test status
Simulation time 659231542183 ps
CPU time 880.39 seconds
Started Dec 31 12:32:13 PM PST 23
Finished Dec 31 12:46:55 PM PST 23
Peak memory 201016 kb
Host smart-ee22d5e4-791e-437f-a273-5114b357956f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062917241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.3062917241
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.1096792193
Short name T465
Test name
Test status
Simulation time 60446608100 ps
CPU time 52.84 seconds
Started Dec 31 12:32:29 PM PST 23
Finished Dec 31 12:33:25 PM PST 23
Peak memory 200776 kb
Host smart-fafab7b8-2924-46f8-aee9-b7015f5a7fdc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096792193 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.1096792193
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.2993830012
Short name T156
Test name
Test status
Simulation time 328117106514 ps
CPU time 104.94 seconds
Started Dec 31 12:32:14 PM PST 23
Finished Dec 31 12:34:00 PM PST 23
Peak memory 200712 kb
Host smart-15d0b0ed-fb79-47da-ac35-b0475637747f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993830012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.2993830012
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.757979886
Short name T227
Test name
Test status
Simulation time 492384449737 ps
CPU time 309.13 seconds
Started Dec 31 12:32:24 PM PST 23
Finished Dec 31 12:37:37 PM PST 23
Peak memory 200616 kb
Host smart-86a7b4a4-ebcc-41f1-8e4d-6d1963561257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757979886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.757979886
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.3602394491
Short name T620
Test name
Test status
Simulation time 330820759386 ps
CPU time 224.6 seconds
Started Dec 31 12:32:08 PM PST 23
Finished Dec 31 12:35:53 PM PST 23
Peak memory 200772 kb
Host smart-a109f5d6-2ab8-4fe4-b304-4ce78a11e759
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602394491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.3602394491
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.543151181
Short name T802
Test name
Test status
Simulation time 491794920924 ps
CPU time 296.33 seconds
Started Dec 31 12:31:59 PM PST 23
Finished Dec 31 12:36:56 PM PST 23
Peak memory 200684 kb
Host smart-0a0d94f2-01df-44c3-b27c-030993ad2f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543151181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.543151181
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.802157586
Short name T171
Test name
Test status
Simulation time 164467818474 ps
CPU time 195.52 seconds
Started Dec 31 12:32:09 PM PST 23
Finished Dec 31 12:35:25 PM PST 23
Peak memory 200708 kb
Host smart-513d45c5-ae83-497f-97c6-a0d1166f4a24
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=802157586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fixe
d.802157586
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.1244663695
Short name T128
Test name
Test status
Simulation time 329603049467 ps
CPU time 756.29 seconds
Started Dec 31 12:32:27 PM PST 23
Finished Dec 31 12:45:06 PM PST 23
Peak memory 200728 kb
Host smart-316ec88a-a42f-44d9-9ce7-c3c8b8bcf812
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244663695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.1244663695
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.3241076499
Short name T705
Test name
Test status
Simulation time 330466966443 ps
CPU time 174.25 seconds
Started Dec 31 12:32:37 PM PST 23
Finished Dec 31 12:35:33 PM PST 23
Peak memory 200672 kb
Host smart-463a9e9d-5735-48c1-84a1-0f7f953cb653
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241076499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.3241076499
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.3745703099
Short name T662
Test name
Test status
Simulation time 121280277525 ps
CPU time 621.08 seconds
Started Dec 31 12:32:28 PM PST 23
Finished Dec 31 12:42:53 PM PST 23
Peak memory 201072 kb
Host smart-3e42e960-df11-4341-8884-4a8e2b27cec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745703099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.3745703099
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.2094108363
Short name T706
Test name
Test status
Simulation time 31879831031 ps
CPU time 17.93 seconds
Started Dec 31 12:32:24 PM PST 23
Finished Dec 31 12:32:45 PM PST 23
Peak memory 200532 kb
Host smart-4c8196b4-4936-40e1-9bed-41466d4c1c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094108363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.2094108363
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.1999907025
Short name T142
Test name
Test status
Simulation time 4887190984 ps
CPU time 3.55 seconds
Started Dec 31 12:32:29 PM PST 23
Finished Dec 31 12:32:36 PM PST 23
Peak memory 200524 kb
Host smart-16f0ce40-3827-4d56-a30d-3d11497369ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999907025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.1999907025
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.880033411
Short name T445
Test name
Test status
Simulation time 5601912908 ps
CPU time 13.66 seconds
Started Dec 31 12:32:03 PM PST 23
Finished Dec 31 12:32:17 PM PST 23
Peak memory 200512 kb
Host smart-7a4af0e3-4ef3-4dd0-ad1d-46ae49c85d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880033411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.880033411
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.1044004451
Short name T522
Test name
Test status
Simulation time 38809463558 ps
CPU time 123.77 seconds
Started Dec 31 12:32:16 PM PST 23
Finished Dec 31 12:34:22 PM PST 23
Peak memory 209348 kb
Host smart-aac3db5e-322d-4139-895a-def980806016
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044004451 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.1044004451
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.2641485620
Short name T436
Test name
Test status
Simulation time 454675207 ps
CPU time 1.46 seconds
Started Dec 31 12:32:19 PM PST 23
Finished Dec 31 12:32:22 PM PST 23
Peak memory 200532 kb
Host smart-df0ee0c2-ca0f-4faf-bbef-73a11e43226d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641485620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.2641485620
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.860377748
Short name T319
Test name
Test status
Simulation time 166233490148 ps
CPU time 208.34 seconds
Started Dec 31 12:32:09 PM PST 23
Finished Dec 31 12:35:38 PM PST 23
Peak memory 200804 kb
Host smart-23ac1537-b48a-4e85-adc9-7fd0133cf5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860377748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.860377748
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.2104390836
Short name T747
Test name
Test status
Simulation time 160643981043 ps
CPU time 340.78 seconds
Started Dec 31 12:32:29 PM PST 23
Finished Dec 31 12:38:13 PM PST 23
Peak memory 200740 kb
Host smart-774d9567-356b-47d8-91bb-d70caebfc25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104390836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.2104390836
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.3119378716
Short name T496
Test name
Test status
Simulation time 169816391668 ps
CPU time 147.37 seconds
Started Dec 31 12:32:22 PM PST 23
Finished Dec 31 12:34:54 PM PST 23
Peak memory 200784 kb
Host smart-7c52b9ff-6c47-40dc-94e8-7e6a208cc577
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119378716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.3119378716
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.2436620484
Short name T306
Test name
Test status
Simulation time 332254603372 ps
CPU time 729.26 seconds
Started Dec 31 12:32:03 PM PST 23
Finished Dec 31 12:44:14 PM PST 23
Peak memory 200692 kb
Host smart-6e30987b-a704-4e3c-87e1-e02a313d84b7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436620484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.2436620484
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.2730806064
Short name T92
Test name
Test status
Simulation time 166422293603 ps
CPU time 52.11 seconds
Started Dec 31 12:32:35 PM PST 23
Finished Dec 31 12:33:29 PM PST 23
Peak memory 200700 kb
Host smart-2787f0c0-d937-44ea-a2bd-65481352a5ce
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730806064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.2730806064
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.2850596140
Short name T350
Test name
Test status
Simulation time 98808209205 ps
CPU time 328 seconds
Started Dec 31 12:32:13 PM PST 23
Finished Dec 31 12:37:43 PM PST 23
Peak memory 201132 kb
Host smart-b0c5b327-3d92-4e38-b05e-c276ba4ed661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850596140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.2850596140
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.1195129602
Short name T587
Test name
Test status
Simulation time 35999093439 ps
CPU time 86.21 seconds
Started Dec 31 12:32:07 PM PST 23
Finished Dec 31 12:33:35 PM PST 23
Peak memory 200528 kb
Host smart-9075dccd-cc9c-4bc7-92bb-e2850ed4ae8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195129602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.1195129602
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.2330107544
Short name T427
Test name
Test status
Simulation time 4287963277 ps
CPU time 3.29 seconds
Started Dec 31 12:32:12 PM PST 23
Finished Dec 31 12:32:17 PM PST 23
Peak memory 200584 kb
Host smart-99978bdc-1ec2-45dc-94fd-3930375473ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330107544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.2330107544
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.2447817222
Short name T634
Test name
Test status
Simulation time 6194638925 ps
CPU time 4.33 seconds
Started Dec 31 12:32:27 PM PST 23
Finished Dec 31 12:32:34 PM PST 23
Peak memory 200548 kb
Host smart-43db27df-c930-4a06-9ad5-f57dcd8f310e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447817222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.2447817222
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.2932042003
Short name T339
Test name
Test status
Simulation time 163345667608 ps
CPU time 172.29 seconds
Started Dec 31 12:32:14 PM PST 23
Finished Dec 31 12:35:08 PM PST 23
Peak memory 216784 kb
Host smart-59bb4b32-1b74-4101-88c4-be46185276fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932042003 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.2932042003
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.1877669072
Short name T753
Test name
Test status
Simulation time 348034165 ps
CPU time 1.42 seconds
Started Dec 31 12:32:26 PM PST 23
Finished Dec 31 12:32:29 PM PST 23
Peak memory 200512 kb
Host smart-3619348e-133b-4845-a877-554b576f31cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877669072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.1877669072
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.2496234515
Short name T163
Test name
Test status
Simulation time 328930369200 ps
CPU time 116.06 seconds
Started Dec 31 12:32:16 PM PST 23
Finished Dec 31 12:34:14 PM PST 23
Peak memory 200744 kb
Host smart-399868bf-ab39-4307-8d06-582af33e9835
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496234515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.2496234515
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.3727024904
Short name T213
Test name
Test status
Simulation time 162360070210 ps
CPU time 388.28 seconds
Started Dec 31 12:32:16 PM PST 23
Finished Dec 31 12:38:46 PM PST 23
Peak memory 200792 kb
Host smart-e591b04a-13ef-4d00-be8a-74db8aaba629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727024904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.3727024904
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.3910606274
Short name T428
Test name
Test status
Simulation time 166007827273 ps
CPU time 371.41 seconds
Started Dec 31 12:32:35 PM PST 23
Finished Dec 31 12:38:48 PM PST 23
Peak memory 200692 kb
Host smart-48204ac6-1512-43a7-a9aa-80e7de93935b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910606274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.3910606274
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.2467581774
Short name T672
Test name
Test status
Simulation time 165549359225 ps
CPU time 360.18 seconds
Started Dec 31 12:32:10 PM PST 23
Finished Dec 31 12:38:12 PM PST 23
Peak memory 200756 kb
Host smart-b3d34511-dde8-4b7f-8008-244901adc03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467581774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.2467581774
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.75432971
Short name T472
Test name
Test status
Simulation time 329806081221 ps
CPU time 187.43 seconds
Started Dec 31 12:32:13 PM PST 23
Finished Dec 31 12:35:22 PM PST 23
Peak memory 200696 kb
Host smart-ec942688-9d4d-4857-8d29-c0bab912fcc7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=75432971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fixed
.75432971
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.498223516
Short name T853
Test name
Test status
Simulation time 506737491758 ps
CPU time 279.65 seconds
Started Dec 31 12:32:49 PM PST 23
Finished Dec 31 12:37:30 PM PST 23
Peak memory 200796 kb
Host smart-ec52b5e1-c1de-4435-856c-80b683cbbefb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498223516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_
wakeup.498223516
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.3516160754
Short name T558
Test name
Test status
Simulation time 494371034961 ps
CPU time 1227.97 seconds
Started Dec 31 12:32:20 PM PST 23
Finished Dec 31 12:52:54 PM PST 23
Peak memory 200716 kb
Host smart-74cf13dc-7186-43ef-b33c-4cd24a538151
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516160754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.3516160754
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.2111033991
Short name T845
Test name
Test status
Simulation time 115086260128 ps
CPU time 642.08 seconds
Started Dec 31 12:32:11 PM PST 23
Finished Dec 31 12:42:54 PM PST 23
Peak memory 201104 kb
Host smart-639a6d80-891a-4ba6-ba32-203158a5d783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111033991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.2111033991
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.4031410679
Short name T500
Test name
Test status
Simulation time 28911581727 ps
CPU time 62.95 seconds
Started Dec 31 12:32:24 PM PST 23
Finished Dec 31 12:33:30 PM PST 23
Peak memory 200592 kb
Host smart-a93c8aaf-601a-4c68-bba2-54de24d58f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031410679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.4031410679
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.4170616743
Short name T624
Test name
Test status
Simulation time 2823719917 ps
CPU time 6.65 seconds
Started Dec 31 12:32:08 PM PST 23
Finished Dec 31 12:32:16 PM PST 23
Peak memory 200592 kb
Host smart-e0c2184e-8821-4a63-b238-b11cb49df240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170616743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.4170616743
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.3372836425
Short name T444
Test name
Test status
Simulation time 5762690411 ps
CPU time 14.14 seconds
Started Dec 31 12:32:21 PM PST 23
Finished Dec 31 12:32:41 PM PST 23
Peak memory 200504 kb
Host smart-d74bebf7-4350-4543-88a3-abf75415331e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372836425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.3372836425
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.3819405051
Short name T629
Test name
Test status
Simulation time 338307704 ps
CPU time 0.79 seconds
Started Dec 31 12:32:42 PM PST 23
Finished Dec 31 12:32:44 PM PST 23
Peak memory 200488 kb
Host smart-7d36d1e8-25fa-43b1-a7a4-90b76d33405f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819405051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.3819405051
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.3909761697
Short name T787
Test name
Test status
Simulation time 163189515116 ps
CPU time 15.8 seconds
Started Dec 31 12:32:17 PM PST 23
Finished Dec 31 12:32:36 PM PST 23
Peak memory 200716 kb
Host smart-14f11f9f-e180-42d2-a0c4-8fb30154118e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909761697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.3909761697
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.2530019283
Short name T322
Test name
Test status
Simulation time 335126626092 ps
CPU time 405.75 seconds
Started Dec 31 12:32:11 PM PST 23
Finished Dec 31 12:38:57 PM PST 23
Peak memory 200780 kb
Host smart-db872848-685d-4683-8c13-18b8eab81e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530019283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.2530019283
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.4244112717
Short name T604
Test name
Test status
Simulation time 161313138220 ps
CPU time 202.23 seconds
Started Dec 31 12:32:28 PM PST 23
Finished Dec 31 12:35:54 PM PST 23
Peak memory 200808 kb
Host smart-bf2c33e5-4e24-4f59-800f-194aa61d8512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244112717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.4244112717
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.2835892113
Short name T731
Test name
Test status
Simulation time 330614293229 ps
CPU time 743.63 seconds
Started Dec 31 12:32:18 PM PST 23
Finished Dec 31 12:44:44 PM PST 23
Peak memory 200756 kb
Host smart-755d9830-439f-4a27-81b2-7e1d34a3e0f6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835892113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.2835892113
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.2057910907
Short name T750
Test name
Test status
Simulation time 327319213383 ps
CPU time 159.08 seconds
Started Dec 31 12:32:14 PM PST 23
Finished Dec 31 12:34:55 PM PST 23
Peak memory 200732 kb
Host smart-f375a0d2-80ee-4ffd-933c-8bd639970788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057910907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.2057910907
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.4157881373
Short name T149
Test name
Test status
Simulation time 495603997007 ps
CPU time 365.73 seconds
Started Dec 31 12:32:14 PM PST 23
Finished Dec 31 12:38:22 PM PST 23
Peak memory 200664 kb
Host smart-0f440c28-feb8-4643-a1f4-d3c1fe31f170
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157881373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.4157881373
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.2453416265
Short name T219
Test name
Test status
Simulation time 341026479707 ps
CPU time 816.87 seconds
Started Dec 31 12:32:29 PM PST 23
Finished Dec 31 12:46:09 PM PST 23
Peak memory 200676 kb
Host smart-cc38b901-a4fc-4db6-a854-c05717b2440f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453416265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.2453416265
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.1944211098
Short name T860
Test name
Test status
Simulation time 163061223989 ps
CPU time 389.02 seconds
Started Dec 31 12:32:28 PM PST 23
Finished Dec 31 12:39:01 PM PST 23
Peak memory 200808 kb
Host smart-0adfd732-76f0-4763-9eac-78c031749d62
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944211098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.1944211098
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.3772934856
Short name T864
Test name
Test status
Simulation time 125027738932 ps
CPU time 710.1 seconds
Started Dec 31 12:32:28 PM PST 23
Finished Dec 31 12:44:22 PM PST 23
Peak memory 201200 kb
Host smart-21843385-7f65-46ef-bc48-d86a6f152236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772934856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.3772934856
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.2956820715
Short name T718
Test name
Test status
Simulation time 41083942623 ps
CPU time 57.86 seconds
Started Dec 31 12:32:41 PM PST 23
Finished Dec 31 12:33:40 PM PST 23
Peak memory 200496 kb
Host smart-87e45ed9-a4af-457a-acc4-4e0b324a4f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956820715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.2956820715
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.1171205346
Short name T774
Test name
Test status
Simulation time 3181359638 ps
CPU time 1.88 seconds
Started Dec 31 12:32:12 PM PST 23
Finished Dec 31 12:32:15 PM PST 23
Peak memory 200584 kb
Host smart-06e80567-6fd0-4818-9d57-e5ee620b5ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171205346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.1171205346
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.3772232016
Short name T825
Test name
Test status
Simulation time 5962906852 ps
CPU time 5.29 seconds
Started Dec 31 12:32:14 PM PST 23
Finished Dec 31 12:32:21 PM PST 23
Peak memory 200572 kb
Host smart-dfa38e5b-6f46-43da-95ef-fed6f69e0a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772232016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.3772232016
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.2709226882
Short name T108
Test name
Test status
Simulation time 215498124782 ps
CPU time 531.02 seconds
Started Dec 31 12:32:22 PM PST 23
Finished Dec 31 12:41:18 PM PST 23
Peak memory 200716 kb
Host smart-9dc09247-e8d4-459a-923d-20d667c34380
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709226882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.2709226882
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.1325333514
Short name T502
Test name
Test status
Simulation time 493557232 ps
CPU time 1.72 seconds
Started Dec 31 12:32:13 PM PST 23
Finished Dec 31 12:32:16 PM PST 23
Peak memory 200472 kb
Host smart-6948a8cb-8893-4430-9b2c-3ffaaf5347b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325333514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.1325333514
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.1345665328
Short name T269
Test name
Test status
Simulation time 334824756163 ps
CPU time 776.83 seconds
Started Dec 31 12:32:10 PM PST 23
Finished Dec 31 12:45:07 PM PST 23
Peak memory 200812 kb
Host smart-7881376b-4877-406c-9243-a648d1434ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345665328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.1345665328
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.3824202707
Short name T799
Test name
Test status
Simulation time 497120136040 ps
CPU time 277.02 seconds
Started Dec 31 12:32:23 PM PST 23
Finished Dec 31 12:37:04 PM PST 23
Peak memory 200672 kb
Host smart-feff073c-8d4b-4c3b-920b-0329d7bb7758
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824202707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.3824202707
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.3588066722
Short name T317
Test name
Test status
Simulation time 501696554721 ps
CPU time 273.75 seconds
Started Dec 31 12:32:28 PM PST 23
Finished Dec 31 12:37:05 PM PST 23
Peak memory 200712 kb
Host smart-93361374-5027-4bd2-8d56-86d833d83e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588066722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.3588066722
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.853933885
Short name T815
Test name
Test status
Simulation time 491478815643 ps
CPU time 1056.17 seconds
Started Dec 31 12:32:48 PM PST 23
Finished Dec 31 12:50:26 PM PST 23
Peak memory 200744 kb
Host smart-71cfc49f-ab18-44d5-a5ff-0a06dff37014
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=853933885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fixe
d.853933885
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.1303676102
Short name T518
Test name
Test status
Simulation time 325591969166 ps
CPU time 722.91 seconds
Started Dec 31 12:32:09 PM PST 23
Finished Dec 31 12:44:14 PM PST 23
Peak memory 200652 kb
Host smart-68809fca-5970-49cb-8620-910f4f4eae11
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303676102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.1303676102
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.535603553
Short name T512
Test name
Test status
Simulation time 89667113011 ps
CPU time 309.01 seconds
Started Dec 31 12:32:48 PM PST 23
Finished Dec 31 12:37:59 PM PST 23
Peak memory 201156 kb
Host smart-78389a13-29cb-4d1d-9554-2cdb26d7ce60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535603553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.535603553
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.3513024863
Short name T694
Test name
Test status
Simulation time 37666325203 ps
CPU time 21.42 seconds
Started Dec 31 12:32:13 PM PST 23
Finished Dec 31 12:32:36 PM PST 23
Peak memory 200596 kb
Host smart-9f675641-fcae-4231-82a2-cf89eb1b72cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513024863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.3513024863
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.931236962
Short name T569
Test name
Test status
Simulation time 4527186088 ps
CPU time 10.56 seconds
Started Dec 31 12:32:53 PM PST 23
Finished Dec 31 12:33:04 PM PST 23
Peak memory 200564 kb
Host smart-29d725ba-bf80-4d52-bac4-02768abe21a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931236962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.931236962
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.3563682257
Short name T746
Test name
Test status
Simulation time 5731135674 ps
CPU time 2.36 seconds
Started Dec 31 12:32:43 PM PST 23
Finished Dec 31 12:32:47 PM PST 23
Peak memory 200524 kb
Host smart-5e9691ef-0d0c-44d2-b235-3da7a155d0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563682257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.3563682257
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.1152336941
Short name T547
Test name
Test status
Simulation time 31471669333 ps
CPU time 73.08 seconds
Started Dec 31 12:32:12 PM PST 23
Finished Dec 31 12:33:26 PM PST 23
Peak memory 209556 kb
Host smart-ffeea051-61ad-4352-8943-bc3980cc7bc6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152336941 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.1152336941
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.870615557
Short name T443
Test name
Test status
Simulation time 430584124 ps
CPU time 0.86 seconds
Started Dec 31 12:32:42 PM PST 23
Finished Dec 31 12:32:44 PM PST 23
Peak memory 200476 kb
Host smart-5fda6aa8-3650-413c-ae17-1620218a11f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870615557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.870615557
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.135445226
Short name T579
Test name
Test status
Simulation time 173747345803 ps
CPU time 181.47 seconds
Started Dec 31 12:32:37 PM PST 23
Finished Dec 31 12:35:40 PM PST 23
Peak memory 200804 kb
Host smart-52b3041c-fec4-4fe7-80a7-2803cd5e9995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135445226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.135445226
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.571838900
Short name T599
Test name
Test status
Simulation time 335321526962 ps
CPU time 409.45 seconds
Started Dec 31 12:32:19 PM PST 23
Finished Dec 31 12:39:10 PM PST 23
Peak memory 200744 kb
Host smart-b9445c08-52d0-444d-9780-694ed69d18ef
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=571838900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrup
t_fixed.571838900
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.2205131641
Short name T307
Test name
Test status
Simulation time 490176121950 ps
CPU time 78.11 seconds
Started Dec 31 12:32:47 PM PST 23
Finished Dec 31 12:34:07 PM PST 23
Peak memory 200752 kb
Host smart-f84bde06-f352-4538-a1e3-d11a4715a95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205131641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.2205131641
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.3268034763
Short name T563
Test name
Test status
Simulation time 501162462740 ps
CPU time 1059.45 seconds
Started Dec 31 12:32:36 PM PST 23
Finished Dec 31 12:50:16 PM PST 23
Peak memory 200740 kb
Host smart-8fe29a1f-f316-4f85-89b9-c62d58a6e2bb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268034763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.3268034763
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.3717189588
Short name T655
Test name
Test status
Simulation time 499533656833 ps
CPU time 264.48 seconds
Started Dec 31 12:32:16 PM PST 23
Finished Dec 31 12:36:43 PM PST 23
Peak memory 200724 kb
Host smart-12b7cef9-bfcc-4440-a148-b318d3170e6a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717189588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.3717189588
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.932711601
Short name T658
Test name
Test status
Simulation time 115444712222 ps
CPU time 405.08 seconds
Started Dec 31 12:32:23 PM PST 23
Finished Dec 31 12:39:12 PM PST 23
Peak memory 201244 kb
Host smart-2aaae80f-0302-49fe-8260-732a222da06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932711601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.932711601
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.2836186654
Short name T550
Test name
Test status
Simulation time 39502873926 ps
CPU time 26.76 seconds
Started Dec 31 12:32:16 PM PST 23
Finished Dec 31 12:32:44 PM PST 23
Peak memory 200560 kb
Host smart-9249119b-6230-4f0a-9d58-e00b7d9e9901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836186654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.2836186654
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.2566840009
Short name T836
Test name
Test status
Simulation time 5013049339 ps
CPU time 3.51 seconds
Started Dec 31 12:32:14 PM PST 23
Finished Dec 31 12:32:19 PM PST 23
Peak memory 200556 kb
Host smart-c61a75fa-a697-4556-83a3-12c36696a512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566840009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.2566840009
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.3625673600
Short name T659
Test name
Test status
Simulation time 5596307052 ps
CPU time 13.9 seconds
Started Dec 31 12:32:18 PM PST 23
Finished Dec 31 12:32:34 PM PST 23
Peak memory 200580 kb
Host smart-d7931390-4f01-4089-8b91-9da7e60a5e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625673600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.3625673600
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.1221976199
Short name T155
Test name
Test status
Simulation time 163253138848 ps
CPU time 166.66 seconds
Started Dec 31 12:32:27 PM PST 23
Finished Dec 31 12:35:17 PM PST 23
Peak memory 200752 kb
Host smart-5f366963-854d-4f26-b680-79e2638a33f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221976199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.1221976199
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.3824594058
Short name T453
Test name
Test status
Simulation time 324500981 ps
CPU time 0.81 seconds
Started Dec 31 12:32:45 PM PST 23
Finished Dec 31 12:32:48 PM PST 23
Peak memory 200456 kb
Host smart-750fca4f-d814-49e6-8672-491435bec2b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824594058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.3824594058
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.1809973696
Short name T41
Test name
Test status
Simulation time 332388981439 ps
CPU time 697.21 seconds
Started Dec 31 12:32:38 PM PST 23
Finished Dec 31 12:44:16 PM PST 23
Peak memory 200752 kb
Host smart-a8e57548-976a-42ae-beea-e31e6cbb0dc7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809973696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.1809973696
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.1062795200
Short name T703
Test name
Test status
Simulation time 332429010203 ps
CPU time 803.77 seconds
Started Dec 31 12:32:13 PM PST 23
Finished Dec 31 12:45:38 PM PST 23
Peak memory 200768 kb
Host smart-a9066bdf-c215-4d64-8569-eec4e85a06e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062795200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.1062795200
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.1817528705
Short name T783
Test name
Test status
Simulation time 327669730261 ps
CPU time 203.16 seconds
Started Dec 31 12:32:27 PM PST 23
Finished Dec 31 12:35:53 PM PST 23
Peak memory 200868 kb
Host smart-d5baa501-ea3a-4f5b-b7a6-ac4c3e35322b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817528705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.1817528705
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.2042106571
Short name T469
Test name
Test status
Simulation time 486311291612 ps
CPU time 626 seconds
Started Dec 31 12:33:02 PM PST 23
Finished Dec 31 12:43:29 PM PST 23
Peak memory 200652 kb
Host smart-d84bafcb-a376-4578-8e4b-a29d55ec4ee5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042106571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.2042106571
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.1587321697
Short name T131
Test name
Test status
Simulation time 489617548238 ps
CPU time 325.47 seconds
Started Dec 31 12:32:43 PM PST 23
Finished Dec 31 12:38:15 PM PST 23
Peak memory 200736 kb
Host smart-2b1518fc-9508-4ae7-8757-70eb33a5e2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587321697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.1587321697
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.879996127
Short name T510
Test name
Test status
Simulation time 329142751818 ps
CPU time 713.54 seconds
Started Dec 31 12:32:40 PM PST 23
Finished Dec 31 12:44:34 PM PST 23
Peak memory 200744 kb
Host smart-f38914bb-9db8-4af6-94a1-038f532dede2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=879996127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fixe
d.879996127
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.2876721866
Short name T668
Test name
Test status
Simulation time 500963351278 ps
CPU time 1147.47 seconds
Started Dec 31 12:32:27 PM PST 23
Finished Dec 31 12:51:38 PM PST 23
Peak memory 200812 kb
Host smart-c4dec0a6-0558-43f8-a256-7faf00380ec4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876721866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.2876721866
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.137637734
Short name T165
Test name
Test status
Simulation time 336887199588 ps
CPU time 245.96 seconds
Started Dec 31 12:32:29 PM PST 23
Finished Dec 31 12:36:38 PM PST 23
Peak memory 200708 kb
Host smart-9a9e6809-addc-4195-97b8-64f8ec1b134d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137637734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
adc_ctrl_filters_wakeup_fixed.137637734
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.2808411686
Short name T347
Test name
Test status
Simulation time 100905792909 ps
CPU time 524.85 seconds
Started Dec 31 12:32:15 PM PST 23
Finished Dec 31 12:41:02 PM PST 23
Peak memory 201168 kb
Host smart-1b5ffc07-978d-4181-9a0f-1b99bb6038c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808411686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.2808411686
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.309396183
Short name T647
Test name
Test status
Simulation time 43456645473 ps
CPU time 50.78 seconds
Started Dec 31 12:32:24 PM PST 23
Finished Dec 31 12:33:18 PM PST 23
Peak memory 200612 kb
Host smart-d235a203-1b9f-409b-97c0-251aace6e96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309396183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.309396183
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.90280824
Short name T680
Test name
Test status
Simulation time 5117963631 ps
CPU time 12.13 seconds
Started Dec 31 12:32:47 PM PST 23
Finished Dec 31 12:33:01 PM PST 23
Peak memory 200588 kb
Host smart-e67d01c2-43ee-4201-8eae-fc4a8e85e3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90280824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.90280824
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.1675746393
Short name T679
Test name
Test status
Simulation time 6027000311 ps
CPU time 7.57 seconds
Started Dec 31 12:32:14 PM PST 23
Finished Dec 31 12:32:23 PM PST 23
Peak memory 200636 kb
Host smart-997eaf60-5e14-4838-b243-e08f163dc5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675746393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.1675746393
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.3431069277
Short name T809
Test name
Test status
Simulation time 333946875220 ps
CPU time 430.82 seconds
Started Dec 31 12:32:24 PM PST 23
Finished Dec 31 12:39:38 PM PST 23
Peak memory 200776 kb
Host smart-db99fb2b-6137-4b9e-aba6-a3fc3e962501
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431069277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.3431069277
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.2041547102
Short name T835
Test name
Test status
Simulation time 33196008857 ps
CPU time 101.92 seconds
Started Dec 31 12:32:38 PM PST 23
Finished Dec 31 12:34:21 PM PST 23
Peak memory 209500 kb
Host smart-10e97c5e-74a5-4ba5-a30e-c2ee22b63a8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041547102 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.2041547102
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.1677424073
Short name T567
Test name
Test status
Simulation time 309995127 ps
CPU time 1.38 seconds
Started Dec 31 12:32:37 PM PST 23
Finished Dec 31 12:32:39 PM PST 23
Peak memory 200496 kb
Host smart-d7d735c2-8df8-4b10-8669-167957be7b6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677424073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.1677424073
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.3735944285
Short name T234
Test name
Test status
Simulation time 161022117253 ps
CPU time 87.76 seconds
Started Dec 31 12:32:35 PM PST 23
Finished Dec 31 12:34:04 PM PST 23
Peak memory 200824 kb
Host smart-8da3bb13-1541-4769-9d50-0b7072ed0f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735944285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.3735944285
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.2857154078
Short name T722
Test name
Test status
Simulation time 329146910111 ps
CPU time 194.53 seconds
Started Dec 31 12:32:35 PM PST 23
Finished Dec 31 12:35:51 PM PST 23
Peak memory 200684 kb
Host smart-be37ceaf-48eb-4d8a-b601-6f6a559ebbb6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857154078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.2857154078
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.1782652791
Short name T119
Test name
Test status
Simulation time 166355726451 ps
CPU time 43.38 seconds
Started Dec 31 12:32:46 PM PST 23
Finished Dec 31 12:33:31 PM PST 23
Peak memory 200684 kb
Host smart-d0d5091f-2d77-497c-9582-bd208233a4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782652791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.1782652791
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.1773173408
Short name T642
Test name
Test status
Simulation time 166567222836 ps
CPU time 131.2 seconds
Started Dec 31 12:33:04 PM PST 23
Finished Dec 31 12:35:16 PM PST 23
Peak memory 200704 kb
Host smart-65c5c3d8-4c1f-45b0-b3bf-662ffa683f3b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773173408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.1773173408
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.3965510658
Short name T313
Test name
Test status
Simulation time 329950882005 ps
CPU time 756.87 seconds
Started Dec 31 12:32:24 PM PST 23
Finished Dec 31 12:45:04 PM PST 23
Peak memory 200696 kb
Host smart-8176d01e-0ab1-4aa9-9946-89327ced532a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965510658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.3965510658
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.4262654396
Short name T419
Test name
Test status
Simulation time 165376204544 ps
CPU time 137 seconds
Started Dec 31 12:32:24 PM PST 23
Finished Dec 31 12:34:44 PM PST 23
Peak memory 200724 kb
Host smart-ff6956a4-0b4b-4e27-9f18-448224531e68
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262654396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.4262654396
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.4169917468
Short name T600
Test name
Test status
Simulation time 93922380905 ps
CPU time 329.5 seconds
Started Dec 31 12:32:27 PM PST 23
Finished Dec 31 12:38:00 PM PST 23
Peak memory 201108 kb
Host smart-e25e15e0-204f-4667-ac33-bf3e9c0313a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169917468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.4169917468
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.3452011284
Short name T553
Test name
Test status
Simulation time 35257362116 ps
CPU time 19.11 seconds
Started Dec 31 12:32:43 PM PST 23
Finished Dec 31 12:33:05 PM PST 23
Peak memory 200532 kb
Host smart-7236f9e3-19c8-4341-b833-a169691d6f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452011284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.3452011284
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.1087940061
Short name T151
Test name
Test status
Simulation time 3666900159 ps
CPU time 4.19 seconds
Started Dec 31 12:32:29 PM PST 23
Finished Dec 31 12:32:36 PM PST 23
Peak memory 200868 kb
Host smart-ac78f6ae-da3b-4c49-8399-eec77b985116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087940061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.1087940061
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.928618814
Short name T497
Test name
Test status
Simulation time 5643264954 ps
CPU time 13.76 seconds
Started Dec 31 12:32:36 PM PST 23
Finished Dec 31 12:32:51 PM PST 23
Peak memory 200516 kb
Host smart-47f571a2-1e2f-46b3-b814-0ba9d15902de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928618814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.928618814
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.3403592728
Short name T336
Test name
Test status
Simulation time 174704295093 ps
CPU time 93.06 seconds
Started Dec 31 12:32:35 PM PST 23
Finished Dec 31 12:34:09 PM PST 23
Peak memory 200768 kb
Host smart-caf6cf34-b8fd-4cb7-ab3c-0460f9bb8b31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403592728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.3403592728
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.2533778553
Short name T79
Test name
Test status
Simulation time 108210105512 ps
CPU time 250.36 seconds
Started Dec 31 12:32:51 PM PST 23
Finished Dec 31 12:37:02 PM PST 23
Peak memory 209104 kb
Host smart-a96953c3-ee95-48b6-93b9-b6a5fab19581
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533778553 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.2533778553
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.957106351
Short name T49
Test name
Test status
Simulation time 393146775 ps
CPU time 1.47 seconds
Started Dec 31 12:32:19 PM PST 23
Finished Dec 31 12:32:27 PM PST 23
Peak memory 200268 kb
Host smart-a6503c92-4325-4f63-8cc7-1d71afbdb725
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957106351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.957106351
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.920691034
Short name T704
Test name
Test status
Simulation time 162742142379 ps
CPU time 378.32 seconds
Started Dec 31 12:32:41 PM PST 23
Finished Dec 31 12:39:00 PM PST 23
Peak memory 200704 kb
Host smart-0d5813e0-695f-48b9-9e0d-f0cd26991f54
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920691034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gati
ng.920691034
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.573254454
Short name T730
Test name
Test status
Simulation time 162070772267 ps
CPU time 101.39 seconds
Started Dec 31 12:32:55 PM PST 23
Finished Dec 31 12:34:43 PM PST 23
Peak memory 200796 kb
Host smart-51742338-e27f-4583-b188-623e8fd5b7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573254454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.573254454
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.2772620385
Short name T312
Test name
Test status
Simulation time 483457225440 ps
CPU time 76.87 seconds
Started Dec 31 12:32:22 PM PST 23
Finished Dec 31 12:33:44 PM PST 23
Peak memory 200756 kb
Host smart-50ffd9b4-4dd4-4ed1-863f-a2a159599a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772620385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.2772620385
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.2072298638
Short name T751
Test name
Test status
Simulation time 164352425988 ps
CPU time 369.16 seconds
Started Dec 31 12:32:57 PM PST 23
Finished Dec 31 12:39:07 PM PST 23
Peak memory 200764 kb
Host smart-50f3e884-e744-485a-a1a7-787b88095cd2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072298638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.2072298638
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.3514216255
Short name T250
Test name
Test status
Simulation time 166333588183 ps
CPU time 218.67 seconds
Started Dec 31 12:32:48 PM PST 23
Finished Dec 31 12:36:28 PM PST 23
Peak memory 200840 kb
Host smart-3b26e2ca-7d09-4927-acca-523e00c3777c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514216255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.3514216255
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.915978277
Short name T543
Test name
Test status
Simulation time 160548873002 ps
CPU time 20.58 seconds
Started Dec 31 12:32:42 PM PST 23
Finished Dec 31 12:33:03 PM PST 23
Peak memory 200748 kb
Host smart-3350de83-1ac1-495a-bbdd-6efb03eda278
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=915978277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fixe
d.915978277
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.2764912981
Short name T290
Test name
Test status
Simulation time 170111868830 ps
CPU time 181 seconds
Started Dec 31 12:32:53 PM PST 23
Finished Dec 31 12:36:05 PM PST 23
Peak memory 200700 kb
Host smart-7ea10007-2d7f-407f-ae7a-7a028c1f049e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764912981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.2764912981
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.3807131281
Short name T821
Test name
Test status
Simulation time 497118780433 ps
CPU time 565.99 seconds
Started Dec 31 12:32:42 PM PST 23
Finished Dec 31 12:42:09 PM PST 23
Peak memory 200692 kb
Host smart-cf6f866a-c145-4c6f-8dec-38ee81ade144
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807131281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.3807131281
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.1627560232
Short name T178
Test name
Test status
Simulation time 100240541754 ps
CPU time 502.83 seconds
Started Dec 31 12:32:46 PM PST 23
Finished Dec 31 12:41:11 PM PST 23
Peak memory 201172 kb
Host smart-02d6f28a-29ff-4e84-b88d-6ac2dc3e8839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627560232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.1627560232
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.4144831875
Short name T739
Test name
Test status
Simulation time 33887891260 ps
CPU time 83.54 seconds
Started Dec 31 12:32:32 PM PST 23
Finished Dec 31 12:33:57 PM PST 23
Peak memory 200532 kb
Host smart-c5726493-00c3-4511-bdec-ee7f386b1fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144831875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.4144831875
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.1531089004
Short name T813
Test name
Test status
Simulation time 4109542904 ps
CPU time 3.25 seconds
Started Dec 31 12:32:40 PM PST 23
Finished Dec 31 12:32:44 PM PST 23
Peak memory 200552 kb
Host smart-24522e61-c7d3-4d3b-b3c7-95c48d5c8f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531089004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.1531089004
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.1005139464
Short name T19
Test name
Test status
Simulation time 5730218005 ps
CPU time 15.99 seconds
Started Dec 31 12:32:42 PM PST 23
Finished Dec 31 12:32:59 PM PST 23
Peak memory 200592 kb
Host smart-02b3dab5-45ac-46cf-953f-df2493b83137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005139464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.1005139464
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.1732147917
Short name T327
Test name
Test status
Simulation time 385520866406 ps
CPU time 1249.85 seconds
Started Dec 31 12:32:28 PM PST 23
Finished Dec 31 12:53:21 PM PST 23
Peak memory 211400 kb
Host smart-a91bd19e-14a2-4cc7-bb9d-a80deda9611e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732147917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.1732147917
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.3292848658
Short name T572
Test name
Test status
Simulation time 356373801 ps
CPU time 1.02 seconds
Started Dec 31 12:32:00 PM PST 23
Finished Dec 31 12:32:02 PM PST 23
Peak memory 200528 kb
Host smart-4a02d4ca-44aa-42b5-8f68-eadc8857414a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292848658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.3292848658
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.2912329922
Short name T281
Test name
Test status
Simulation time 329668659821 ps
CPU time 204.08 seconds
Started Dec 31 12:32:15 PM PST 23
Finished Dec 31 12:35:41 PM PST 23
Peak memory 200736 kb
Host smart-5f8e32e9-11f3-4d42-bc7b-52f432e391e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912329922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.2912329922
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.1251741451
Short name T793
Test name
Test status
Simulation time 496975158407 ps
CPU time 605.18 seconds
Started Dec 31 12:32:47 PM PST 23
Finished Dec 31 12:42:55 PM PST 23
Peak memory 199400 kb
Host smart-43811b55-5b2c-4797-b6b1-985a50771413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251741451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.1251741451
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.2138859134
Short name T643
Test name
Test status
Simulation time 324100951197 ps
CPU time 740.24 seconds
Started Dec 31 12:33:09 PM PST 23
Finished Dec 31 12:45:36 PM PST 23
Peak memory 200428 kb
Host smart-a27dcbd7-e45f-4cb7-9fd9-15f158629b8a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138859134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.2138859134
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.2396303225
Short name T702
Test name
Test status
Simulation time 162826860587 ps
CPU time 113.29 seconds
Started Dec 31 12:32:07 PM PST 23
Finished Dec 31 12:34:02 PM PST 23
Peak memory 200712 kb
Host smart-9994d76a-bf7d-41b1-b93d-04e04ecbdc6a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396303225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.2396303225
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.1139404761
Short name T272
Test name
Test status
Simulation time 175704058176 ps
CPU time 70.06 seconds
Started Dec 31 12:31:58 PM PST 23
Finished Dec 31 12:33:09 PM PST 23
Peak memory 200700 kb
Host smart-c8160227-8157-4b20-bf52-fcd4b82248b9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139404761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.1139404761
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.2503902907
Short name T174
Test name
Test status
Simulation time 493707475296 ps
CPU time 890.54 seconds
Started Dec 31 12:33:16 PM PST 23
Finished Dec 31 12:48:11 PM PST 23
Peak memory 200756 kb
Host smart-7c71b6e0-c604-4aca-9c4f-15d6366a286e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503902907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.2503902907
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.1469183390
Short name T665
Test name
Test status
Simulation time 109230928024 ps
CPU time 583.56 seconds
Started Dec 31 12:32:02 PM PST 23
Finished Dec 31 12:41:46 PM PST 23
Peak memory 201140 kb
Host smart-70ad24a5-0f54-4c1e-848a-662b940b6288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469183390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.1469183390
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.1814412534
Short name T832
Test name
Test status
Simulation time 40811142196 ps
CPU time 22.08 seconds
Started Dec 31 12:32:13 PM PST 23
Finished Dec 31 12:32:36 PM PST 23
Peak memory 200536 kb
Host smart-666b21bd-751d-4ed8-98d8-10e3a79742d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814412534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.1814412534
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.194689011
Short name T676
Test name
Test status
Simulation time 3489625487 ps
CPU time 8.59 seconds
Started Dec 31 12:32:55 PM PST 23
Finished Dec 31 12:33:05 PM PST 23
Peak memory 200552 kb
Host smart-24845021-c9e3-4c26-98a8-847d145de2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194689011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.194689011
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.1499681627
Short name T54
Test name
Test status
Simulation time 8163203569 ps
CPU time 9.93 seconds
Started Dec 31 12:32:19 PM PST 23
Finished Dec 31 12:32:30 PM PST 23
Peak memory 217000 kb
Host smart-4782b329-3baa-4a0d-ad11-1e66058cc48f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499681627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.1499681627
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.1869726244
Short name T682
Test name
Test status
Simulation time 5837034312 ps
CPU time 13.13 seconds
Started Dec 31 12:32:01 PM PST 23
Finished Dec 31 12:32:16 PM PST 23
Peak memory 200740 kb
Host smart-8b47bd7a-be9f-48cd-84bf-44bf8c13b506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869726244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.1869726244
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.2733846525
Short name T651
Test name
Test status
Simulation time 432579230 ps
CPU time 1.51 seconds
Started Dec 31 12:32:49 PM PST 23
Finished Dec 31 12:32:52 PM PST 23
Peak memory 200532 kb
Host smart-4f0fa6cc-c6c5-4e7c-8e26-c58d27032636
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733846525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.2733846525
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.2712092339
Short name T300
Test name
Test status
Simulation time 487922948626 ps
CPU time 389.13 seconds
Started Dec 31 12:32:45 PM PST 23
Finished Dec 31 12:39:17 PM PST 23
Peak memory 200780 kb
Host smart-89ed86da-bf90-4ac4-a5da-89d435bcebf0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712092339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.2712092339
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.3405938376
Short name T271
Test name
Test status
Simulation time 495731161503 ps
CPU time 565.65 seconds
Started Dec 31 12:32:26 PM PST 23
Finished Dec 31 12:41:54 PM PST 23
Peak memory 200788 kb
Host smart-77cec0cd-f607-48ac-8018-20c2e1242277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405938376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.3405938376
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.191357082
Short name T93
Test name
Test status
Simulation time 336768323233 ps
CPU time 184.85 seconds
Started Dec 31 12:32:47 PM PST 23
Finished Dec 31 12:35:54 PM PST 23
Peak memory 200660 kb
Host smart-a1291e88-2539-45ea-abec-3a38a6a5a6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191357082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.191357082
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.1671714434
Short name T517
Test name
Test status
Simulation time 166757812894 ps
CPU time 359.45 seconds
Started Dec 31 12:32:27 PM PST 23
Finished Dec 31 12:38:29 PM PST 23
Peak memory 200716 kb
Host smart-83ca164f-bfed-4f0c-a4e0-0424b3c5884a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671714434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.1671714434
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.2084844380
Short name T713
Test name
Test status
Simulation time 319182868428 ps
CPU time 382.39 seconds
Started Dec 31 12:32:59 PM PST 23
Finished Dec 31 12:39:22 PM PST 23
Peak memory 200748 kb
Host smart-6094b1c0-ba6a-45c0-a27c-56e4453da007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084844380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.2084844380
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.1762937155
Short name T586
Test name
Test status
Simulation time 330813082718 ps
CPU time 189.06 seconds
Started Dec 31 12:32:43 PM PST 23
Finished Dec 31 12:35:54 PM PST 23
Peak memory 200696 kb
Host smart-f19fcab2-25fc-4610-bcac-eb2e0a290bf2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762937155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.1762937155
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.3488189692
Short name T843
Test name
Test status
Simulation time 174102972438 ps
CPU time 176.15 seconds
Started Dec 31 12:32:49 PM PST 23
Finished Dec 31 12:35:47 PM PST 23
Peak memory 200848 kb
Host smart-f10d5a9a-96bd-4d00-bef4-3bd01c05273c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488189692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.3488189692
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.2205890957
Short name T545
Test name
Test status
Simulation time 324860729294 ps
CPU time 105.26 seconds
Started Dec 31 12:32:45 PM PST 23
Finished Dec 31 12:34:33 PM PST 23
Peak memory 200696 kb
Host smart-de316d47-81fa-4cc9-af12-63b0989bc59e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205890957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.2205890957
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.2903236943
Short name T812
Test name
Test status
Simulation time 83026637632 ps
CPU time 342.46 seconds
Started Dec 31 12:32:47 PM PST 23
Finished Dec 31 12:38:32 PM PST 23
Peak memory 201244 kb
Host smart-ab991ebc-d4e3-4939-bf8c-e90b009ab4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903236943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.2903236943
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.2429647905
Short name T779
Test name
Test status
Simulation time 29984563422 ps
CPU time 65.94 seconds
Started Dec 31 12:32:17 PM PST 23
Finished Dec 31 12:33:26 PM PST 23
Peak memory 200592 kb
Host smart-2af7c809-ca81-4647-8740-c4e058ac733e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429647905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.2429647905
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.4238838806
Short name T534
Test name
Test status
Simulation time 5157006864 ps
CPU time 3.53 seconds
Started Dec 31 12:32:37 PM PST 23
Finished Dec 31 12:32:41 PM PST 23
Peak memory 200580 kb
Host smart-9b07ec52-cae2-49a4-aa02-0c2e283347e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238838806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.4238838806
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.3958849936
Short name T776
Test name
Test status
Simulation time 5981097558 ps
CPU time 7.55 seconds
Started Dec 31 12:32:57 PM PST 23
Finished Dec 31 12:33:06 PM PST 23
Peak memory 200572 kb
Host smart-4f4bb2af-d9bd-4470-94cc-10f1e39e2119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958849936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.3958849936
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.1833691890
Short name T283
Test name
Test status
Simulation time 194532962470 ps
CPU time 392.76 seconds
Started Dec 31 12:32:45 PM PST 23
Finished Dec 31 12:39:20 PM PST 23
Peak memory 200724 kb
Host smart-a4961f9e-6af8-492b-a45e-b555f1864b4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833691890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.1833691890
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.2413791056
Short name T51
Test name
Test status
Simulation time 298694131 ps
CPU time 1.15 seconds
Started Dec 31 12:32:47 PM PST 23
Finished Dec 31 12:32:50 PM PST 23
Peak memory 200600 kb
Host smart-8bc42d34-ed05-48b9-87b5-cbec7e07cb29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413791056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.2413791056
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.33970314
Short name T297
Test name
Test status
Simulation time 166531427915 ps
CPU time 368.88 seconds
Started Dec 31 12:32:31 PM PST 23
Finished Dec 31 12:38:42 PM PST 23
Peak memory 200700 kb
Host smart-f8eb92e9-1158-49ae-b1cd-1fbf0bc802f1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33970314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gatin
g.33970314
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.634226245
Short name T692
Test name
Test status
Simulation time 158213486388 ps
CPU time 359.03 seconds
Started Dec 31 12:32:54 PM PST 23
Finished Dec 31 12:38:54 PM PST 23
Peak memory 200808 kb
Host smart-9a503dcb-5f36-4240-ac9b-1e6cc10fb550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634226245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.634226245
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.2919893014
Short name T202
Test name
Test status
Simulation time 329644259240 ps
CPU time 720.79 seconds
Started Dec 31 12:32:48 PM PST 23
Finished Dec 31 12:44:50 PM PST 23
Peak memory 200848 kb
Host smart-2e5b9556-a5e2-4add-8c19-047873ba9a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919893014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.2919893014
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.3453201865
Short name T585
Test name
Test status
Simulation time 491310230264 ps
CPU time 1176.71 seconds
Started Dec 31 12:32:19 PM PST 23
Finished Dec 31 12:52:02 PM PST 23
Peak memory 200716 kb
Host smart-dc1d6a9d-f643-4284-b8ce-cb3083bceceb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453201865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.3453201865
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.455982859
Short name T789
Test name
Test status
Simulation time 332935165616 ps
CPU time 198.11 seconds
Started Dec 31 12:32:35 PM PST 23
Finished Dec 31 12:35:55 PM PST 23
Peak memory 200688 kb
Host smart-290e0590-1aba-4d1a-8683-c10c0ab8a976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455982859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.455982859
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.333852969
Short name T711
Test name
Test status
Simulation time 331916382559 ps
CPU time 357.45 seconds
Started Dec 31 12:32:32 PM PST 23
Finished Dec 31 12:38:31 PM PST 23
Peak memory 200804 kb
Host smart-2f2a74f2-3c2b-471c-a37a-2ddb86ab4082
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=333852969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fixe
d.333852969
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.1629987353
Short name T95
Test name
Test status
Simulation time 333893961650 ps
CPU time 107.91 seconds
Started Dec 31 12:32:45 PM PST 23
Finished Dec 31 12:34:36 PM PST 23
Peak memory 200720 kb
Host smart-0dec9c04-e605-424e-995c-9d6e4718ec12
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629987353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.1629987353
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.4255783716
Short name T664
Test name
Test status
Simulation time 167366029984 ps
CPU time 92.9 seconds
Started Dec 31 12:32:45 PM PST 23
Finished Dec 31 12:34:20 PM PST 23
Peak memory 200676 kb
Host smart-7f02b464-4617-4438-a898-ec18cb28105c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255783716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.4255783716
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.3559133439
Short name T183
Test name
Test status
Simulation time 123168541759 ps
CPU time 638.32 seconds
Started Dec 31 12:32:55 PM PST 23
Finished Dec 31 12:43:35 PM PST 23
Peak memory 201236 kb
Host smart-6e40ec0d-9253-4731-b1cb-4038e2c9f399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559133439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.3559133439
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.2783983899
Short name T817
Test name
Test status
Simulation time 37356431279 ps
CPU time 28.41 seconds
Started Dec 31 12:32:43 PM PST 23
Finished Dec 31 12:33:13 PM PST 23
Peak memory 200608 kb
Host smart-51a4c052-0c33-4cb7-8e90-39aec044a46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783983899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.2783983899
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.2900963478
Short name T533
Test name
Test status
Simulation time 5063537861 ps
CPU time 3.88 seconds
Started Dec 31 12:32:34 PM PST 23
Finished Dec 31 12:32:39 PM PST 23
Peak memory 200508 kb
Host smart-f5f077d6-45ca-4890-a544-14e1daafb6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900963478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.2900963478
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.3695899318
Short name T460
Test name
Test status
Simulation time 5690312118 ps
CPU time 4.01 seconds
Started Dec 31 12:32:11 PM PST 23
Finished Dec 31 12:32:16 PM PST 23
Peak memory 200536 kb
Host smart-0daa83c7-c399-4211-9b95-1cda4389cece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695899318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.3695899318
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.834607030
Short name T293
Test name
Test status
Simulation time 208333929933 ps
CPU time 429.97 seconds
Started Dec 31 12:32:53 PM PST 23
Finished Dec 31 12:40:04 PM PST 23
Peak memory 200788 kb
Host smart-536c204f-0d02-4736-8397-01c91eefbfa3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834607030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all.
834607030
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.753434911
Short name T259
Test name
Test status
Simulation time 83326629811 ps
CPU time 19.99 seconds
Started Dec 31 12:32:51 PM PST 23
Finished Dec 31 12:33:12 PM PST 23
Peak memory 200768 kb
Host smart-41d23999-3c9d-4341-8381-8c12c1f7cf55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753434911 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.753434911
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.2869924041
Short name T556
Test name
Test status
Simulation time 356899358 ps
CPU time 1.35 seconds
Started Dec 31 12:32:36 PM PST 23
Finished Dec 31 12:32:38 PM PST 23
Peak memory 200480 kb
Host smart-809a3ad0-acd5-4401-b077-9633785ad398
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869924041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.2869924041
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.2521746386
Short name T334
Test name
Test status
Simulation time 487264587172 ps
CPU time 473.42 seconds
Started Dec 31 12:32:44 PM PST 23
Finished Dec 31 12:40:40 PM PST 23
Peak memory 200808 kb
Host smart-fe638225-7786-4f37-8fa6-824ecb8d4ea3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521746386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.2521746386
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.1305305393
Short name T487
Test name
Test status
Simulation time 164555408777 ps
CPU time 88.98 seconds
Started Dec 31 12:32:35 PM PST 23
Finished Dec 31 12:34:05 PM PST 23
Peak memory 200692 kb
Host smart-06e9020d-ee2e-4eb0-86b9-fc5c8b7eda45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305305393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.1305305393
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.3384774588
Short name T257
Test name
Test status
Simulation time 322012226228 ps
CPU time 737.14 seconds
Started Dec 31 12:32:40 PM PST 23
Finished Dec 31 12:44:58 PM PST 23
Peak memory 200772 kb
Host smart-238bc606-7ae4-4a1f-b6ba-428d40710177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384774588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.3384774588
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.987816516
Short name T454
Test name
Test status
Simulation time 161520722382 ps
CPU time 377.6 seconds
Started Dec 31 12:32:27 PM PST 23
Finished Dec 31 12:38:48 PM PST 23
Peak memory 200716 kb
Host smart-627b67f8-78f6-4917-a03a-a06b7267de0e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=987816516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrup
t_fixed.987816516
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.746102322
Short name T738
Test name
Test status
Simulation time 496022953869 ps
CPU time 177.15 seconds
Started Dec 31 12:32:34 PM PST 23
Finished Dec 31 12:35:33 PM PST 23
Peak memory 200752 kb
Host smart-b4a99694-8fb8-4ea9-be77-a91641dae8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746102322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.746102322
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.888524992
Short name T525
Test name
Test status
Simulation time 160785631805 ps
CPU time 201.37 seconds
Started Dec 31 12:32:28 PM PST 23
Finished Dec 31 12:35:52 PM PST 23
Peak memory 200664 kb
Host smart-d9421b48-8456-475d-b17a-6fcca56f317c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=888524992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fixe
d.888524992
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.82515607
Short name T342
Test name
Test status
Simulation time 328670222719 ps
CPU time 414.05 seconds
Started Dec 31 12:33:06 PM PST 23
Finished Dec 31 12:40:03 PM PST 23
Peak memory 200736 kb
Host smart-79f31d63-8a72-4528-8e74-22ed2736d804
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82515607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_w
akeup.82515607
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.3018547958
Short name T834
Test name
Test status
Simulation time 164959049269 ps
CPU time 97.25 seconds
Started Dec 31 12:32:35 PM PST 23
Finished Dec 31 12:34:14 PM PST 23
Peak memory 200688 kb
Host smart-00c7fa39-7e29-42ae-8cb1-31310044d175
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018547958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.3018547958
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.3851210586
Short name T842
Test name
Test status
Simulation time 63783236540 ps
CPU time 243.3 seconds
Started Dec 31 12:32:36 PM PST 23
Finished Dec 31 12:36:46 PM PST 23
Peak memory 201140 kb
Host smart-f6b8af68-7cc0-4c87-803f-c318f2e4a95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851210586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.3851210586
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.286488522
Short name T509
Test name
Test status
Simulation time 31102141416 ps
CPU time 69.67 seconds
Started Dec 31 12:32:16 PM PST 23
Finished Dec 31 12:33:28 PM PST 23
Peak memory 200652 kb
Host smart-93cf48af-5820-458e-a34b-bd29c9c02125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286488522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.286488522
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.2221503465
Short name T471
Test name
Test status
Simulation time 3096214280 ps
CPU time 8.18 seconds
Started Dec 31 12:32:44 PM PST 23
Finished Dec 31 12:32:55 PM PST 23
Peak memory 200492 kb
Host smart-597a5611-844e-4d2b-8d1f-82945b627c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221503465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.2221503465
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.1879372742
Short name T152
Test name
Test status
Simulation time 6125133309 ps
CPU time 7.87 seconds
Started Dec 31 12:32:37 PM PST 23
Finished Dec 31 12:32:46 PM PST 23
Peak memory 200456 kb
Host smart-1dbcbb17-8087-47a8-9841-b709a36ae7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879372742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.1879372742
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.3878836220
Short name T482
Test name
Test status
Simulation time 192951925712 ps
CPU time 470.88 seconds
Started Dec 31 12:32:28 PM PST 23
Finished Dec 31 12:40:22 PM PST 23
Peak memory 200640 kb
Host smart-43575ba1-4a80-488f-9b3f-c2695f63d791
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878836220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.3878836220
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.3809861975
Short name T559
Test name
Test status
Simulation time 65571187685 ps
CPU time 180.66 seconds
Started Dec 31 12:32:37 PM PST 23
Finished Dec 31 12:35:38 PM PST 23
Peak memory 209368 kb
Host smart-9efd03ab-6c76-4445-9f75-24ca167d6724
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809861975 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.3809861975
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.3642892257
Short name T50
Test name
Test status
Simulation time 344545122 ps
CPU time 1.14 seconds
Started Dec 31 12:32:41 PM PST 23
Finished Dec 31 12:32:43 PM PST 23
Peak memory 200520 kb
Host smart-6eaa0019-1919-4532-b2a1-a11a95c8671f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642892257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.3642892257
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.4081872285
Short name T218
Test name
Test status
Simulation time 161819512593 ps
CPU time 94.34 seconds
Started Dec 31 12:32:31 PM PST 23
Finished Dec 31 12:34:07 PM PST 23
Peak memory 200808 kb
Host smart-11a898a9-022d-4d22-a9d7-8eb5ce1b29e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081872285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.4081872285
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.1385544009
Short name T230
Test name
Test status
Simulation time 329154966228 ps
CPU time 798.35 seconds
Started Dec 31 12:32:37 PM PST 23
Finished Dec 31 12:45:56 PM PST 23
Peak memory 200748 kb
Host smart-4fbed238-3953-4da0-b4a0-8e742b094d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385544009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.1385544009
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.2722696995
Short name T661
Test name
Test status
Simulation time 162463268335 ps
CPU time 369.44 seconds
Started Dec 31 12:32:52 PM PST 23
Finished Dec 31 12:39:02 PM PST 23
Peak memory 200852 kb
Host smart-35907cff-f039-4307-896e-0fc45ab3b489
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722696995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.2722696995
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.4065673387
Short name T653
Test name
Test status
Simulation time 499628413738 ps
CPU time 521 seconds
Started Dec 31 12:32:50 PM PST 23
Finished Dec 31 12:41:33 PM PST 23
Peak memory 200744 kb
Host smart-21fb80a6-fde3-45ff-83c7-0b20ab59c33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065673387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.4065673387
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.2530505043
Short name T633
Test name
Test status
Simulation time 330531927611 ps
CPU time 288.94 seconds
Started Dec 31 12:33:18 PM PST 23
Finished Dec 31 12:38:10 PM PST 23
Peak memory 200736 kb
Host smart-c660a5a5-cfb3-40fd-9526-c965380992f1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530505043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.2530505043
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.1507103075
Short name T666
Test name
Test status
Simulation time 173331829768 ps
CPU time 115.62 seconds
Started Dec 31 12:32:27 PM PST 23
Finished Dec 31 12:34:26 PM PST 23
Peak memory 200804 kb
Host smart-6eea43fd-a128-48d3-b8c5-db08b5d4d92b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507103075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.1507103075
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.2620925875
Short name T627
Test name
Test status
Simulation time 165084168236 ps
CPU time 344.61 seconds
Started Dec 31 12:32:43 PM PST 23
Finished Dec 31 12:38:30 PM PST 23
Peak memory 200772 kb
Host smart-73b0f360-9a32-47d7-902b-9e0d3bcd1b8c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620925875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.2620925875
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.2200437859
Short name T421
Test name
Test status
Simulation time 36411861111 ps
CPU time 77.86 seconds
Started Dec 31 12:32:30 PM PST 23
Finished Dec 31 12:33:50 PM PST 23
Peak memory 200592 kb
Host smart-df97b75b-40c3-4ca1-bbad-f484e10e3890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200437859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.2200437859
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.973368754
Short name T646
Test name
Test status
Simulation time 3050252334 ps
CPU time 5.16 seconds
Started Dec 31 12:32:50 PM PST 23
Finished Dec 31 12:32:56 PM PST 23
Peak memory 200624 kb
Host smart-32d90772-f331-4200-b23c-2654966b961c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973368754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.973368754
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.501077755
Short name T688
Test name
Test status
Simulation time 6059635050 ps
CPU time 7.95 seconds
Started Dec 31 12:32:53 PM PST 23
Finished Dec 31 12:33:02 PM PST 23
Peak memory 200580 kb
Host smart-24a872a9-42aa-4883-b60b-1c34e72925f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501077755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.501077755
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.3866097077
Short name T330
Test name
Test status
Simulation time 322100220782 ps
CPU time 670.1 seconds
Started Dec 31 12:32:39 PM PST 23
Finished Dec 31 12:43:50 PM PST 23
Peak memory 201200 kb
Host smart-c24174f0-ca96-427c-b027-451c53d956ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866097077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.3866097077
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.2952638473
Short name T208
Test name
Test status
Simulation time 401265272653 ps
CPU time 74.12 seconds
Started Dec 31 12:32:46 PM PST 23
Finished Dec 31 12:34:02 PM PST 23
Peak memory 209228 kb
Host smart-e31b8e15-76cc-42c5-8d95-4c9d3de72673
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952638473 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.2952638473
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.3205818404
Short name T674
Test name
Test status
Simulation time 287029179 ps
CPU time 0.9 seconds
Started Dec 31 12:32:49 PM PST 23
Finished Dec 31 12:32:52 PM PST 23
Peak memory 200508 kb
Host smart-370d9772-a35b-4864-86b3-94d840bcdbb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205818404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.3205818404
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.3145301535
Short name T764
Test name
Test status
Simulation time 167527468434 ps
CPU time 107.19 seconds
Started Dec 31 12:32:43 PM PST 23
Finished Dec 31 12:34:33 PM PST 23
Peak memory 200748 kb
Host smart-69f2a009-7336-4f80-aa9d-6184909c44aa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145301535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.3145301535
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.522378309
Short name T286
Test name
Test status
Simulation time 166418658858 ps
CPU time 393 seconds
Started Dec 31 12:33:03 PM PST 23
Finished Dec 31 12:39:37 PM PST 23
Peak memory 200720 kb
Host smart-b4428220-8345-43a2-b3a0-23cf8a0ccbe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522378309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.522378309
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.986821853
Short name T595
Test name
Test status
Simulation time 334693750044 ps
CPU time 740.58 seconds
Started Dec 31 12:32:56 PM PST 23
Finished Dec 31 12:45:18 PM PST 23
Peak memory 200736 kb
Host smart-4cbb28e0-2329-40d1-aa2e-1f0fac51486c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=986821853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrup
t_fixed.986821853
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.3466838839
Short name T766
Test name
Test status
Simulation time 158290996217 ps
CPU time 200.71 seconds
Started Dec 31 12:32:31 PM PST 23
Finished Dec 31 12:35:54 PM PST 23
Peak memory 200784 kb
Host smart-674cc7a2-fedc-4b10-9295-b1b95a962fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466838839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.3466838839
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.2985462922
Short name T849
Test name
Test status
Simulation time 327011315346 ps
CPU time 729.83 seconds
Started Dec 31 12:32:59 PM PST 23
Finished Dec 31 12:45:10 PM PST 23
Peak memory 200708 kb
Host smart-2384404d-bade-4146-8974-fc24c4e62b7b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985462922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.2985462922
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.1078163643
Short name T505
Test name
Test status
Simulation time 491509117512 ps
CPU time 293.44 seconds
Started Dec 31 12:32:46 PM PST 23
Finished Dec 31 12:37:42 PM PST 23
Peak memory 200756 kb
Host smart-ada47c28-985d-4d26-8d23-79a6083eeb89
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078163643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.1078163643
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.2967697034
Short name T546
Test name
Test status
Simulation time 112888303735 ps
CPU time 420.13 seconds
Started Dec 31 12:32:41 PM PST 23
Finished Dec 31 12:39:41 PM PST 23
Peak memory 201208 kb
Host smart-94645358-5fdb-424d-b80f-3596f875783d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967697034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.2967697034
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.3232648969
Short name T537
Test name
Test status
Simulation time 36089457958 ps
CPU time 14 seconds
Started Dec 31 12:32:49 PM PST 23
Finished Dec 31 12:33:04 PM PST 23
Peak memory 200588 kb
Host smart-d09740d8-e1fb-430c-9f46-322d0866167b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232648969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.3232648969
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.832200005
Short name T685
Test name
Test status
Simulation time 3704065123 ps
CPU time 9.49 seconds
Started Dec 31 12:32:34 PM PST 23
Finished Dec 31 12:32:46 PM PST 23
Peak memory 200568 kb
Host smart-6f20ea7f-aeb0-41b6-929c-3e0ab8403209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832200005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.832200005
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.443363195
Short name T430
Test name
Test status
Simulation time 6292627139 ps
CPU time 4.07 seconds
Started Dec 31 12:32:52 PM PST 23
Finished Dec 31 12:32:57 PM PST 23
Peak memory 200576 kb
Host smart-86bf3a6b-b282-4afb-a797-cbf4c6c6a5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443363195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.443363195
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.3257165770
Short name T284
Test name
Test status
Simulation time 487163474569 ps
CPU time 161.15 seconds
Started Dec 31 12:32:50 PM PST 23
Finished Dec 31 12:35:33 PM PST 23
Peak memory 200680 kb
Host smart-cd2bb79e-cec4-4c15-86a9-3f5617f6fa6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257165770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.3257165770
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.3192390028
Short name T619
Test name
Test status
Simulation time 529529429 ps
CPU time 0.91 seconds
Started Dec 31 12:33:07 PM PST 23
Finished Dec 31 12:33:11 PM PST 23
Peak memory 200512 kb
Host smart-18343053-2531-4d8e-9a86-da2f2bc3780f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192390028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.3192390028
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.320816432
Short name T278
Test name
Test status
Simulation time 336896798070 ps
CPU time 82.88 seconds
Started Dec 31 12:32:36 PM PST 23
Finished Dec 31 12:34:00 PM PST 23
Peak memory 200692 kb
Host smart-996654fa-de2a-47c1-b4a1-c68e0db378e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320816432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.320816432
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.2315915684
Short name T785
Test name
Test status
Simulation time 333362444687 ps
CPU time 827.52 seconds
Started Dec 31 12:32:50 PM PST 23
Finished Dec 31 12:46:39 PM PST 23
Peak memory 200776 kb
Host smart-0a348c0a-ab63-47c6-9b0f-ea52918313fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315915684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.2315915684
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.3382838135
Short name T696
Test name
Test status
Simulation time 329007190622 ps
CPU time 753.88 seconds
Started Dec 31 12:33:04 PM PST 23
Finished Dec 31 12:45:44 PM PST 23
Peak memory 200800 kb
Host smart-7bb0e1ab-40ee-4a3a-9ba3-47a795c93789
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382838135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.3382838135
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.2308656717
Short name T495
Test name
Test status
Simulation time 162102175726 ps
CPU time 379.71 seconds
Started Dec 31 12:33:03 PM PST 23
Finished Dec 31 12:39:24 PM PST 23
Peak memory 200788 kb
Host smart-760b02f7-dc8c-496d-b0af-50a2e091cad6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308656717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.2308656717
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.4175837342
Short name T309
Test name
Test status
Simulation time 328369053690 ps
CPU time 195.64 seconds
Started Dec 31 12:32:53 PM PST 23
Finished Dec 31 12:36:21 PM PST 23
Peak memory 200740 kb
Host smart-6b33a8a5-6a74-4a35-8d1a-5e05594aaa0e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175837342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.4175837342
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.1799370295
Short name T450
Test name
Test status
Simulation time 328575202166 ps
CPU time 200.6 seconds
Started Dec 31 12:32:47 PM PST 23
Finished Dec 31 12:36:10 PM PST 23
Peak memory 200712 kb
Host smart-77cdc64a-ab24-43f3-888b-e8b0f41ba0cd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799370295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.1799370295
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.66397199
Short name T170
Test name
Test status
Simulation time 35350375997 ps
CPU time 20.52 seconds
Started Dec 31 12:32:42 PM PST 23
Finished Dec 31 12:33:04 PM PST 23
Peak memory 200624 kb
Host smart-d2701f3a-d7bb-458b-8510-bf3e42dc6e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66397199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.66397199
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.1464460385
Short name T621
Test name
Test status
Simulation time 3969384242 ps
CPU time 8.36 seconds
Started Dec 31 12:32:48 PM PST 23
Finished Dec 31 12:32:58 PM PST 23
Peak memory 200588 kb
Host smart-fefcad37-b93a-4d54-bef5-1291350ac29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464460385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.1464460385
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.175972592
Short name T417
Test name
Test status
Simulation time 5856740554 ps
CPU time 14.4 seconds
Started Dec 31 12:32:28 PM PST 23
Finished Dec 31 12:32:45 PM PST 23
Peak memory 200520 kb
Host smart-62f678e8-3e7c-495a-8722-653efd352768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175972592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.175972592
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.1420507264
Short name T804
Test name
Test status
Simulation time 94555367163 ps
CPU time 493.75 seconds
Started Dec 31 12:33:44 PM PST 23
Finished Dec 31 12:41:59 PM PST 23
Peak memory 209104 kb
Host smart-07e6a974-7e78-468a-97eb-4d6da670aa47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420507264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.1420507264
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.3619984525
Short name T435
Test name
Test status
Simulation time 19782747037 ps
CPU time 64.37 seconds
Started Dec 31 12:33:01 PM PST 23
Finished Dec 31 12:34:07 PM PST 23
Peak memory 201384 kb
Host smart-57f37634-98d7-4009-b994-4b405d3993b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619984525 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.3619984525
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.279385309
Short name T803
Test name
Test status
Simulation time 353783617 ps
CPU time 1 seconds
Started Dec 31 12:32:43 PM PST 23
Finished Dec 31 12:32:45 PM PST 23
Peak memory 200508 kb
Host smart-496f35fd-00d2-450b-aa44-b7ded2ff7399
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279385309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.279385309
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.1500429377
Short name T326
Test name
Test status
Simulation time 163852380161 ps
CPU time 195.02 seconds
Started Dec 31 12:33:04 PM PST 23
Finished Dec 31 12:36:20 PM PST 23
Peak memory 200808 kb
Host smart-530ca6b2-ce82-41a4-95e9-c5449b196e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500429377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.1500429377
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.2008542209
Short name T144
Test name
Test status
Simulation time 161772949279 ps
CPU time 51.76 seconds
Started Dec 31 12:32:56 PM PST 23
Finished Dec 31 12:33:49 PM PST 23
Peak memory 200752 kb
Host smart-df9ead0e-3e26-45dd-992d-b245cb837cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008542209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.2008542209
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.2121628272
Short name T455
Test name
Test status
Simulation time 490729553515 ps
CPU time 329.81 seconds
Started Dec 31 12:32:54 PM PST 23
Finished Dec 31 12:38:25 PM PST 23
Peak memory 200652 kb
Host smart-cae37f8f-8e8d-4da4-8502-5b3f8edc61a7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121628272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.2121628272
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.1966075503
Short name T594
Test name
Test status
Simulation time 163154380758 ps
CPU time 375.66 seconds
Started Dec 31 12:33:00 PM PST 23
Finished Dec 31 12:39:17 PM PST 23
Peak memory 200872 kb
Host smart-37292791-a077-4e22-812b-19b031b41520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966075503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.1966075503
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.2090638366
Short name T690
Test name
Test status
Simulation time 482636173572 ps
CPU time 1076.18 seconds
Started Dec 31 12:32:59 PM PST 23
Finished Dec 31 12:51:01 PM PST 23
Peak memory 200744 kb
Host smart-5c373592-102d-4bcd-a1f8-97d9176b5283
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090638366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.2090638366
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.405623678
Short name T741
Test name
Test status
Simulation time 166926208488 ps
CPU time 92.23 seconds
Started Dec 31 12:32:41 PM PST 23
Finished Dec 31 12:34:14 PM PST 23
Peak memory 200728 kb
Host smart-e25c0624-5254-4735-8a98-c6e551a1e74e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405623678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_
wakeup.405623678
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.327302859
Short name T15
Test name
Test status
Simulation time 327085588849 ps
CPU time 187.12 seconds
Started Dec 31 12:32:42 PM PST 23
Finished Dec 31 12:35:50 PM PST 23
Peak memory 200716 kb
Host smart-5ea1e758-7cb1-4654-9fe3-f74b5ba187d5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327302859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
adc_ctrl_filters_wakeup_fixed.327302859
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.100105393
Short name T348
Test name
Test status
Simulation time 124532745564 ps
CPU time 494.45 seconds
Started Dec 31 12:32:46 PM PST 23
Finished Dec 31 12:41:03 PM PST 23
Peak memory 201344 kb
Host smart-a48835e9-c4cb-4292-800d-fb0ade647721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100105393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.100105393
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.2376123244
Short name T719
Test name
Test status
Simulation time 39376486577 ps
CPU time 15.21 seconds
Started Dec 31 12:32:47 PM PST 23
Finished Dec 31 12:33:05 PM PST 23
Peak memory 200576 kb
Host smart-787ae915-c34f-4a38-a960-2e6b8de4b92c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376123244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.2376123244
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.761397518
Short name T45
Test name
Test status
Simulation time 3380161783 ps
CPU time 6.47 seconds
Started Dec 31 12:32:35 PM PST 23
Finished Dec 31 12:32:43 PM PST 23
Peak memory 200536 kb
Host smart-58819a11-11dc-4747-85f1-18d7fe997f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761397518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.761397518
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.1371124897
Short name T840
Test name
Test status
Simulation time 6117422300 ps
CPU time 2.74 seconds
Started Dec 31 12:32:50 PM PST 23
Finished Dec 31 12:32:54 PM PST 23
Peak memory 200508 kb
Host smart-31d66025-5fdf-43a9-80a2-28d1e6315b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371124897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.1371124897
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.2580478172
Short name T772
Test name
Test status
Simulation time 183645134122 ps
CPU time 448.36 seconds
Started Dec 31 12:32:44 PM PST 23
Finished Dec 31 12:40:16 PM PST 23
Peak memory 200692 kb
Host smart-a6f85e2f-8455-45df-9103-3863839f61df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580478172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.2580478172
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.1604747088
Short name T195
Test name
Test status
Simulation time 394285529582 ps
CPU time 214.96 seconds
Started Dec 31 12:32:44 PM PST 23
Finished Dec 31 12:36:21 PM PST 23
Peak memory 209524 kb
Host smart-2e678a70-2af5-4133-8c84-d06166d1e8cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604747088 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.1604747088
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.3428720452
Short name T645
Test name
Test status
Simulation time 546694233 ps
CPU time 0.7 seconds
Started Dec 31 12:32:49 PM PST 23
Finished Dec 31 12:32:51 PM PST 23
Peak memory 200536 kb
Host smart-9ab4165f-d3a1-4c24-bd8e-4b194beba354
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428720452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.3428720452
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.513483719
Short name T541
Test name
Test status
Simulation time 338938593654 ps
CPU time 813.49 seconds
Started Dec 31 12:32:32 PM PST 23
Finished Dec 31 12:46:07 PM PST 23
Peak memory 200776 kb
Host smart-31c8ed59-d531-4fde-a71a-cecbb15577ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513483719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.513483719
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.1466607484
Short name T786
Test name
Test status
Simulation time 329832445194 ps
CPU time 819.28 seconds
Started Dec 31 12:32:37 PM PST 23
Finished Dec 31 12:46:17 PM PST 23
Peak memory 200800 kb
Host smart-11e46c53-5054-43d8-9d06-7708e54812c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466607484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.1466607484
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.3784248962
Short name T570
Test name
Test status
Simulation time 488610319102 ps
CPU time 614.49 seconds
Started Dec 31 12:32:48 PM PST 23
Finished Dec 31 12:43:04 PM PST 23
Peak memory 200700 kb
Host smart-2890fe27-5678-444a-956e-592ee3f60562
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784248962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.3784248962
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.1004872764
Short name T606
Test name
Test status
Simulation time 160119764601 ps
CPU time 344.6 seconds
Started Dec 31 12:32:49 PM PST 23
Finished Dec 31 12:38:35 PM PST 23
Peak memory 200996 kb
Host smart-8c930225-9a64-4e7f-95cc-2a1c57292d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004872764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.1004872764
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.1988970550
Short name T814
Test name
Test status
Simulation time 329288665781 ps
CPU time 195.34 seconds
Started Dec 31 12:34:13 PM PST 23
Finished Dec 31 12:37:30 PM PST 23
Peak memory 200716 kb
Host smart-36f2196a-09c9-46bf-a3df-4a9943063988
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988970550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.1988970550
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.1714924432
Short name T243
Test name
Test status
Simulation time 334475958704 ps
CPU time 188.31 seconds
Started Dec 31 12:32:47 PM PST 23
Finished Dec 31 12:35:57 PM PST 23
Peak memory 200784 kb
Host smart-b583bf51-dddc-4ae9-ac67-9c3e03d500d4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714924432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.1714924432
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.964843821
Short name T479
Test name
Test status
Simulation time 161994015839 ps
CPU time 77.99 seconds
Started Dec 31 12:32:51 PM PST 23
Finished Dec 31 12:34:10 PM PST 23
Peak memory 200716 kb
Host smart-2d5aab97-1351-4f4e-ae43-82960855a53c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964843821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
adc_ctrl_filters_wakeup_fixed.964843821
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.4030953364
Short name T605
Test name
Test status
Simulation time 96544630912 ps
CPU time 421.09 seconds
Started Dec 31 12:32:59 PM PST 23
Finished Dec 31 12:40:01 PM PST 23
Peak memory 201212 kb
Host smart-9b78401d-7752-43c1-a994-39f833358972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030953364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.4030953364
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.2803692477
Short name T462
Test name
Test status
Simulation time 30685139075 ps
CPU time 56.91 seconds
Started Dec 31 12:32:50 PM PST 23
Finished Dec 31 12:33:48 PM PST 23
Peak memory 200468 kb
Host smart-307918fb-9344-4d4c-834a-fb384d7108fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803692477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.2803692477
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.3547999612
Short name T501
Test name
Test status
Simulation time 4786688397 ps
CPU time 12.05 seconds
Started Dec 31 12:32:43 PM PST 23
Finished Dec 31 12:32:56 PM PST 23
Peak memory 200576 kb
Host smart-ec3eb831-4c32-4b6d-84b7-c3f0c8079806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547999612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.3547999612
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.1131782545
Short name T660
Test name
Test status
Simulation time 6074253409 ps
CPU time 3.54 seconds
Started Dec 31 12:32:53 PM PST 23
Finished Dec 31 12:32:57 PM PST 23
Peak memory 200500 kb
Host smart-2945de71-f469-4e87-890d-d73bc1eef8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131782545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.1131782545
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.543139655
Short name T291
Test name
Test status
Simulation time 120739557163 ps
CPU time 362.95 seconds
Started Dec 31 12:32:55 PM PST 23
Finished Dec 31 12:39:00 PM PST 23
Peak memory 209464 kb
Host smart-17e90588-c6a2-4ef1-85b9-3529c2bb9dd2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543139655 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.543139655
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.618703403
Short name T686
Test name
Test status
Simulation time 308872274 ps
CPU time 1.31 seconds
Started Dec 31 12:32:46 PM PST 23
Finished Dec 31 12:32:50 PM PST 23
Peak memory 200528 kb
Host smart-35ea5910-a88a-4034-8ac3-b1af5bb03918
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618703403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.618703403
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.1665165499
Short name T240
Test name
Test status
Simulation time 168059306242 ps
CPU time 22.86 seconds
Started Dec 31 12:33:01 PM PST 23
Finished Dec 31 12:33:26 PM PST 23
Peak memory 200700 kb
Host smart-7ede3d8e-c714-4619-a65a-e6d5c7d658a5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665165499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.1665165499
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.28312188
Short name T768
Test name
Test status
Simulation time 167480728392 ps
CPU time 31.66 seconds
Started Dec 31 12:32:53 PM PST 23
Finished Dec 31 12:33:26 PM PST 23
Peak memory 200660 kb
Host smart-9a8c1a27-3b94-4c8a-b229-ab95affcc4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28312188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.28312188
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.1036708531
Short name T760
Test name
Test status
Simulation time 161910015667 ps
CPU time 375.57 seconds
Started Dec 31 12:32:43 PM PST 23
Finished Dec 31 12:39:01 PM PST 23
Peak memory 200712 kb
Host smart-eccdf432-ee4b-4f72-9389-a60a394ea55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036708531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.1036708531
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.1320735552
Short name T857
Test name
Test status
Simulation time 328968629157 ps
CPU time 181.65 seconds
Started Dec 31 12:33:00 PM PST 23
Finished Dec 31 12:36:03 PM PST 23
Peak memory 200728 kb
Host smart-e3374c46-5a0b-4eca-90a3-065e29de9b8a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320735552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.1320735552
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.1327684135
Short name T452
Test name
Test status
Simulation time 495528458952 ps
CPU time 1185.91 seconds
Started Dec 31 12:32:49 PM PST 23
Finished Dec 31 12:52:36 PM PST 23
Peak memory 200672 kb
Host smart-6c37a92d-f2c1-49e3-8367-601c08174d57
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327684135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.1327684135
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.2061296989
Short name T859
Test name
Test status
Simulation time 187674497268 ps
CPU time 104.57 seconds
Started Dec 31 12:32:59 PM PST 23
Finished Dec 31 12:34:44 PM PST 23
Peak memory 200788 kb
Host smart-c8d4f4ff-3c2a-4d5c-9e7b-fd4a41d9a012
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061296989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.2061296989
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.2308990775
Short name T592
Test name
Test status
Simulation time 327090872181 ps
CPU time 115.46 seconds
Started Dec 31 12:32:49 PM PST 23
Finished Dec 31 12:34:46 PM PST 23
Peak memory 200748 kb
Host smart-5d03d933-720a-47fb-99c5-fe962fc0f07e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308990775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.2308990775
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.352118650
Short name T701
Test name
Test status
Simulation time 80463996254 ps
CPU time 253.27 seconds
Started Dec 31 12:32:51 PM PST 23
Finished Dec 31 12:37:05 PM PST 23
Peak memory 201044 kb
Host smart-c464ab92-e3b2-456d-9a79-4d8390acde55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352118650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.352118650
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.3436892146
Short name T757
Test name
Test status
Simulation time 26863890283 ps
CPU time 64.45 seconds
Started Dec 31 12:32:56 PM PST 23
Finished Dec 31 12:34:02 PM PST 23
Peak memory 200584 kb
Host smart-54636cbf-659b-47bc-8bd8-3c03a083ab47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436892146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.3436892146
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.4189272613
Short name T770
Test name
Test status
Simulation time 2836800361 ps
CPU time 7.01 seconds
Started Dec 31 12:32:43 PM PST 23
Finished Dec 31 12:32:51 PM PST 23
Peak memory 200552 kb
Host smart-df4aae87-b519-4a62-921d-3923288054aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189272613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.4189272613
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.3621207853
Short name T138
Test name
Test status
Simulation time 5866507447 ps
CPU time 13.59 seconds
Started Dec 31 12:33:01 PM PST 23
Finished Dec 31 12:33:16 PM PST 23
Peak memory 200584 kb
Host smart-515ae282-e1e0-4f30-8507-95a8ed4ccfbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621207853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.3621207853
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.1389444716
Short name T186
Test name
Test status
Simulation time 282557520357 ps
CPU time 668.78 seconds
Started Dec 31 12:32:49 PM PST 23
Finished Dec 31 12:43:59 PM PST 23
Peak memory 201248 kb
Host smart-35e6b5d4-a142-4d22-9525-6ff0551e1a6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389444716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.1389444716
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.1308326124
Short name T838
Test name
Test status
Simulation time 227330338333 ps
CPU time 207.88 seconds
Started Dec 31 12:32:57 PM PST 23
Finished Dec 31 12:36:27 PM PST 23
Peak memory 209508 kb
Host smart-ef117e5a-6062-435f-b81e-a3ba32a148fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308326124 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.1308326124
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.3274235856
Short name T736
Test name
Test status
Simulation time 343786661 ps
CPU time 1.34 seconds
Started Dec 31 12:33:02 PM PST 23
Finished Dec 31 12:33:04 PM PST 23
Peak memory 200516 kb
Host smart-73214acc-2e06-4c88-b26c-e2d7c6b8202b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274235856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.3274235856
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.321278261
Short name T296
Test name
Test status
Simulation time 170449798288 ps
CPU time 28.91 seconds
Started Dec 31 12:32:56 PM PST 23
Finished Dec 31 12:33:26 PM PST 23
Peak memory 200808 kb
Host smart-5927c80c-64be-4b56-b4a1-4615ec40cec7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321278261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gati
ng.321278261
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.1478102117
Short name T288
Test name
Test status
Simulation time 166109215178 ps
CPU time 79.49 seconds
Started Dec 31 12:32:57 PM PST 23
Finished Dec 31 12:34:18 PM PST 23
Peak memory 200836 kb
Host smart-0d92daa2-0324-4f00-bc1d-21c7e5af8257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478102117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.1478102117
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.2686012831
Short name T806
Test name
Test status
Simulation time 163766571927 ps
CPU time 186.02 seconds
Started Dec 31 12:32:42 PM PST 23
Finished Dec 31 12:35:49 PM PST 23
Peak memory 200768 kb
Host smart-15903575-7a1e-4557-b45d-11d99f7fe604
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686012831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.2686012831
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.1381540726
Short name T618
Test name
Test status
Simulation time 497761864446 ps
CPU time 1140.75 seconds
Started Dec 31 12:32:43 PM PST 23
Finished Dec 31 12:51:45 PM PST 23
Peak memory 200836 kb
Host smart-769e4541-0876-4ac1-990f-fe9195bb6308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381540726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.1381540726
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.3060535979
Short name T514
Test name
Test status
Simulation time 167319737371 ps
CPU time 101.19 seconds
Started Dec 31 12:32:59 PM PST 23
Finished Dec 31 12:34:42 PM PST 23
Peak memory 200688 kb
Host smart-15cf9e6b-3886-41ad-999c-da408dfaec75
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060535979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.3060535979
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.985822629
Short name T538
Test name
Test status
Simulation time 165333162246 ps
CPU time 102.36 seconds
Started Dec 31 12:32:53 PM PST 23
Finished Dec 31 12:34:36 PM PST 23
Peak memory 200720 kb
Host smart-5c1c492d-836a-4f3d-add1-59f0e5e32244
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985822629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
adc_ctrl_filters_wakeup_fixed.985822629
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.2141715745
Short name T169
Test name
Test status
Simulation time 114655579981 ps
CPU time 573.25 seconds
Started Dec 31 12:32:50 PM PST 23
Finished Dec 31 12:42:25 PM PST 23
Peak memory 201128 kb
Host smart-48d1faa8-e567-477b-b43a-0c611ac3fefd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141715745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.2141715745
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.1759235304
Short name T484
Test name
Test status
Simulation time 30809486124 ps
CPU time 73.04 seconds
Started Dec 31 12:32:51 PM PST 23
Finished Dec 31 12:34:05 PM PST 23
Peak memory 200600 kb
Host smart-4c947c8f-ed2f-4c25-8364-2a343981c329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759235304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.1759235304
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.3480602767
Short name T418
Test name
Test status
Simulation time 2932452734 ps
CPU time 7.21 seconds
Started Dec 31 12:32:59 PM PST 23
Finished Dec 31 12:33:08 PM PST 23
Peak memory 200592 kb
Host smart-ca077765-2be7-4b8a-9ad7-ee7ede6f23fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480602767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.3480602767
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.3363941770
Short name T508
Test name
Test status
Simulation time 6135026539 ps
CPU time 5.53 seconds
Started Dec 31 12:33:00 PM PST 23
Finished Dec 31 12:33:07 PM PST 23
Peak memory 200532 kb
Host smart-b2ea68f9-a109-4e05-aa4c-3b0e37b072e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363941770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.3363941770
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.3083659845
Short name T277
Test name
Test status
Simulation time 173684830584 ps
CPU time 111.52 seconds
Started Dec 31 12:32:59 PM PST 23
Finished Dec 31 12:34:51 PM PST 23
Peak memory 209064 kb
Host smart-8483ce0b-4cd7-462e-845f-c039608218f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083659845 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.3083659845
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.1778739132
Short name T511
Test name
Test status
Simulation time 480543640 ps
CPU time 1.78 seconds
Started Dec 31 12:32:26 PM PST 23
Finished Dec 31 12:32:31 PM PST 23
Peak memory 200484 kb
Host smart-db80b161-e82d-4537-a928-466dd08b80dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778739132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.1778739132
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.3870503163
Short name T744
Test name
Test status
Simulation time 328639215997 ps
CPU time 173.45 seconds
Started Dec 31 12:32:12 PM PST 23
Finished Dec 31 12:35:06 PM PST 23
Peak memory 200796 kb
Host smart-49086584-ec54-4300-8950-d38399996589
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870503163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.3870503163
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.3925892032
Short name T632
Test name
Test status
Simulation time 319656911313 ps
CPU time 700.12 seconds
Started Dec 31 12:31:52 PM PST 23
Finished Dec 31 12:43:33 PM PST 23
Peak memory 200772 kb
Host smart-673f6eae-83ce-4f5e-817a-00199389ef20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925892032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.3925892032
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.2730422618
Short name T820
Test name
Test status
Simulation time 481992027517 ps
CPU time 97.42 seconds
Started Dec 31 12:33:32 PM PST 23
Finished Dec 31 12:35:12 PM PST 23
Peak memory 200496 kb
Host smart-30df7754-fe8b-4f90-adf0-9f1b29b32f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730422618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.2730422618
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.2210415024
Short name T808
Test name
Test status
Simulation time 165618789938 ps
CPU time 188.48 seconds
Started Dec 31 12:31:50 PM PST 23
Finished Dec 31 12:34:59 PM PST 23
Peak memory 200764 kb
Host smart-fe38cee0-84b4-40aa-9987-ad939a6eec41
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210415024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.2210415024
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.1668771577
Short name T308
Test name
Test status
Simulation time 479814997669 ps
CPU time 205.95 seconds
Started Dec 31 12:31:59 PM PST 23
Finished Dec 31 12:35:26 PM PST 23
Peak memory 200744 kb
Host smart-4d6ee528-8a78-469c-a4d1-a2428848d340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668771577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.1668771577
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.3844201597
Short name T474
Test name
Test status
Simulation time 493558892305 ps
CPU time 620.18 seconds
Started Dec 31 12:32:06 PM PST 23
Finished Dec 31 12:42:27 PM PST 23
Peak memory 200692 kb
Host smart-d26fbb03-1d7f-4923-9a2d-1975e8748dd3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844201597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.3844201597
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.4273181041
Short name T274
Test name
Test status
Simulation time 493795896747 ps
CPU time 1107.76 seconds
Started Dec 31 12:33:09 PM PST 23
Finished Dec 31 12:51:44 PM PST 23
Peak memory 200440 kb
Host smart-e16ff154-2375-4f99-9b02-2bd2a51723c9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273181041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.4273181041
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.1430776304
Short name T767
Test name
Test status
Simulation time 503699069130 ps
CPU time 578.31 seconds
Started Dec 31 12:33:12 PM PST 23
Finished Dec 31 12:42:56 PM PST 23
Peak memory 200760 kb
Host smart-fe79c955-ec96-4f25-bf7f-39bf31cb5ecd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430776304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.1430776304
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.2684914462
Short name T468
Test name
Test status
Simulation time 93635261594 ps
CPU time 346.87 seconds
Started Dec 31 12:33:35 PM PST 23
Finished Dec 31 12:39:25 PM PST 23
Peak memory 200876 kb
Host smart-299e758c-1cac-4340-bcba-7013cb7dbf34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684914462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.2684914462
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.2870453609
Short name T761
Test name
Test status
Simulation time 35441158533 ps
CPU time 77.13 seconds
Started Dec 31 12:32:10 PM PST 23
Finished Dec 31 12:33:28 PM PST 23
Peak memory 200588 kb
Host smart-39f79361-c8fa-4c31-89d3-1471268ff0d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870453609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.2870453609
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.2859201314
Short name T424
Test name
Test status
Simulation time 3266958255 ps
CPU time 8.44 seconds
Started Dec 31 12:31:53 PM PST 23
Finished Dec 31 12:32:02 PM PST 23
Peak memory 200548 kb
Host smart-9abf9e17-e424-45f4-9284-9257b5bf5268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859201314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.2859201314
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.3578181236
Short name T459
Test name
Test status
Simulation time 5995974261 ps
CPU time 4.64 seconds
Started Dec 31 12:32:54 PM PST 23
Finished Dec 31 12:33:00 PM PST 23
Peak memory 200544 kb
Host smart-22970453-fbf5-4831-a8a0-2aea527df2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578181236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.3578181236
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.230839042
Short name T530
Test name
Test status
Simulation time 493289212 ps
CPU time 0.85 seconds
Started Dec 31 12:33:05 PM PST 23
Finished Dec 31 12:33:07 PM PST 23
Peak memory 200532 kb
Host smart-7f36c2bf-e932-4cd7-bc18-69fef668dbf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230839042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.230839042
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.2924376876
Short name T466
Test name
Test status
Simulation time 164561003155 ps
CPU time 170.99 seconds
Started Dec 31 12:32:44 PM PST 23
Finished Dec 31 12:35:37 PM PST 23
Peak memory 200852 kb
Host smart-d5be5883-160b-4cc5-ac06-489c69fa45d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924376876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.2924376876
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.1716894678
Short name T641
Test name
Test status
Simulation time 330699340435 ps
CPU time 242.01 seconds
Started Dec 31 12:32:46 PM PST 23
Finished Dec 31 12:36:50 PM PST 23
Peak memory 200796 kb
Host smart-cd67d65c-5b0d-4ef1-a393-4c7b0d5a1c49
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716894678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.1716894678
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.2742797473
Short name T848
Test name
Test status
Simulation time 159897763710 ps
CPU time 118.85 seconds
Started Dec 31 12:33:00 PM PST 23
Finished Dec 31 12:35:01 PM PST 23
Peak memory 200800 kb
Host smart-230eda30-94da-46d8-a306-528b82272312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742797473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.2742797473
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.900474841
Short name T714
Test name
Test status
Simulation time 481527736371 ps
CPU time 1186.36 seconds
Started Dec 31 12:33:22 PM PST 23
Finished Dec 31 12:53:09 PM PST 23
Peak memory 200636 kb
Host smart-7ee2d514-5612-4b19-8cf5-91c7c2a48f68
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=900474841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fixe
d.900474841
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.3133096342
Short name T193
Test name
Test status
Simulation time 165849842252 ps
CPU time 378.61 seconds
Started Dec 31 12:33:22 PM PST 23
Finished Dec 31 12:39:42 PM PST 23
Peak memory 200692 kb
Host smart-9ae1b2e8-b97d-4a65-8b4c-255e0ef3258d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133096342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.3133096342
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.2583299040
Short name T823
Test name
Test status
Simulation time 161794158766 ps
CPU time 99.31 seconds
Started Dec 31 12:32:49 PM PST 23
Finished Dec 31 12:34:30 PM PST 23
Peak memory 200744 kb
Host smart-6c5ef151-bc18-410a-822e-c1e78b3dc0ea
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583299040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.2583299040
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.1125598422
Short name T426
Test name
Test status
Simulation time 23902588838 ps
CPU time 58.55 seconds
Started Dec 31 12:33:01 PM PST 23
Finished Dec 31 12:34:01 PM PST 23
Peak memory 200588 kb
Host smart-73b8ad9e-a634-4071-ad9d-bd5aebd4b0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125598422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.1125598422
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.4158565930
Short name T763
Test name
Test status
Simulation time 4995742040 ps
CPU time 11.57 seconds
Started Dec 31 12:32:58 PM PST 23
Finished Dec 31 12:33:11 PM PST 23
Peak memory 200480 kb
Host smart-bfe91c28-0510-4321-88ab-6c4bd640282f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158565930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.4158565930
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.1560422908
Short name T635
Test name
Test status
Simulation time 5982537324 ps
CPU time 14.41 seconds
Started Dec 31 12:33:15 PM PST 23
Finished Dec 31 12:33:33 PM PST 23
Peak memory 200536 kb
Host smart-5535a70c-2663-49da-b247-0e29f0ede347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560422908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.1560422908
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.3372867167
Short name T117
Test name
Test status
Simulation time 162106262134 ps
CPU time 28.78 seconds
Started Dec 31 12:32:54 PM PST 23
Finished Dec 31 12:33:24 PM PST 23
Peak memory 200684 kb
Host smart-9be60674-9866-4793-aa90-8ee00c5540fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372867167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.3372867167
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.310470005
Short name T335
Test name
Test status
Simulation time 134375637612 ps
CPU time 124.8 seconds
Started Dec 31 12:32:57 PM PST 23
Finished Dec 31 12:35:03 PM PST 23
Peak memory 209060 kb
Host smart-a99d89ae-8828-4f48-99a4-d3096e203b42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310470005 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.310470005
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.2703690502
Short name T649
Test name
Test status
Simulation time 535465659 ps
CPU time 1.17 seconds
Started Dec 31 12:33:05 PM PST 23
Finished Dec 31 12:33:07 PM PST 23
Peak memory 200476 kb
Host smart-df5dc670-ec57-4e1a-b7d0-1eaf7e205ba3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703690502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.2703690502
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.3080229487
Short name T801
Test name
Test status
Simulation time 327722867524 ps
CPU time 159.68 seconds
Started Dec 31 12:32:38 PM PST 23
Finished Dec 31 12:35:18 PM PST 23
Peak memory 200700 kb
Host smart-9e14c66c-313b-4859-9f79-dc8d0862be69
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080229487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.3080229487
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.2777915833
Short name T105
Test name
Test status
Simulation time 491266553468 ps
CPU time 307.68 seconds
Started Dec 31 12:32:46 PM PST 23
Finished Dec 31 12:37:56 PM PST 23
Peak memory 200752 kb
Host smart-653c4418-00c3-40ba-82cd-5be7f912b25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777915833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.2777915833
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.2142640559
Short name T331
Test name
Test status
Simulation time 327382389468 ps
CPU time 791.34 seconds
Started Dec 31 12:32:59 PM PST 23
Finished Dec 31 12:46:12 PM PST 23
Peak memory 201012 kb
Host smart-f9ac9532-3fbc-4b71-a7e6-afe157a27c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142640559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.2142640559
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.403448294
Short name T833
Test name
Test status
Simulation time 168993669381 ps
CPU time 105.71 seconds
Started Dec 31 12:32:55 PM PST 23
Finished Dec 31 12:34:42 PM PST 23
Peak memory 200676 kb
Host smart-4ad8fcac-242d-45d2-b258-2aa5f61920db
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=403448294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrup
t_fixed.403448294
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.833907593
Short name T235
Test name
Test status
Simulation time 324732000059 ps
CPU time 716.77 seconds
Started Dec 31 12:33:04 PM PST 23
Finished Dec 31 12:45:02 PM PST 23
Peak memory 200688 kb
Host smart-fdfe2291-29a7-4afd-a84d-2153cbb5fd23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833907593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.833907593
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.2684188971
Short name T709
Test name
Test status
Simulation time 322148558990 ps
CPU time 744.43 seconds
Started Dec 31 12:32:56 PM PST 23
Finished Dec 31 12:45:21 PM PST 23
Peak memory 200740 kb
Host smart-60c090be-1664-43f9-9571-d9cb0b7e54b4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684188971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.2684188971
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.1806675811
Short name T223
Test name
Test status
Simulation time 166498619468 ps
CPU time 105.56 seconds
Started Dec 31 12:32:47 PM PST 23
Finished Dec 31 12:34:34 PM PST 23
Peak memory 200828 kb
Host smart-4f33c340-865e-4139-8b1e-a97225ef63c1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806675811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.1806675811
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.1834576411
Short name T697
Test name
Test status
Simulation time 159103514177 ps
CPU time 197.31 seconds
Started Dec 31 12:33:05 PM PST 23
Finished Dec 31 12:36:23 PM PST 23
Peak memory 200708 kb
Host smart-c7a36037-a3d7-42f8-b3aa-a129cbdaf0cb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834576411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.1834576411
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.1008444000
Short name T179
Test name
Test status
Simulation time 89776309992 ps
CPU time 367.8 seconds
Started Dec 31 12:33:00 PM PST 23
Finished Dec 31 12:39:09 PM PST 23
Peak memory 201100 kb
Host smart-925e6048-7511-4592-8501-e46d4ff1d251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008444000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.1008444000
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.1104304505
Short name T839
Test name
Test status
Simulation time 36551140760 ps
CPU time 45.27 seconds
Started Dec 31 12:32:58 PM PST 23
Finished Dec 31 12:33:44 PM PST 23
Peak memory 200548 kb
Host smart-43dada18-3dcd-4007-9181-9259281d80da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104304505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.1104304505
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.2984407226
Short name T794
Test name
Test status
Simulation time 4062908964 ps
CPU time 3.03 seconds
Started Dec 31 12:33:00 PM PST 23
Finished Dec 31 12:33:04 PM PST 23
Peak memory 200596 kb
Host smart-d9cf4759-13ab-4c4e-8ba1-d4b6f57f33be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984407226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.2984407226
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.3785390408
Short name T529
Test name
Test status
Simulation time 5788609469 ps
CPU time 14.9 seconds
Started Dec 31 12:32:50 PM PST 23
Finished Dec 31 12:33:06 PM PST 23
Peak memory 200540 kb
Host smart-b772d33c-bc99-4166-9fa3-8a694b04fdfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785390408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.3785390408
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.3829477197
Short name T209
Test name
Test status
Simulation time 493784572842 ps
CPU time 1188.13 seconds
Started Dec 31 12:33:10 PM PST 23
Finished Dec 31 12:53:04 PM PST 23
Peak memory 200872 kb
Host smart-d993baf2-8f36-48c6-8788-74f9ce45a1cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829477197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.3829477197
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.38550047
Short name T656
Test name
Test status
Simulation time 335042984961 ps
CPU time 523.78 seconds
Started Dec 31 12:32:55 PM PST 23
Finished Dec 31 12:41:39 PM PST 23
Peak memory 209512 kb
Host smart-dbfad315-2438-4d6a-bf68-491abf7e81fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38550047 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.38550047
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.561564955
Short name T623
Test name
Test status
Simulation time 306592232 ps
CPU time 0.97 seconds
Started Dec 31 12:33:05 PM PST 23
Finished Dec 31 12:33:11 PM PST 23
Peak memory 200512 kb
Host smart-016793f0-c699-4564-af67-6f7952725148
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561564955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.561564955
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.45329086
Short name T749
Test name
Test status
Simulation time 500879720876 ps
CPU time 156.51 seconds
Started Dec 31 12:33:00 PM PST 23
Finished Dec 31 12:35:39 PM PST 23
Peak memory 200812 kb
Host smart-1260364c-f8c4-4f9e-bb02-e1bfa063118f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45329086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.45329086
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.424768871
Short name T132
Test name
Test status
Simulation time 496933521117 ps
CPU time 186.98 seconds
Started Dec 31 12:33:00 PM PST 23
Finished Dec 31 12:36:09 PM PST 23
Peak memory 200740 kb
Host smart-fdcd82a6-434c-4d6d-971c-ede11c556bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424768871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.424768871
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.372790470
Short name T734
Test name
Test status
Simulation time 326874681197 ps
CPU time 137.14 seconds
Started Dec 31 12:32:56 PM PST 23
Finished Dec 31 12:35:15 PM PST 23
Peak memory 200764 kb
Host smart-42ba2072-9619-45e8-9a85-230bb80355f8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=372790470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrup
t_fixed.372790470
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.4254393183
Short name T328
Test name
Test status
Simulation time 485466206166 ps
CPU time 588.63 seconds
Started Dec 31 12:32:52 PM PST 23
Finished Dec 31 12:42:41 PM PST 23
Peak memory 200724 kb
Host smart-f44bbd9e-8f0a-418d-bd6e-dc7183354196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254393183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.4254393183
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.1029360249
Short name T720
Test name
Test status
Simulation time 494688883553 ps
CPU time 296.79 seconds
Started Dec 31 12:32:53 PM PST 23
Finished Dec 31 12:37:51 PM PST 23
Peak memory 200664 kb
Host smart-e37eb061-f53d-4204-b9af-913573458a2c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029360249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.1029360249
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.511397226
Short name T607
Test name
Test status
Simulation time 492555972949 ps
CPU time 561.69 seconds
Started Dec 31 12:33:00 PM PST 23
Finished Dec 31 12:42:23 PM PST 23
Peak memory 200792 kb
Host smart-99f7a851-dae8-40a4-874e-46a69e796225
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511397226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
adc_ctrl_filters_wakeup_fixed.511397226
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.685432096
Short name T17
Test name
Test status
Simulation time 114260618718 ps
CPU time 471.32 seconds
Started Dec 31 12:33:01 PM PST 23
Finished Dec 31 12:40:54 PM PST 23
Peak memory 201160 kb
Host smart-c35f27e2-3441-4a6a-a31d-76facd7932ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685432096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.685432096
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.894441333
Short name T555
Test name
Test status
Simulation time 46695771913 ps
CPU time 54.17 seconds
Started Dec 31 12:33:09 PM PST 23
Finished Dec 31 12:34:05 PM PST 23
Peak memory 200472 kb
Host smart-72ce36e8-38e5-4feb-8dbd-68db381a6432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894441333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.894441333
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.2705139519
Short name T504
Test name
Test status
Simulation time 3093790788 ps
CPU time 2.41 seconds
Started Dec 31 12:33:19 PM PST 23
Finished Dec 31 12:33:24 PM PST 23
Peak memory 200588 kb
Host smart-c810cfae-314d-419d-8c0e-3d443da6449b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705139519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.2705139519
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.762205791
Short name T588
Test name
Test status
Simulation time 6376043381 ps
CPU time 4.18 seconds
Started Dec 31 12:32:55 PM PST 23
Finished Dec 31 12:33:01 PM PST 23
Peak memory 200460 kb
Host smart-4edc6c53-3d5a-4304-ab22-75c02075353e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762205791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.762205791
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.128246242
Short name T253
Test name
Test status
Simulation time 77965228551 ps
CPU time 69.74 seconds
Started Dec 31 12:32:59 PM PST 23
Finished Dec 31 12:34:15 PM PST 23
Peak memory 209044 kb
Host smart-7109f6e5-e83f-48ce-a316-85453b3fbdfd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128246242 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.128246242
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.2577805443
Short name T457
Test name
Test status
Simulation time 318628586 ps
CPU time 0.8 seconds
Started Dec 31 12:32:58 PM PST 23
Finished Dec 31 12:33:03 PM PST 23
Peak memory 200520 kb
Host smart-77756a66-b63b-4b74-a489-997451cd6414
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577805443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.2577805443
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.804714179
Short name T828
Test name
Test status
Simulation time 489137121875 ps
CPU time 287.21 seconds
Started Dec 31 12:32:49 PM PST 23
Finished Dec 31 12:37:37 PM PST 23
Peak memory 200696 kb
Host smart-5b872e9d-3fd1-4c63-87b4-6648b37989d4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804714179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gati
ng.804714179
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.3348179237
Short name T723
Test name
Test status
Simulation time 165817742847 ps
CPU time 363.46 seconds
Started Dec 31 12:32:55 PM PST 23
Finished Dec 31 12:39:06 PM PST 23
Peak memory 200688 kb
Host smart-418f4a72-0d30-4445-b75f-3225f5a7b595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348179237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.3348179237
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.1476485333
Short name T122
Test name
Test status
Simulation time 161834260166 ps
CPU time 195.04 seconds
Started Dec 31 12:32:52 PM PST 23
Finished Dec 31 12:36:08 PM PST 23
Peak memory 200832 kb
Host smart-30059991-bbe8-4635-8053-7a7b78540d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476485333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.1476485333
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.4009168892
Short name T575
Test name
Test status
Simulation time 327841931546 ps
CPU time 731.57 seconds
Started Dec 31 12:33:00 PM PST 23
Finished Dec 31 12:45:13 PM PST 23
Peak memory 200684 kb
Host smart-a7414032-d8c8-4e55-acd9-f80948f2e906
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009168892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.4009168892
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.3472225884
Short name T584
Test name
Test status
Simulation time 172378170070 ps
CPU time 76.04 seconds
Started Dec 31 12:32:53 PM PST 23
Finished Dec 31 12:34:10 PM PST 23
Peak memory 200832 kb
Host smart-04ce5d4a-9d66-46c5-b06c-90f621f2567c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472225884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.3472225884
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.1567817570
Short name T754
Test name
Test status
Simulation time 337059293596 ps
CPU time 192.98 seconds
Started Dec 31 12:32:44 PM PST 23
Finished Dec 31 12:36:00 PM PST 23
Peak memory 200700 kb
Host smart-21e9c05a-db83-4f6b-93f3-b1672250498d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567817570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.1567817570
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.3549899824
Short name T91
Test name
Test status
Simulation time 330665850290 ps
CPU time 122.96 seconds
Started Dec 31 12:32:42 PM PST 23
Finished Dec 31 12:34:46 PM PST 23
Peak memory 200676 kb
Host smart-c29021a7-f8a5-4e8b-b1a1-32ba971a9988
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549899824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.3549899824
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.3252572746
Short name T810
Test name
Test status
Simulation time 497794470929 ps
CPU time 572.49 seconds
Started Dec 31 12:32:56 PM PST 23
Finished Dec 31 12:42:30 PM PST 23
Peak memory 200708 kb
Host smart-9b7f5626-7eaa-4222-8540-fcabdce56ed0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252572746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.3252572746
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.1802857214
Short name T811
Test name
Test status
Simulation time 119267745104 ps
CPU time 670.53 seconds
Started Dec 31 12:33:07 PM PST 23
Finished Dec 31 12:44:20 PM PST 23
Peak memory 201240 kb
Host smart-7024500b-8f00-495f-a514-7a670f729817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802857214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.1802857214
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.3952876318
Short name T850
Test name
Test status
Simulation time 47116844803 ps
CPU time 28.85 seconds
Started Dec 31 12:33:21 PM PST 23
Finished Dec 31 12:33:51 PM PST 23
Peak memory 200484 kb
Host smart-b408d29e-1aef-4193-8c99-df9ebf90e74e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952876318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.3952876318
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.970739816
Short name T422
Test name
Test status
Simulation time 5290451816 ps
CPU time 3.7 seconds
Started Dec 31 12:32:54 PM PST 23
Finished Dec 31 12:32:59 PM PST 23
Peak memory 200580 kb
Host smart-91f330e3-b045-496f-946a-d87dab8a7437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970739816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.970739816
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.3892702413
Short name T612
Test name
Test status
Simulation time 5715176779 ps
CPU time 3.86 seconds
Started Dec 31 12:32:53 PM PST 23
Finished Dec 31 12:32:58 PM PST 23
Peak memory 200540 kb
Host smart-eeb8ca09-e014-4cd5-86a7-cee5c543f13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892702413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.3892702413
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.2943682917
Short name T24
Test name
Test status
Simulation time 69188717353 ps
CPU time 175.04 seconds
Started Dec 31 12:32:46 PM PST 23
Finished Dec 31 12:35:44 PM PST 23
Peak memory 209460 kb
Host smart-176275c2-2f14-46f7-9aed-e57f4693c801
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943682917 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.2943682917
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.1664783805
Short name T458
Test name
Test status
Simulation time 338955531 ps
CPU time 0.79 seconds
Started Dec 31 12:33:05 PM PST 23
Finished Dec 31 12:33:08 PM PST 23
Peak memory 200496 kb
Host smart-a4751ce6-f013-4ec2-83f8-b6461bd1fdaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664783805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.1664783805
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.2748289441
Short name T280
Test name
Test status
Simulation time 166222900007 ps
CPU time 36.5 seconds
Started Dec 31 12:33:12 PM PST 23
Finished Dec 31 12:33:54 PM PST 23
Peak memory 200784 kb
Host smart-f07fc68e-cb7e-4fd3-81e4-b7c3b29e7b50
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748289441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.2748289441
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.1560706546
Short name T721
Test name
Test status
Simulation time 325943535802 ps
CPU time 435.37 seconds
Started Dec 31 12:32:57 PM PST 23
Finished Dec 31 12:40:14 PM PST 23
Peak memory 200740 kb
Host smart-c6f26129-e398-46eb-bed7-1e0bbe2d5fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560706546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.1560706546
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.1024478314
Short name T782
Test name
Test status
Simulation time 326216145045 ps
CPU time 743.85 seconds
Started Dec 31 12:32:53 PM PST 23
Finished Dec 31 12:45:18 PM PST 23
Peak memory 200780 kb
Host smart-bfdae203-cefc-4bca-91ac-4f02976f79a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024478314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.1024478314
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.1726374980
Short name T494
Test name
Test status
Simulation time 327316852729 ps
CPU time 353.69 seconds
Started Dec 31 12:33:00 PM PST 23
Finished Dec 31 12:38:56 PM PST 23
Peak memory 200696 kb
Host smart-e352a9ea-4c19-4bff-a56d-d2d6a2fd37c8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726374980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.1726374980
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.3724828911
Short name T698
Test name
Test status
Simulation time 321991939331 ps
CPU time 107.62 seconds
Started Dec 31 12:33:12 PM PST 23
Finished Dec 31 12:35:05 PM PST 23
Peak memory 200780 kb
Host smart-486b6f87-c00d-44f2-9db3-b2077d1db336
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724828911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.3724828911
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.1588578851
Short name T554
Test name
Test status
Simulation time 167040214016 ps
CPU time 167.67 seconds
Started Dec 31 12:32:59 PM PST 23
Finished Dec 31 12:35:48 PM PST 23
Peak memory 200744 kb
Host smart-a7968d82-6648-4bbc-858d-ed23c7657e9c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588578851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.1588578851
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.827623959
Short name T729
Test name
Test status
Simulation time 124921382739 ps
CPU time 635.06 seconds
Started Dec 31 12:32:54 PM PST 23
Finished Dec 31 12:43:30 PM PST 23
Peak memory 201052 kb
Host smart-8568c435-7ffb-4803-9e4b-887c2849a427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827623959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.827623959
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.2521053890
Short name T670
Test name
Test status
Simulation time 29024485702 ps
CPU time 61.69 seconds
Started Dec 31 12:32:55 PM PST 23
Finished Dec 31 12:33:58 PM PST 23
Peak memory 200608 kb
Host smart-762786ec-242f-4d0a-8feb-d200715646a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521053890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.2521053890
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.2057415192
Short name T552
Test name
Test status
Simulation time 5015315500 ps
CPU time 4.04 seconds
Started Dec 31 12:32:59 PM PST 23
Finished Dec 31 12:33:04 PM PST 23
Peak memory 200608 kb
Host smart-37e9028e-03ee-4218-b211-ee99d3159da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057415192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.2057415192
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.1266021029
Short name T449
Test name
Test status
Simulation time 6032863140 ps
CPU time 4.36 seconds
Started Dec 31 12:33:11 PM PST 23
Finished Dec 31 12:33:22 PM PST 23
Peak memory 200544 kb
Host smart-409da7ee-6900-4e34-afa0-5bcd8099588c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266021029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.1266021029
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.1635191284
Short name T610
Test name
Test status
Simulation time 320257676996 ps
CPU time 1062.13 seconds
Started Dec 31 12:33:07 PM PST 23
Finished Dec 31 12:50:52 PM PST 23
Peak memory 201144 kb
Host smart-12decac4-6291-4e96-b01c-06573ecb2efc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635191284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.1635191284
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.2205769193
Short name T513
Test name
Test status
Simulation time 463475634 ps
CPU time 0.98 seconds
Started Dec 31 12:33:01 PM PST 23
Finished Dec 31 12:33:03 PM PST 23
Peak memory 200532 kb
Host smart-6f8d2447-f63e-4dad-a8d3-e8c0a231949d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205769193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.2205769193
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.1663328535
Short name T150
Test name
Test status
Simulation time 164343145525 ps
CPU time 199.27 seconds
Started Dec 31 12:32:59 PM PST 23
Finished Dec 31 12:36:19 PM PST 23
Peak memory 200740 kb
Host smart-f6c41689-5c5e-4709-b3da-57360af71e7f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663328535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.1663328535
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.4027028222
Short name T206
Test name
Test status
Simulation time 189553562818 ps
CPU time 109.45 seconds
Started Dec 31 12:33:09 PM PST 23
Finished Dec 31 12:35:05 PM PST 23
Peak memory 200752 kb
Host smart-73487a08-c1fe-4578-8024-25ec4666f48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027028222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.4027028222
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.3353259928
Short name T265
Test name
Test status
Simulation time 164059456484 ps
CPU time 112.46 seconds
Started Dec 31 12:33:08 PM PST 23
Finished Dec 31 12:35:03 PM PST 23
Peak memory 200852 kb
Host smart-3ebca9af-8109-4fda-bab4-f5815b8adfd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353259928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.3353259928
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.3804045673
Short name T778
Test name
Test status
Simulation time 486931366272 ps
CPU time 1036.1 seconds
Started Dec 31 12:32:56 PM PST 23
Finished Dec 31 12:50:14 PM PST 23
Peak memory 200708 kb
Host smart-271a5afc-5dda-480d-93ec-8b5dbed839f3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804045673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.3804045673
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.2233388592
Short name T199
Test name
Test status
Simulation time 329424619851 ps
CPU time 772.69 seconds
Started Dec 31 12:33:01 PM PST 23
Finished Dec 31 12:45:55 PM PST 23
Peak memory 200756 kb
Host smart-f315599b-d7e6-47c1-ba17-5d6d48243168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233388592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.2233388592
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.586858593
Short name T650
Test name
Test status
Simulation time 490739497866 ps
CPU time 1156.9 seconds
Started Dec 31 12:33:05 PM PST 23
Finished Dec 31 12:52:23 PM PST 23
Peak memory 200732 kb
Host smart-cee110d6-9a13-4fa5-8eff-d88d9c00817f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=586858593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fixe
d.586858593
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.3911323418
Short name T614
Test name
Test status
Simulation time 163486258127 ps
CPU time 384.36 seconds
Started Dec 31 12:32:57 PM PST 23
Finished Dec 31 12:39:22 PM PST 23
Peak memory 200784 kb
Host smart-765c366f-e854-4b57-b0bb-6ad06e87a6b1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911323418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.3911323418
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.449314052
Short name T551
Test name
Test status
Simulation time 487441222865 ps
CPU time 1073.78 seconds
Started Dec 31 12:33:18 PM PST 23
Finished Dec 31 12:51:15 PM PST 23
Peak memory 200740 kb
Host smart-55ec5891-f009-4bec-a993-f903ba9083b7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449314052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
adc_ctrl_filters_wakeup_fixed.449314052
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.211338382
Short name T727
Test name
Test status
Simulation time 115745379913 ps
CPU time 587.96 seconds
Started Dec 31 12:33:10 PM PST 23
Finished Dec 31 12:43:05 PM PST 23
Peak memory 201212 kb
Host smart-a577c5d3-1aaf-4d1b-93d3-3454ba811b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211338382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.211338382
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.2449979860
Short name T675
Test name
Test status
Simulation time 41743429593 ps
CPU time 22.53 seconds
Started Dec 31 12:33:00 PM PST 23
Finished Dec 31 12:33:24 PM PST 23
Peak memory 200508 kb
Host smart-9e7b8409-2054-4351-b3a9-13d281e63faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449979860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.2449979860
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.1892560823
Short name T596
Test name
Test status
Simulation time 5118371867 ps
CPU time 2.44 seconds
Started Dec 31 12:33:32 PM PST 23
Finished Dec 31 12:33:40 PM PST 23
Peak memory 200576 kb
Host smart-937db8d3-23ce-43d9-8533-6d99a5af7f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892560823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.1892560823
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.2793463195
Short name T438
Test name
Test status
Simulation time 5820367394 ps
CPU time 15.78 seconds
Started Dec 31 12:33:05 PM PST 23
Finished Dec 31 12:33:22 PM PST 23
Peak memory 200532 kb
Host smart-a7eef35f-05a2-4ca3-8a6b-7a9548f4f750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793463195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.2793463195
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.2365194744
Short name T483
Test name
Test status
Simulation time 5747647634 ps
CPU time 12.95 seconds
Started Dec 31 12:33:04 PM PST 23
Finished Dec 31 12:33:19 PM PST 23
Peak memory 200516 kb
Host smart-789f74a6-5a61-44c4-9705-40d709db9119
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365194744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.2365194744
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.2398639644
Short name T337
Test name
Test status
Simulation time 173005216409 ps
CPU time 51.15 seconds
Started Dec 31 12:32:55 PM PST 23
Finished Dec 31 12:33:48 PM PST 23
Peak memory 209064 kb
Host smart-2585bc97-82fb-4c11-820d-fb669dd55709
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398639644 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.2398639644
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.3380655978
Short name T531
Test name
Test status
Simulation time 290326364 ps
CPU time 0.9 seconds
Started Dec 31 12:32:55 PM PST 23
Finished Dec 31 12:32:57 PM PST 23
Peak memory 200540 kb
Host smart-7adf1978-0bb0-4724-8e21-1bcbd1ccb145
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380655978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.3380655978
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.372474833
Short name T207
Test name
Test status
Simulation time 179162997991 ps
CPU time 432.69 seconds
Started Dec 31 12:33:02 PM PST 23
Finished Dec 31 12:40:23 PM PST 23
Peak memory 200024 kb
Host smart-97391817-a97c-404a-b376-80d8e26a11ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372474833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.372474833
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.551528669
Short name T201
Test name
Test status
Simulation time 170866252350 ps
CPU time 221.88 seconds
Started Dec 31 12:33:43 PM PST 23
Finished Dec 31 12:37:26 PM PST 23
Peak memory 200676 kb
Host smart-72c316b6-bd25-4bac-a6b6-3be781eeba41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551528669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.551528669
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.593460358
Short name T819
Test name
Test status
Simulation time 323638695794 ps
CPU time 387.6 seconds
Started Dec 31 12:33:12 PM PST 23
Finished Dec 31 12:39:45 PM PST 23
Peak memory 200736 kb
Host smart-c90571b5-db65-453c-b918-7b4ffdea138f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=593460358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrup
t_fixed.593460358
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.4077769038
Short name T464
Test name
Test status
Simulation time 160636335943 ps
CPU time 308.06 seconds
Started Dec 31 12:33:04 PM PST 23
Finished Dec 31 12:38:14 PM PST 23
Peak memory 200676 kb
Host smart-6ae05b5e-a804-4c48-9744-67664fd38eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077769038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.4077769038
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.3444048772
Short name T863
Test name
Test status
Simulation time 329638476906 ps
CPU time 121.75 seconds
Started Dec 31 12:33:05 PM PST 23
Finished Dec 31 12:35:08 PM PST 23
Peak memory 200860 kb
Host smart-6f219606-7bcb-4953-8ec0-4aff23e1c638
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444048772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.3444048772
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.1425148069
Short name T613
Test name
Test status
Simulation time 164383172090 ps
CPU time 98.36 seconds
Started Dec 31 12:33:09 PM PST 23
Finished Dec 31 12:34:54 PM PST 23
Peak memory 200704 kb
Host smart-59a5958a-b3e8-48b0-9418-9d07bb02d560
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425148069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.1425148069
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.4050726004
Short name T577
Test name
Test status
Simulation time 167656224617 ps
CPU time 50.86 seconds
Started Dec 31 12:32:55 PM PST 23
Finished Dec 31 12:33:47 PM PST 23
Peak memory 200676 kb
Host smart-5a04a149-fa43-49ba-9b5c-87361a8bb16e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050726004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.4050726004
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.124686881
Short name T180
Test name
Test status
Simulation time 131395148019 ps
CPU time 551.58 seconds
Started Dec 31 12:33:26 PM PST 23
Finished Dec 31 12:42:45 PM PST 23
Peak memory 201264 kb
Host smart-1031ba46-efea-4147-a4df-58bd0d2b96a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124686881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.124686881
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.3289131777
Short name T673
Test name
Test status
Simulation time 32414831800 ps
CPU time 73.02 seconds
Started Dec 31 12:33:32 PM PST 23
Finished Dec 31 12:34:50 PM PST 23
Peak memory 200528 kb
Host smart-9473cb69-12f5-477d-9e67-e5835cb30067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289131777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.3289131777
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.1973135250
Short name T617
Test name
Test status
Simulation time 4962894670 ps
CPU time 10.86 seconds
Started Dec 31 12:33:23 PM PST 23
Finished Dec 31 12:33:35 PM PST 23
Peak memory 200604 kb
Host smart-3d3402c3-abe4-4e71-859c-709f1fa15ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973135250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.1973135250
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.4106318677
Short name T416
Test name
Test status
Simulation time 6064125573 ps
CPU time 14.54 seconds
Started Dec 31 12:32:55 PM PST 23
Finished Dec 31 12:33:11 PM PST 23
Peak memory 200452 kb
Host smart-c31d079d-79ef-4ca7-b2e1-f8d3d3695dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106318677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.4106318677
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.984209963
Short name T332
Test name
Test status
Simulation time 577201248081 ps
CPU time 1468.97 seconds
Started Dec 31 12:33:11 PM PST 23
Finished Dec 31 12:57:47 PM PST 23
Peak memory 211200 kb
Host smart-e8b52099-1056-4aa1-9db5-3e5217030702
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984209963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all.
984209963
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.2113277288
Short name T256
Test name
Test status
Simulation time 29597551629 ps
CPU time 60.38 seconds
Started Dec 31 12:33:06 PM PST 23
Finished Dec 31 12:34:09 PM PST 23
Peak memory 209348 kb
Host smart-6c43c1b0-13c6-42df-87fc-c80b4518ade3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113277288 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.2113277288
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.3038103417
Short name T654
Test name
Test status
Simulation time 293213236 ps
CPU time 0.9 seconds
Started Dec 31 12:33:28 PM PST 23
Finished Dec 31 12:33:34 PM PST 23
Peak memory 200496 kb
Host smart-a9aba813-22a8-412e-a61d-22d9de91bb44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038103417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.3038103417
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.1583667613
Short name T854
Test name
Test status
Simulation time 489645881194 ps
CPU time 469.16 seconds
Started Dec 31 12:33:02 PM PST 23
Finished Dec 31 12:40:59 PM PST 23
Peak memory 200748 kb
Host smart-e51f188b-abf4-4651-9d41-b3a2b64667c9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583667613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.1583667613
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.1638316858
Short name T683
Test name
Test status
Simulation time 165546800579 ps
CPU time 382.45 seconds
Started Dec 31 12:33:19 PM PST 23
Finished Dec 31 12:39:44 PM PST 23
Peak memory 200792 kb
Host smart-ca25eb6d-d74c-4acd-82d1-5b3fdfa2b50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638316858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.1638316858
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.1828127929
Short name T628
Test name
Test status
Simulation time 498416920142 ps
CPU time 585.25 seconds
Started Dec 31 12:33:07 PM PST 23
Finished Dec 31 12:42:55 PM PST 23
Peak memory 200836 kb
Host smart-0ad531be-d17c-41a3-9529-18f54c0d0632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828127929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.1828127929
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.2865900368
Short name T137
Test name
Test status
Simulation time 164508388697 ps
CPU time 99.49 seconds
Started Dec 31 12:33:23 PM PST 23
Finished Dec 31 12:35:04 PM PST 23
Peak memory 200648 kb
Host smart-3b6dc04c-5a2a-49c4-b5d2-2150fe272a68
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865900368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.2865900368
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.3377694465
Short name T88
Test name
Test status
Simulation time 491837126951 ps
CPU time 1000.52 seconds
Started Dec 31 12:32:56 PM PST 23
Finished Dec 31 12:49:38 PM PST 23
Peak memory 200724 kb
Host smart-c02cf0e8-396a-47ac-ab2e-322ba39cb23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377694465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.3377694465
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.1753541241
Short name T470
Test name
Test status
Simulation time 333815167457 ps
CPU time 200.19 seconds
Started Dec 31 12:33:19 PM PST 23
Finished Dec 31 12:36:42 PM PST 23
Peak memory 200800 kb
Host smart-adb033cd-b46f-49a1-a42a-f67dfda9d98a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753541241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.1753541241
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.4099388995
Short name T104
Test name
Test status
Simulation time 333781788196 ps
CPU time 378.95 seconds
Started Dec 31 12:33:06 PM PST 23
Finished Dec 31 12:39:26 PM PST 23
Peak memory 200684 kb
Host smart-fc8faf66-5d48-465e-bd98-c9dc53ab14d5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099388995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.4099388995
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.2623281243
Short name T536
Test name
Test status
Simulation time 498003777197 ps
CPU time 1199.23 seconds
Started Dec 31 12:33:18 PM PST 23
Finished Dec 31 12:53:21 PM PST 23
Peak memory 200736 kb
Host smart-50672be6-f50a-4a7f-b2f1-e746ccb7a1d4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623281243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.2623281243
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.437565252
Short name T580
Test name
Test status
Simulation time 74625957893 ps
CPU time 423.88 seconds
Started Dec 31 12:33:14 PM PST 23
Finished Dec 31 12:40:22 PM PST 23
Peak memory 201136 kb
Host smart-9840c134-628d-4816-8ca5-b69d7582e7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437565252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.437565252
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.3453477974
Short name T434
Test name
Test status
Simulation time 23797261563 ps
CPU time 54.43 seconds
Started Dec 31 12:33:19 PM PST 23
Finished Dec 31 12:34:16 PM PST 23
Peak memory 200576 kb
Host smart-eeeaa14f-c495-49ff-be8c-bfcf098eeec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453477974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.3453477974
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.2526396009
Short name T172
Test name
Test status
Simulation time 3906755806 ps
CPU time 5.19 seconds
Started Dec 31 12:33:32 PM PST 23
Finished Dec 31 12:33:42 PM PST 23
Peak memory 200608 kb
Host smart-807d2b7f-31a3-4d19-87f6-6beca0a9f2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526396009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.2526396009
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.2525935029
Short name T862
Test name
Test status
Simulation time 6117719051 ps
CPU time 15.58 seconds
Started Dec 31 12:33:00 PM PST 23
Finished Dec 31 12:33:17 PM PST 23
Peak memory 200616 kb
Host smart-de45e7a1-27d1-4939-a7c8-fb226a9efe3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525935029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.2525935029
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.1709822765
Short name T626
Test name
Test status
Simulation time 329949547729 ps
CPU time 727.04 seconds
Started Dec 31 12:33:22 PM PST 23
Finished Dec 31 12:45:30 PM PST 23
Peak memory 200712 kb
Host smart-8a5642c2-8731-4311-8f53-d08c3b19a7c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709822765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.1709822765
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.2940179955
Short name T535
Test name
Test status
Simulation time 57731838539 ps
CPU time 102.8 seconds
Started Dec 31 12:33:06 PM PST 23
Finished Dec 31 12:34:51 PM PST 23
Peak memory 209488 kb
Host smart-dd0742c8-ddf3-4db1-bc62-747c7fc0d097
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940179955 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.2940179955
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.211829566
Short name T700
Test name
Test status
Simulation time 388705906 ps
CPU time 0.81 seconds
Started Dec 31 12:33:27 PM PST 23
Finished Dec 31 12:33:34 PM PST 23
Peak memory 200540 kb
Host smart-6ec81ea8-1e35-43e7-a6db-b7036e085a42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211829566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.211829566
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.952162105
Short name T100
Test name
Test status
Simulation time 488574997639 ps
CPU time 246.16 seconds
Started Dec 31 12:33:02 PM PST 23
Finished Dec 31 12:37:09 PM PST 23
Peak memory 200704 kb
Host smart-7183e3d9-b062-4bd3-87f5-6c2c39dcb874
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952162105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gati
ng.952162105
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.1735652455
Short name T515
Test name
Test status
Simulation time 163240053546 ps
CPU time 374.57 seconds
Started Dec 31 12:33:01 PM PST 23
Finished Dec 31 12:39:17 PM PST 23
Peak memory 200848 kb
Host smart-9bf62f65-af3e-41ad-96ff-8e6b25f0f89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735652455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.1735652455
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.899427661
Short name T292
Test name
Test status
Simulation time 333234630034 ps
CPU time 823.08 seconds
Started Dec 31 12:33:03 PM PST 23
Finished Dec 31 12:46:47 PM PST 23
Peak memory 200696 kb
Host smart-54292711-cb26-48ea-ad22-16c5b4c5d139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899427661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.899427661
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.3975070615
Short name T489
Test name
Test status
Simulation time 325738930090 ps
CPU time 166.7 seconds
Started Dec 31 12:33:18 PM PST 23
Finished Dec 31 12:36:08 PM PST 23
Peak memory 200756 kb
Host smart-f132bfec-8f91-4a38-8e3b-d1957346168a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975070615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.3975070615
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.3142167723
Short name T677
Test name
Test status
Simulation time 322847932679 ps
CPU time 202.81 seconds
Started Dec 31 12:33:37 PM PST 23
Finished Dec 31 12:37:02 PM PST 23
Peak memory 200716 kb
Host smart-ac95ac75-cd1a-47ba-946a-4861f2f0dc2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142167723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.3142167723
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.4057724831
Short name T678
Test name
Test status
Simulation time 321912809725 ps
CPU time 198.69 seconds
Started Dec 31 12:33:29 PM PST 23
Finished Dec 31 12:36:52 PM PST 23
Peak memory 200728 kb
Host smart-8e6f9862-9550-4d0f-93a6-3172299cbb2f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057724831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.4057724831
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.3331578656
Short name T310
Test name
Test status
Simulation time 167078561432 ps
CPU time 99.59 seconds
Started Dec 31 12:33:15 PM PST 23
Finished Dec 31 12:34:58 PM PST 23
Peak memory 200760 kb
Host smart-4872bf10-34e6-4eb4-8614-0d7bd2ebcfa1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331578656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.3331578656
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.3185064175
Short name T480
Test name
Test status
Simulation time 335378373090 ps
CPU time 251.37 seconds
Started Dec 31 12:33:00 PM PST 23
Finished Dec 31 12:37:13 PM PST 23
Peak memory 200712 kb
Host smart-7e48e897-738b-4beb-80a1-5ee42e815c9c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185064175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.3185064175
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.377117419
Short name T80
Test name
Test status
Simulation time 71947766300 ps
CPU time 230.01 seconds
Started Dec 31 12:33:12 PM PST 23
Finished Dec 31 12:37:08 PM PST 23
Peak memory 201232 kb
Host smart-1deb53ea-b2fa-48da-9e36-0f93e9e4aebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377117419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.377117419
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.301395514
Short name T176
Test name
Test status
Simulation time 27479508172 ps
CPU time 12.46 seconds
Started Dec 31 12:33:11 PM PST 23
Finished Dec 31 12:33:30 PM PST 23
Peak memory 200588 kb
Host smart-7186b51b-3254-4b43-8862-ce7aa71dd2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301395514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.301395514
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.520286532
Short name T488
Test name
Test status
Simulation time 4635298855 ps
CPU time 3.81 seconds
Started Dec 31 12:33:09 PM PST 23
Finished Dec 31 12:33:14 PM PST 23
Peak memory 200868 kb
Host smart-71382a7a-5e26-4d52-a2d3-9c9ddab650d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520286532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.520286532
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.3408242563
Short name T708
Test name
Test status
Simulation time 5809399486 ps
CPU time 4.41 seconds
Started Dec 31 12:33:22 PM PST 23
Finished Dec 31 12:33:27 PM PST 23
Peak memory 200600 kb
Host smart-c36ebccf-150f-446c-8525-0c41637dcc7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408242563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.3408242563
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.78750385
Short name T775
Test name
Test status
Simulation time 122758334281 ps
CPU time 353.68 seconds
Started Dec 31 12:33:28 PM PST 23
Finished Dec 31 12:39:27 PM PST 23
Peak memory 217260 kb
Host smart-bc16146b-0d30-42fa-8474-40afe330dc4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78750385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all.78750385
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.3878840538
Short name T477
Test name
Test status
Simulation time 25043254582 ps
CPU time 44.95 seconds
Started Dec 31 12:33:38 PM PST 23
Finished Dec 31 12:34:24 PM PST 23
Peak memory 200804 kb
Host smart-1bac6d09-8ffd-4937-a27a-0bdf85a24a8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878840538 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.3878840538
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.1056488603
Short name T429
Test name
Test status
Simulation time 291538490 ps
CPU time 1.01 seconds
Started Dec 31 12:33:20 PM PST 23
Finished Dec 31 12:33:23 PM PST 23
Peak memory 200508 kb
Host smart-84378908-5c70-4ee6-ac53-f52d9ea74eb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056488603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.1056488603
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.3179563862
Short name T681
Test name
Test status
Simulation time 163972376779 ps
CPU time 101.34 seconds
Started Dec 31 12:33:10 PM PST 23
Finished Dec 31 12:34:57 PM PST 23
Peak memory 200744 kb
Host smart-52433026-413b-4bff-a3c7-9fad138830d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179563862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.3179563862
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.2517458998
Short name T287
Test name
Test status
Simulation time 493963821831 ps
CPU time 587.94 seconds
Started Dec 31 12:33:18 PM PST 23
Finished Dec 31 12:43:09 PM PST 23
Peak memory 200772 kb
Host smart-b2649f19-8a9a-4d3a-aa0d-c1b4565f9869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517458998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.2517458998
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.3734138774
Short name T630
Test name
Test status
Simulation time 164689226472 ps
CPU time 107.29 seconds
Started Dec 31 12:33:15 PM PST 23
Finished Dec 31 12:35:06 PM PST 23
Peak memory 200680 kb
Host smart-300b590a-a7e2-40d1-9919-ac21bf212e2f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734138774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.3734138774
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.1935578781
Short name T139
Test name
Test status
Simulation time 335213877337 ps
CPU time 198.78 seconds
Started Dec 31 12:33:36 PM PST 23
Finished Dec 31 12:36:58 PM PST 23
Peak memory 200732 kb
Host smart-be3e3799-42e4-4dc2-9c82-191bf321c9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935578781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.1935578781
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.3909960561
Short name T851
Test name
Test status
Simulation time 166872837044 ps
CPU time 167.1 seconds
Started Dec 31 12:33:06 PM PST 23
Finished Dec 31 12:35:56 PM PST 23
Peak memory 200768 kb
Host smart-fd74cea2-f719-43d9-b36b-4d18426a0a04
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909960561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.3909960561
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.3023103610
Short name T532
Test name
Test status
Simulation time 492251669743 ps
CPU time 1216.87 seconds
Started Dec 31 12:33:01 PM PST 23
Finished Dec 31 12:53:20 PM PST 23
Peak memory 200724 kb
Host smart-c53e0b3e-d24e-4724-8217-67b2171d8b66
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023103610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.3023103610
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.2819442304
Short name T184
Test name
Test status
Simulation time 137882876786 ps
CPU time 515.12 seconds
Started Dec 31 12:33:21 PM PST 23
Finished Dec 31 12:41:57 PM PST 23
Peak memory 201108 kb
Host smart-5251d0b8-2055-42dc-9137-056f0a9c32c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819442304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.2819442304
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.2468211931
Short name T442
Test name
Test status
Simulation time 32079184899 ps
CPU time 63.07 seconds
Started Dec 31 12:33:36 PM PST 23
Finished Dec 31 12:34:42 PM PST 23
Peak memory 200536 kb
Host smart-dc6e5c3f-a8b1-4988-95d3-6924855705d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468211931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.2468211931
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.3236098791
Short name T491
Test name
Test status
Simulation time 4889961421 ps
CPU time 12.15 seconds
Started Dec 31 12:33:28 PM PST 23
Finished Dec 31 12:33:45 PM PST 23
Peak memory 200548 kb
Host smart-a0d40b2f-253b-4dc0-a1ff-1433ba1a7727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236098791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.3236098791
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.203548949
Short name T506
Test name
Test status
Simulation time 5816276385 ps
CPU time 7.23 seconds
Started Dec 31 12:33:20 PM PST 23
Finished Dec 31 12:33:29 PM PST 23
Peak memory 200512 kb
Host smart-fef6a404-fd6d-4488-a697-3eca9de44800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203548949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.203548949
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.3015782459
Short name T795
Test name
Test status
Simulation time 91742309112 ps
CPU time 137.11 seconds
Started Dec 31 12:33:21 PM PST 23
Finished Dec 31 12:35:40 PM PST 23
Peak memory 209412 kb
Host smart-e84b3950-8fd4-4264-96b6-fd3035f42e40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015782459 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.3015782459
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.4224447770
Short name T451
Test name
Test status
Simulation time 535394300 ps
CPU time 0.86 seconds
Started Dec 31 12:32:09 PM PST 23
Finished Dec 31 12:32:11 PM PST 23
Peak memory 200524 kb
Host smart-4d168d0e-3419-4994-b994-4e5fbae353d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224447770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.4224447770
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.1686917552
Short name T725
Test name
Test status
Simulation time 335474069199 ps
CPU time 195.58 seconds
Started Dec 31 12:32:00 PM PST 23
Finished Dec 31 12:35:17 PM PST 23
Peak memory 201000 kb
Host smart-fb5e035e-d972-4fc6-b44a-82021beb2b3b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686917552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.1686917552
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.1619404041
Short name T841
Test name
Test status
Simulation time 160921188845 ps
CPU time 348.97 seconds
Started Dec 31 12:32:05 PM PST 23
Finished Dec 31 12:37:55 PM PST 23
Peak memory 200772 kb
Host smart-ca302442-a12d-4dd8-9803-cd0a5f81db59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619404041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.1619404041
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.3132679740
Short name T133
Test name
Test status
Simulation time 488611478162 ps
CPU time 210.88 seconds
Started Dec 31 12:32:02 PM PST 23
Finished Dec 31 12:35:34 PM PST 23
Peak memory 200756 kb
Host smart-13f9e646-2333-433b-a3ea-83f7105ebe3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132679740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.3132679740
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.3424778732
Short name T598
Test name
Test status
Simulation time 491676320814 ps
CPU time 296.89 seconds
Started Dec 31 12:31:59 PM PST 23
Finished Dec 31 12:36:56 PM PST 23
Peak memory 200696 kb
Host smart-9b024634-fd62-45c0-a769-a5436bec45ae
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424778732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.3424778732
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.3297168714
Short name T440
Test name
Test status
Simulation time 331738317016 ps
CPU time 193.44 seconds
Started Dec 31 12:33:13 PM PST 23
Finished Dec 31 12:36:31 PM PST 23
Peak memory 200792 kb
Host smart-068f1363-f463-41c3-b3be-c3a218831137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297168714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.3297168714
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.1015962162
Short name T441
Test name
Test status
Simulation time 328777555587 ps
CPU time 747.83 seconds
Started Dec 31 12:32:06 PM PST 23
Finished Dec 31 12:44:35 PM PST 23
Peak memory 200708 kb
Host smart-e81d057f-43f2-47e8-90db-4e657d7cad63
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015962162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.1015962162
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.2923976650
Short name T211
Test name
Test status
Simulation time 168105370829 ps
CPU time 370.82 seconds
Started Dec 31 12:32:11 PM PST 23
Finished Dec 31 12:38:23 PM PST 23
Peak memory 200664 kb
Host smart-3573f512-cead-460e-8a6b-8f2c0731334b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923976650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.2923976650
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.3605964852
Short name T699
Test name
Test status
Simulation time 163238502183 ps
CPU time 74.67 seconds
Started Dec 31 12:32:47 PM PST 23
Finished Dec 31 12:34:04 PM PST 23
Peak memory 199120 kb
Host smart-700c61ef-e1a0-4207-81ff-0b7757c9d5d3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605964852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.3605964852
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.1812081562
Short name T732
Test name
Test status
Simulation time 116900092246 ps
CPU time 413.78 seconds
Started Dec 31 12:32:13 PM PST 23
Finished Dec 31 12:39:08 PM PST 23
Peak memory 201156 kb
Host smart-563a7c7e-22b1-46dd-9199-1d9f7c7c100f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812081562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.1812081562
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.159194373
Short name T657
Test name
Test status
Simulation time 32667104757 ps
CPU time 42.13 seconds
Started Dec 31 12:32:16 PM PST 23
Finished Dec 31 12:33:00 PM PST 23
Peak memory 200524 kb
Host smart-4fdc4687-c486-4fff-a5d4-d1c4b3270644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159194373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.159194373
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.993720056
Short name T796
Test name
Test status
Simulation time 5059698750 ps
CPU time 3.57 seconds
Started Dec 31 12:32:10 PM PST 23
Finished Dec 31 12:32:15 PM PST 23
Peak memory 200592 kb
Host smart-8d01b44e-2089-4a1a-a883-1b1b283b9918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993720056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.993720056
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.2574995253
Short name T53
Test name
Test status
Simulation time 7939578430 ps
CPU time 10.14 seconds
Started Dec 31 12:31:59 PM PST 23
Finished Dec 31 12:32:10 PM PST 23
Peak memory 216940 kb
Host smart-74b08dec-e9f4-4d27-8855-961a94969529
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574995253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.2574995253
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.496843037
Short name T516
Test name
Test status
Simulation time 5630982672 ps
CPU time 7.42 seconds
Started Dec 31 12:32:01 PM PST 23
Finished Dec 31 12:32:10 PM PST 23
Peak memory 200948 kb
Host smart-403d27e7-8550-4c51-9e38-68f8a47c0234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496843037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.496843037
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.2565671393
Short name T249
Test name
Test status
Simulation time 174794473104 ps
CPU time 29.71 seconds
Started Dec 31 12:32:13 PM PST 23
Finished Dec 31 12:32:45 PM PST 23
Peak memory 200792 kb
Host smart-450c108e-bb0a-47c9-9670-1ef8d7eb4fe5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565671393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
2565671393
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.1038190410
Short name T773
Test name
Test status
Simulation time 296802152 ps
CPU time 0.94 seconds
Started Dec 31 12:33:33 PM PST 23
Finished Dec 31 12:33:39 PM PST 23
Peak memory 200536 kb
Host smart-96521ac2-e940-496f-a88b-7715fbbc7742
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038190410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.1038190410
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.3582471486
Short name T340
Test name
Test status
Simulation time 324887669571 ps
CPU time 203.89 seconds
Started Dec 31 12:33:38 PM PST 23
Finished Dec 31 12:37:04 PM PST 23
Peak memory 200836 kb
Host smart-f230eec7-9622-4538-bfec-68f4adae067b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582471486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.3582471486
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.2573012814
Short name T237
Test name
Test status
Simulation time 166239508071 ps
CPU time 418.31 seconds
Started Dec 31 12:33:46 PM PST 23
Finished Dec 31 12:40:45 PM PST 23
Peak memory 200784 kb
Host smart-ce7bae51-38f8-4048-bcf9-6126c8b098b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573012814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.2573012814
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.1577286453
Short name T146
Test name
Test status
Simulation time 491074714866 ps
CPU time 75.9 seconds
Started Dec 31 12:33:26 PM PST 23
Finished Dec 31 12:34:49 PM PST 23
Peak memory 200792 kb
Host smart-da31b282-e777-443c-bcb2-48c006405f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577286453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.1577286453
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.3784687530
Short name T20
Test name
Test status
Simulation time 325130952392 ps
CPU time 205.8 seconds
Started Dec 31 12:33:18 PM PST 23
Finished Dec 31 12:36:47 PM PST 23
Peak memory 200712 kb
Host smart-515b52d1-a2bf-4621-a0fc-04ddb1774dc3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784687530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.3784687530
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.2614479409
Short name T523
Test name
Test status
Simulation time 323468776537 ps
CPU time 743.07 seconds
Started Dec 31 12:33:41 PM PST 23
Finished Dec 31 12:46:06 PM PST 23
Peak memory 200804 kb
Host smart-b965b4ae-0b1b-4de2-8770-adeac726c9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614479409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.2614479409
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.2899919622
Short name T448
Test name
Test status
Simulation time 491086108578 ps
CPU time 1157.96 seconds
Started Dec 31 12:33:28 PM PST 23
Finished Dec 31 12:52:51 PM PST 23
Peak memory 200840 kb
Host smart-fedc090b-4416-4af4-b57d-ac07cfbd1351
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899919622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.2899919622
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.3944869186
Short name T260
Test name
Test status
Simulation time 164562141518 ps
CPU time 92.8 seconds
Started Dec 31 12:33:31 PM PST 23
Finished Dec 31 12:35:06 PM PST 23
Peak memory 200736 kb
Host smart-8908dfc6-7869-474e-ac7e-57645e33a9e3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944869186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.3944869186
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.1940320045
Short name T743
Test name
Test status
Simulation time 488963281142 ps
CPU time 1118.23 seconds
Started Dec 31 12:32:58 PM PST 23
Finished Dec 31 12:51:38 PM PST 23
Peak memory 200648 kb
Host smart-a41f7e26-cd12-420b-bb9f-239321c87eee
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940320045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.1940320045
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.3088317940
Short name T560
Test name
Test status
Simulation time 37153771027 ps
CPU time 82.17 seconds
Started Dec 31 12:33:27 PM PST 23
Finished Dec 31 12:34:55 PM PST 23
Peak memory 200552 kb
Host smart-195aa385-e3de-4c43-a980-ed8c774bd703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088317940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.3088317940
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.2919343743
Short name T791
Test name
Test status
Simulation time 3940361615 ps
CPU time 5.28 seconds
Started Dec 31 12:33:07 PM PST 23
Finished Dec 31 12:33:15 PM PST 23
Peak memory 200584 kb
Host smart-367f1237-7105-4b49-b67d-3b8cbd5b7c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919343743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.2919343743
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.1450956144
Short name T507
Test name
Test status
Simulation time 5987004361 ps
CPU time 4.67 seconds
Started Dec 31 12:33:15 PM PST 23
Finished Dec 31 12:33:23 PM PST 23
Peak memory 200556 kb
Host smart-ffbf0ca6-1beb-4169-8dd0-c9fb1b2475c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450956144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.1450956144
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.336680100
Short name T212
Test name
Test status
Simulation time 169314618318 ps
CPU time 362.86 seconds
Started Dec 31 12:33:22 PM PST 23
Finished Dec 31 12:39:26 PM PST 23
Peak memory 200668 kb
Host smart-104268a2-6baf-4d32-a252-53a7141b0bc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336680100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all.
336680100
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.1553274311
Short name T847
Test name
Test status
Simulation time 100599392761 ps
CPU time 48.9 seconds
Started Dec 31 12:33:11 PM PST 23
Finished Dec 31 12:34:06 PM PST 23
Peak memory 209004 kb
Host smart-aa3e9309-40ac-4226-a789-2cbfa5a580b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553274311 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.1553274311
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.1797344226
Short name T639
Test name
Test status
Simulation time 493714864 ps
CPU time 1.79 seconds
Started Dec 31 12:33:06 PM PST 23
Finished Dec 31 12:33:09 PM PST 23
Peak memory 200452 kb
Host smart-22f3edc5-bef0-4aaa-ade2-fc0f9185e518
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797344226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.1797344226
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.1773415089
Short name T226
Test name
Test status
Simulation time 166868767788 ps
CPU time 57.99 seconds
Started Dec 31 12:33:29 PM PST 23
Finished Dec 31 12:34:31 PM PST 23
Peak memory 200804 kb
Host smart-611c9479-8275-41e7-b955-e1ac3f5cd2ae
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773415089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.1773415089
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.2182703568
Short name T316
Test name
Test status
Simulation time 165611592572 ps
CPU time 428.34 seconds
Started Dec 31 12:33:22 PM PST 23
Finished Dec 31 12:40:32 PM PST 23
Peak memory 200692 kb
Host smart-37a182fd-843b-4111-969c-1153702e8115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182703568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.2182703568
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.2858241484
Short name T528
Test name
Test status
Simulation time 317718418331 ps
CPU time 76.92 seconds
Started Dec 31 12:33:17 PM PST 23
Finished Dec 31 12:34:38 PM PST 23
Peak memory 200708 kb
Host smart-0b72b871-3895-424e-90d0-c4018265160f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858241484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.2858241484
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.3778073076
Short name T134
Test name
Test status
Simulation time 502008891341 ps
CPU time 305.04 seconds
Started Dec 31 12:33:08 PM PST 23
Finished Dec 31 12:38:15 PM PST 23
Peak memory 200748 kb
Host smart-565d667f-3641-46d3-8257-c81fcb57b770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778073076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.3778073076
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.3590455164
Short name T826
Test name
Test status
Simulation time 324362788548 ps
CPU time 724.71 seconds
Started Dec 31 12:33:04 PM PST 23
Finished Dec 31 12:45:10 PM PST 23
Peak memory 200756 kb
Host smart-65fd3294-da1f-4d1e-9a7a-d93e013f2a32
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590455164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.3590455164
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.2087344618
Short name T798
Test name
Test status
Simulation time 158948027860 ps
CPU time 368.08 seconds
Started Dec 31 12:33:15 PM PST 23
Finished Dec 31 12:39:26 PM PST 23
Peak memory 200708 kb
Host smart-da607323-315b-417b-872c-df551e48236f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087344618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.2087344618
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.3040282292
Short name T182
Test name
Test status
Simulation time 71355410936 ps
CPU time 222.02 seconds
Started Dec 31 12:33:18 PM PST 23
Finished Dec 31 12:37:03 PM PST 23
Peak memory 201244 kb
Host smart-188775fb-a762-4455-b950-cdf6540a575c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040282292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.3040282292
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.439297455
Short name T526
Test name
Test status
Simulation time 27224617271 ps
CPU time 24.16 seconds
Started Dec 31 12:33:06 PM PST 23
Finished Dec 31 12:33:31 PM PST 23
Peak memory 200576 kb
Host smart-d5359ee9-c0c0-4bce-a1a9-8bcb0a39a0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439297455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.439297455
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.1775052031
Short name T669
Test name
Test status
Simulation time 4963157950 ps
CPU time 3.82 seconds
Started Dec 31 12:33:14 PM PST 23
Finished Dec 31 12:33:22 PM PST 23
Peak memory 200608 kb
Host smart-495f8937-a774-4f54-b188-bc59aec7b754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775052031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.1775052031
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.1275068
Short name T740
Test name
Test status
Simulation time 5980669824 ps
CPU time 13.67 seconds
Started Dec 31 12:33:36 PM PST 23
Finished Dec 31 12:33:52 PM PST 23
Peak memory 200576 kb
Host smart-32e5a7e0-0a20-42ae-adfb-6da284589dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.1275068
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.1506912742
Short name T194
Test name
Test status
Simulation time 165961984796 ps
CPU time 359.33 seconds
Started Dec 31 12:33:26 PM PST 23
Finished Dec 31 12:39:32 PM PST 23
Peak memory 200728 kb
Host smart-48a14d5f-f249-42a1-9794-0e073052a0c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506912742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.1506912742
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.1622293041
Short name T204
Test name
Test status
Simulation time 235251051170 ps
CPU time 137.37 seconds
Started Dec 31 12:33:09 PM PST 23
Finished Dec 31 12:35:31 PM PST 23
Peak memory 209028 kb
Host smart-7cea378d-5865-4afe-a47e-764e5e00f998
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622293041 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.1622293041
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.3221527214
Short name T581
Test name
Test status
Simulation time 439447285 ps
CPU time 0.86 seconds
Started Dec 31 12:33:34 PM PST 23
Finished Dec 31 12:33:39 PM PST 23
Peak memory 200508 kb
Host smart-9a2b1cc5-a834-485e-97fc-7be6371a5028
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221527214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.3221527214
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.2420182225
Short name T215
Test name
Test status
Simulation time 328144252658 ps
CPU time 327.82 seconds
Started Dec 31 12:33:38 PM PST 23
Finished Dec 31 12:39:08 PM PST 23
Peak memory 200712 kb
Host smart-61e7d65a-b9da-4437-88d1-dc2dfa96fb87
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420182225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.2420182225
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.27371729
Short name T21
Test name
Test status
Simulation time 159864540418 ps
CPU time 106.39 seconds
Started Dec 31 12:33:30 PM PST 23
Finished Dec 31 12:35:20 PM PST 23
Peak memory 200764 kb
Host smart-8b81aa3e-81e8-48db-9884-d61579faef14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27371729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.27371729
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.3628987189
Short name T153
Test name
Test status
Simulation time 494608584226 ps
CPU time 292.69 seconds
Started Dec 31 12:33:31 PM PST 23
Finished Dec 31 12:38:26 PM PST 23
Peak memory 200788 kb
Host smart-c5d0ce63-efe1-4068-ad30-6926364e02f2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628987189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.3628987189
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.500292316
Short name T222
Test name
Test status
Simulation time 327996247345 ps
CPU time 713.97 seconds
Started Dec 31 12:33:28 PM PST 23
Finished Dec 31 12:45:27 PM PST 23
Peak memory 200704 kb
Host smart-c9fde208-3454-4d73-987b-d0b2d29f4ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500292316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.500292316
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.4096810476
Short name T589
Test name
Test status
Simulation time 329338650334 ps
CPU time 376.63 seconds
Started Dec 31 12:33:08 PM PST 23
Finished Dec 31 12:39:27 PM PST 23
Peak memory 200840 kb
Host smart-ac306038-5cea-4929-8bb9-a3f0fe9b9dfb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096810476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.4096810476
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.2280068530
Short name T46
Test name
Test status
Simulation time 502107637061 ps
CPU time 146.91 seconds
Started Dec 31 12:33:35 PM PST 23
Finished Dec 31 12:36:05 PM PST 23
Peak memory 200748 kb
Host smart-9559e430-1a21-49df-b47b-f2f340ba91a6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280068530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.2280068530
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.2506799176
Short name T190
Test name
Test status
Simulation time 143260802269 ps
CPU time 455.02 seconds
Started Dec 31 12:33:29 PM PST 23
Finished Dec 31 12:41:08 PM PST 23
Peak memory 201148 kb
Host smart-4767f55d-649c-40c4-a379-8868571b4c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506799176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.2506799176
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.567701121
Short name T837
Test name
Test status
Simulation time 46573270047 ps
CPU time 109.91 seconds
Started Dec 31 12:33:19 PM PST 23
Finished Dec 31 12:35:12 PM PST 23
Peak memory 200576 kb
Host smart-ec7f5427-2f66-40f7-82f7-d3e0406fbbf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567701121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.567701121
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.2896522762
Short name T425
Test name
Test status
Simulation time 3143394700 ps
CPU time 6.67 seconds
Started Dec 31 12:33:37 PM PST 23
Finished Dec 31 12:33:46 PM PST 23
Peak memory 200568 kb
Host smart-04fcf3db-7b33-4f8a-93db-5255f1748f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896522762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.2896522762
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.2192907665
Short name T447
Test name
Test status
Simulation time 5665975548 ps
CPU time 4.39 seconds
Started Dec 31 12:33:29 PM PST 23
Finished Dec 31 12:33:38 PM PST 23
Peak memory 200532 kb
Host smart-d26ee233-4d9e-4cf9-80c5-a0328756d4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192907665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.2192907665
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.3249941728
Short name T490
Test name
Test status
Simulation time 116795466823 ps
CPU time 578.11 seconds
Started Dec 31 12:33:13 PM PST 23
Finished Dec 31 12:42:56 PM PST 23
Peak memory 201160 kb
Host smart-5316d8ba-4d6b-4b91-93de-71bbfd179210
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249941728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.3249941728
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.1786307146
Short name T527
Test name
Test status
Simulation time 38000513582 ps
CPU time 108.98 seconds
Started Dec 31 12:33:24 PM PST 23
Finished Dec 31 12:35:15 PM PST 23
Peak memory 209488 kb
Host smart-90975da5-b56d-449d-b301-0432c0cd7da5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786307146 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.1786307146
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.2871194171
Short name T521
Test name
Test status
Simulation time 449465589 ps
CPU time 0.84 seconds
Started Dec 31 12:33:48 PM PST 23
Finished Dec 31 12:33:51 PM PST 23
Peak memory 200524 kb
Host smart-4ba77f59-06df-43cb-849c-4afb6241b114
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871194171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.2871194171
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.1163550096
Short name T640
Test name
Test status
Simulation time 171318615790 ps
CPU time 370.94 seconds
Started Dec 31 12:33:48 PM PST 23
Finished Dec 31 12:40:01 PM PST 23
Peak memory 200832 kb
Host smart-d1e342cd-be0d-44a1-ba1a-71dadea8c866
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163550096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.1163550096
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.548523100
Short name T827
Test name
Test status
Simulation time 169708970826 ps
CPU time 115.24 seconds
Started Dec 31 12:33:26 PM PST 23
Finished Dec 31 12:35:28 PM PST 23
Peak memory 200728 kb
Host smart-f4e99c95-bc77-47e2-bab6-37180438bae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548523100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.548523100
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.2519968242
Short name T756
Test name
Test status
Simulation time 487863828248 ps
CPU time 317.16 seconds
Started Dec 31 12:33:32 PM PST 23
Finished Dec 31 12:38:54 PM PST 23
Peak memory 200796 kb
Host smart-bbde763e-cfc6-4eb1-9a82-daccf5dd3e8c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519968242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.2519968242
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.3564962674
Short name T192
Test name
Test status
Simulation time 163735176091 ps
CPU time 201.62 seconds
Started Dec 31 12:33:39 PM PST 23
Finished Dec 31 12:37:03 PM PST 23
Peak memory 200680 kb
Host smart-28d695f3-86c2-4f12-bdb2-c653301d4723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564962674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.3564962674
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.550128149
Short name T473
Test name
Test status
Simulation time 496487439125 ps
CPU time 594.58 seconds
Started Dec 31 12:33:18 PM PST 23
Finished Dec 31 12:43:16 PM PST 23
Peak memory 200672 kb
Host smart-602d7d43-6d7b-43bf-af6f-f8b8778d3d8e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=550128149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fixe
d.550128149
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.3491797125
Short name T807
Test name
Test status
Simulation time 326459026094 ps
CPU time 156.17 seconds
Started Dec 31 12:33:09 PM PST 23
Finished Dec 31 12:35:51 PM PST 23
Peak memory 200732 kb
Host smart-e8d6f55b-12bb-4f46-86b9-db8e61fcf0e8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491797125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.3491797125
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.4136768077
Short name T830
Test name
Test status
Simulation time 324375995319 ps
CPU time 747.41 seconds
Started Dec 31 12:33:27 PM PST 23
Finished Dec 31 12:46:01 PM PST 23
Peak memory 201076 kb
Host smart-7cafd5be-1d3f-4ebb-9d66-653f03cf79c3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136768077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.4136768077
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.2485257442
Short name T467
Test name
Test status
Simulation time 119015071919 ps
CPU time 387.86 seconds
Started Dec 31 12:33:24 PM PST 23
Finished Dec 31 12:39:54 PM PST 23
Peak memory 201076 kb
Host smart-c0d9d46d-b9ba-40c2-89a3-df993e6ba3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485257442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.2485257442
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.584804902
Short name T748
Test name
Test status
Simulation time 29448680107 ps
CPU time 72.78 seconds
Started Dec 31 12:33:28 PM PST 23
Finished Dec 31 12:34:46 PM PST 23
Peak memory 200556 kb
Host smart-a60c3cf2-2f55-4573-846b-21d1ad40679e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584804902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.584804902
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.1494588270
Short name T485
Test name
Test status
Simulation time 3396190318 ps
CPU time 2.4 seconds
Started Dec 31 12:33:30 PM PST 23
Finished Dec 31 12:33:37 PM PST 23
Peak memory 200636 kb
Host smart-963c39ea-adc9-474f-8f4e-add0ce967829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494588270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.1494588270
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.2534317902
Short name T737
Test name
Test status
Simulation time 6134577001 ps
CPU time 7.37 seconds
Started Dec 31 12:33:24 PM PST 23
Finished Dec 31 12:33:33 PM PST 23
Peak memory 200572 kb
Host smart-c9f9c773-a0f7-4d5a-8d65-d5fbb73dc48f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534317902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.2534317902
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.6204643
Short name T197
Test name
Test status
Simulation time 165997877744 ps
CPU time 180.63 seconds
Started Dec 31 12:33:21 PM PST 23
Finished Dec 31 12:36:23 PM PST 23
Peak memory 200700 kb
Host smart-9dfa0031-2892-4015-b6c3-0c87549772f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6204643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_a
ll_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all.6204643
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.1469603358
Short name T285
Test name
Test status
Simulation time 124338947501 ps
CPU time 236.61 seconds
Started Dec 31 12:33:43 PM PST 23
Finished Dec 31 12:37:41 PM PST 23
Peak memory 217556 kb
Host smart-caf204de-594f-4332-945a-8a5b2ddbd992
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469603358 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.1469603358
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.846304528
Short name T499
Test name
Test status
Simulation time 329573134 ps
CPU time 1.29 seconds
Started Dec 31 12:33:35 PM PST 23
Finished Dec 31 12:33:40 PM PST 23
Peak memory 200484 kb
Host smart-b30891a2-8d6e-4c84-83b9-1a382acfa00c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846304528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.846304528
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.4158326954
Short name T295
Test name
Test status
Simulation time 328969129239 ps
CPU time 762.51 seconds
Started Dec 31 12:33:23 PM PST 23
Finished Dec 31 12:46:07 PM PST 23
Peak memory 200832 kb
Host smart-c70b86f9-d491-4633-a85a-c5c2210f8120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158326954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.4158326954
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.1183239759
Short name T671
Test name
Test status
Simulation time 489900476508 ps
CPU time 582.6 seconds
Started Dec 31 12:33:25 PM PST 23
Finished Dec 31 12:43:13 PM PST 23
Peak memory 200792 kb
Host smart-cf67025e-77f5-4a75-a40c-b90c37fe3fdb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183239759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.1183239759
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.825134393
Short name T56
Test name
Test status
Simulation time 166852893117 ps
CPU time 266.32 seconds
Started Dec 31 12:33:20 PM PST 23
Finished Dec 31 12:37:48 PM PST 23
Peak memory 200740 kb
Host smart-54f82fcb-d2f3-4d85-be63-7afc62b79d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825134393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.825134393
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.1634748341
Short name T616
Test name
Test status
Simulation time 327485325274 ps
CPU time 196.61 seconds
Started Dec 31 12:33:35 PM PST 23
Finished Dec 31 12:36:55 PM PST 23
Peak memory 200684 kb
Host smart-2ef7f7c5-742b-4aeb-b4b1-3f9a21220219
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634748341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.1634748341
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.2435346683
Short name T324
Test name
Test status
Simulation time 163346322201 ps
CPU time 185.91 seconds
Started Dec 31 12:33:17 PM PST 23
Finished Dec 31 12:36:27 PM PST 23
Peak memory 200728 kb
Host smart-876f9485-d638-482f-83f0-1e71fe1d3182
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435346683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.2435346683
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.4063098152
Short name T663
Test name
Test status
Simulation time 326890155321 ps
CPU time 200.38 seconds
Started Dec 31 12:33:21 PM PST 23
Finished Dec 31 12:36:43 PM PST 23
Peak memory 200736 kb
Host smart-1c146217-9c85-4d68-930b-34c1bae02415
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063098152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.4063098152
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.52224560
Short name T846
Test name
Test status
Simulation time 98540478766 ps
CPU time 371.37 seconds
Started Dec 31 12:33:23 PM PST 23
Finished Dec 31 12:39:36 PM PST 23
Peak memory 201168 kb
Host smart-76458374-6832-40f2-a235-7571e5ab3a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52224560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.52224560
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.232078079
Short name T695
Test name
Test status
Simulation time 36871685661 ps
CPU time 88.41 seconds
Started Dec 31 12:33:24 PM PST 23
Finished Dec 31 12:34:54 PM PST 23
Peak memory 200580 kb
Host smart-b5698ff2-e897-45da-8645-dec813ee239b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232078079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.232078079
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.567655956
Short name T486
Test name
Test status
Simulation time 3673036755 ps
CPU time 4.57 seconds
Started Dec 31 12:33:24 PM PST 23
Finished Dec 31 12:33:30 PM PST 23
Peak memory 200540 kb
Host smart-67514a2d-ba96-49d1-afa9-ce2b56c3b575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567655956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.567655956
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.81941464
Short name T611
Test name
Test status
Simulation time 5926588556 ps
CPU time 14.81 seconds
Started Dec 31 12:33:39 PM PST 23
Finished Dec 31 12:33:56 PM PST 23
Peak memory 200540 kb
Host smart-34672065-f935-4f79-b867-d1ba52c89c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81941464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.81941464
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.2557751174
Short name T792
Test name
Test status
Simulation time 658244888975 ps
CPU time 310.62 seconds
Started Dec 31 12:33:43 PM PST 23
Finished Dec 31 12:38:55 PM PST 23
Peak memory 209416 kb
Host smart-71f26be8-2033-42be-8de3-b5ae7deba92b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557751174 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.2557751174
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.1805488768
Short name T602
Test name
Test status
Simulation time 293548027 ps
CPU time 0.77 seconds
Started Dec 31 12:33:38 PM PST 23
Finished Dec 31 12:33:40 PM PST 23
Peak memory 200520 kb
Host smart-aec85cf9-53f8-4136-abe4-1b1bce2607a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805488768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.1805488768
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.2767260200
Short name T762
Test name
Test status
Simulation time 160275162642 ps
CPU time 347.49 seconds
Started Dec 31 12:33:45 PM PST 23
Finished Dec 31 12:39:34 PM PST 23
Peak memory 200708 kb
Host smart-0dc8350b-555b-4bb0-9a81-e71ff7eecb09
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767260200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.2767260200
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.3960590824
Short name T252
Test name
Test status
Simulation time 495176832302 ps
CPU time 589.66 seconds
Started Dec 31 12:33:16 PM PST 23
Finished Dec 31 12:43:10 PM PST 23
Peak memory 200688 kb
Host smart-664fbd68-52eb-453f-85c2-d2c4184a28e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960590824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.3960590824
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.3205989344
Short name T439
Test name
Test status
Simulation time 488457445670 ps
CPU time 216.83 seconds
Started Dec 31 12:33:35 PM PST 23
Finished Dec 31 12:37:15 PM PST 23
Peak memory 200792 kb
Host smart-c9e9a0b7-b9c6-424e-84ae-0f85e736df82
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205989344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.3205989344
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.874577177
Short name T224
Test name
Test status
Simulation time 162497735785 ps
CPU time 97.8 seconds
Started Dec 31 12:33:38 PM PST 23
Finished Dec 31 12:35:18 PM PST 23
Peak memory 200820 kb
Host smart-f3a1b868-7d01-4bc1-a35d-3ebbae464a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874577177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.874577177
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.40991849
Short name T542
Test name
Test status
Simulation time 165913975953 ps
CPU time 360.99 seconds
Started Dec 31 12:33:31 PM PST 23
Finished Dec 31 12:39:34 PM PST 23
Peak memory 200752 kb
Host smart-d602fcfd-c548-4ce5-abfd-fd43e52e4af5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=40991849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fixed
.40991849
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.3299706208
Short name T241
Test name
Test status
Simulation time 485384743082 ps
CPU time 1058.06 seconds
Started Dec 31 12:33:31 PM PST 23
Finished Dec 31 12:51:12 PM PST 23
Peak memory 200748 kb
Host smart-4d2a0cbd-1ccb-41b0-bc29-f4364de2a4d7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299706208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.3299706208
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.852293832
Short name T112
Test name
Test status
Simulation time 330854614041 ps
CPU time 772.41 seconds
Started Dec 31 12:33:33 PM PST 23
Finished Dec 31 12:46:30 PM PST 23
Peak memory 200728 kb
Host smart-8ab70328-9c1d-4566-af11-b2bdf7c9fcd1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852293832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
adc_ctrl_filters_wakeup_fixed.852293832
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.2236677409
Short name T593
Test name
Test status
Simulation time 119776181979 ps
CPU time 603.62 seconds
Started Dec 31 12:33:20 PM PST 23
Finished Dec 31 12:43:25 PM PST 23
Peak memory 201184 kb
Host smart-18919cf6-fc57-4bbe-8de4-c3809d9b3942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236677409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.2236677409
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.3989171573
Short name T415
Test name
Test status
Simulation time 30982313299 ps
CPU time 75.66 seconds
Started Dec 31 12:33:42 PM PST 23
Finished Dec 31 12:34:59 PM PST 23
Peak memory 200604 kb
Host smart-6287f4cd-4b85-4e6e-b24f-9b2c845cc315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989171573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.3989171573
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.511372955
Short name T818
Test name
Test status
Simulation time 3420313739 ps
CPU time 2.74 seconds
Started Dec 31 12:33:44 PM PST 23
Finished Dec 31 12:33:48 PM PST 23
Peak memory 200636 kb
Host smart-0ec08d09-7823-41ea-bb48-c7ed308c39bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511372955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.511372955
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.238057743
Short name T574
Test name
Test status
Simulation time 5792012894 ps
CPU time 14.47 seconds
Started Dec 31 12:33:40 PM PST 23
Finished Dec 31 12:33:56 PM PST 23
Peak memory 200604 kb
Host smart-9f3c4838-5828-4c0b-b886-922168ff8acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238057743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.238057743
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.243857409
Short name T716
Test name
Test status
Simulation time 379624895038 ps
CPU time 245.08 seconds
Started Dec 31 12:33:44 PM PST 23
Finished Dec 31 12:37:51 PM PST 23
Peak memory 200720 kb
Host smart-3f69df2e-2ced-47ab-b9e2-497826104ed3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243857409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all.
243857409
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.1396306202
Short name T320
Test name
Test status
Simulation time 50294877854 ps
CPU time 104.58 seconds
Started Dec 31 12:33:25 PM PST 23
Finished Dec 31 12:35:14 PM PST 23
Peak memory 209424 kb
Host smart-5d168c6e-48f5-442b-b2a9-8da050a1efad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396306202 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.1396306202
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.1018285354
Short name T805
Test name
Test status
Simulation time 486592796 ps
CPU time 0.71 seconds
Started Dec 31 12:33:51 PM PST 23
Finished Dec 31 12:33:54 PM PST 23
Peak memory 200520 kb
Host smart-becec336-da83-4b4c-8d0f-7d5e580d94e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018285354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.1018285354
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.3504326585
Short name T140
Test name
Test status
Simulation time 493019558352 ps
CPU time 202.48 seconds
Started Dec 31 12:33:32 PM PST 23
Finished Dec 31 12:37:01 PM PST 23
Peak memory 200704 kb
Host smart-c0fe6fdb-0f89-494d-8c5c-23446b6f0d21
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504326585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.3504326585
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.2770220354
Short name T608
Test name
Test status
Simulation time 164454720175 ps
CPU time 193.91 seconds
Started Dec 31 12:33:28 PM PST 23
Finished Dec 31 12:36:47 PM PST 23
Peak memory 200804 kb
Host smart-07534ede-3c74-4437-8951-59b669ab6c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770220354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.2770220354
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.1447451064
Short name T597
Test name
Test status
Simulation time 492026872468 ps
CPU time 1121.36 seconds
Started Dec 31 12:33:42 PM PST 23
Finished Dec 31 12:52:24 PM PST 23
Peak memory 200780 kb
Host smart-1a6c1d24-155d-4038-a3e8-325ff328a257
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447451064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.1447451064
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.3641221554
Short name T855
Test name
Test status
Simulation time 160013712620 ps
CPU time 102.51 seconds
Started Dec 31 12:33:36 PM PST 23
Finished Dec 31 12:35:22 PM PST 23
Peak memory 200836 kb
Host smart-3a5cefa1-4e4e-410a-b9cc-0903b3360a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641221554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.3641221554
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.3234507239
Short name T733
Test name
Test status
Simulation time 325523310773 ps
CPU time 736.8 seconds
Started Dec 31 12:33:45 PM PST 23
Finished Dec 31 12:46:03 PM PST 23
Peak memory 200792 kb
Host smart-bb2dd235-f257-4975-bb7e-690ebe8c8261
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234507239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.3234507239
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.3191347863
Short name T109
Test name
Test status
Simulation time 495263704823 ps
CPU time 300.49 seconds
Started Dec 31 12:33:42 PM PST 23
Finished Dec 31 12:38:44 PM PST 23
Peak memory 200744 kb
Host smart-f1119a5a-fc25-420f-99a9-2ad5c2d3f07d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191347863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.3191347863
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.2415971657
Short name T717
Test name
Test status
Simulation time 161402754143 ps
CPU time 331.9 seconds
Started Dec 31 12:33:41 PM PST 23
Finished Dec 31 12:39:14 PM PST 23
Peak memory 200632 kb
Host smart-148f9937-894b-4049-805f-36b2d6ddb25c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415971657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.2415971657
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.1918304221
Short name T745
Test name
Test status
Simulation time 44591788826 ps
CPU time 96.82 seconds
Started Dec 31 12:33:59 PM PST 23
Finished Dec 31 12:35:39 PM PST 23
Peak memory 200580 kb
Host smart-4978319f-ef44-4a87-83d0-432f7a2ff8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918304221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.1918304221
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.733758846
Short name T481
Test name
Test status
Simulation time 4577449334 ps
CPU time 10.85 seconds
Started Dec 31 12:33:38 PM PST 23
Finished Dec 31 12:33:51 PM PST 23
Peak memory 200576 kb
Host smart-989d2e49-030c-4e89-a895-d878e6d765f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733758846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.733758846
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.4143393714
Short name T652
Test name
Test status
Simulation time 5736913755 ps
CPU time 7 seconds
Started Dec 31 12:33:27 PM PST 23
Finished Dec 31 12:33:40 PM PST 23
Peak memory 200532 kb
Host smart-7c6fc1a2-bad6-423c-b92a-ce336900c8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143393714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.4143393714
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.1848174102
Short name T89
Test name
Test status
Simulation time 55494466920 ps
CPU time 34.13 seconds
Started Dec 31 12:33:44 PM PST 23
Finished Dec 31 12:34:20 PM PST 23
Peak memory 208944 kb
Host smart-a5b2320f-bc59-48f0-8eb8-62bb93d8f46b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848174102 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.1848174102
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.2533859696
Short name T456
Test name
Test status
Simulation time 408548959 ps
CPU time 1.03 seconds
Started Dec 31 12:33:45 PM PST 23
Finished Dec 31 12:33:47 PM PST 23
Peak memory 200496 kb
Host smart-00851b55-8cf0-4eaf-b866-c43de7d2aed8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533859696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.2533859696
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.4053476775
Short name T160
Test name
Test status
Simulation time 167003513361 ps
CPU time 364.36 seconds
Started Dec 31 12:33:45 PM PST 23
Finished Dec 31 12:39:51 PM PST 23
Peak memory 200800 kb
Host smart-51f1eead-0060-4d5e-9557-a44899e0eac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053476775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.4053476775
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.4035154993
Short name T318
Test name
Test status
Simulation time 327766120839 ps
CPU time 218.79 seconds
Started Dec 31 12:33:44 PM PST 23
Finished Dec 31 12:37:24 PM PST 23
Peak memory 200764 kb
Host smart-fa114344-9e53-48f6-ac0a-2e29a09f3d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035154993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.4035154993
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.1471913566
Short name T638
Test name
Test status
Simulation time 163768591958 ps
CPU time 387.61 seconds
Started Dec 31 12:33:45 PM PST 23
Finished Dec 31 12:40:14 PM PST 23
Peak memory 200716 kb
Host smart-cf092781-69c7-4d93-94ba-90a4cb3d47ed
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471913566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.1471913566
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.3102971180
Short name T228
Test name
Test status
Simulation time 487941929855 ps
CPU time 1041.03 seconds
Started Dec 31 12:33:50 PM PST 23
Finished Dec 31 12:51:12 PM PST 23
Peak memory 200732 kb
Host smart-9ccbff78-bf59-4205-ba52-0bb3292909d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102971180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.3102971180
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.2788826814
Short name T461
Test name
Test status
Simulation time 332817372414 ps
CPU time 172.84 seconds
Started Dec 31 12:33:43 PM PST 23
Finished Dec 31 12:36:37 PM PST 23
Peak memory 200672 kb
Host smart-284390e7-d162-4672-865b-601aed1c6bba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788826814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.2788826814
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.3969935857
Short name T758
Test name
Test status
Simulation time 329527124968 ps
CPU time 358.99 seconds
Started Dec 31 12:33:36 PM PST 23
Finished Dec 31 12:39:38 PM PST 23
Peak memory 200744 kb
Host smart-90a3cf9c-8194-4352-82ff-281db637251b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969935857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.3969935857
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.3889281839
Short name T816
Test name
Test status
Simulation time 498562709896 ps
CPU time 186.17 seconds
Started Dec 31 12:33:38 PM PST 23
Finished Dec 31 12:36:46 PM PST 23
Peak memory 200776 kb
Host smart-cf3e76d8-4091-46b7-9de9-37ed0333366c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889281839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.3889281839
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.3530102709
Short name T498
Test name
Test status
Simulation time 70210880991 ps
CPU time 370.87 seconds
Started Dec 31 12:33:37 PM PST 23
Finished Dec 31 12:39:50 PM PST 23
Peak memory 201152 kb
Host smart-e951aa76-1585-4d6e-9586-a4d2954b1e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530102709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.3530102709
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.770252618
Short name T582
Test name
Test status
Simulation time 36390934002 ps
CPU time 45.54 seconds
Started Dec 31 12:33:49 PM PST 23
Finished Dec 31 12:34:36 PM PST 23
Peak memory 200552 kb
Host smart-bc8e00fe-a31c-4a48-9f49-82ccc891ff7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770252618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.770252618
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.210543178
Short name T861
Test name
Test status
Simulation time 5286993774 ps
CPU time 12.3 seconds
Started Dec 31 12:33:53 PM PST 23
Finished Dec 31 12:34:07 PM PST 23
Peak memory 200592 kb
Host smart-a2908b65-aa6b-4b84-aa5b-fcc0e26d41e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210543178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.210543178
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.4252364298
Short name T561
Test name
Test status
Simulation time 6091701451 ps
CPU time 14.83 seconds
Started Dec 31 12:33:44 PM PST 23
Finished Dec 31 12:34:00 PM PST 23
Peak memory 200528 kb
Host smart-008b251d-419d-4c39-a38b-0ae72e97cd80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252364298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.4252364298
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.3097917139
Short name T124
Test name
Test status
Simulation time 376693337823 ps
CPU time 847.66 seconds
Started Dec 31 12:33:40 PM PST 23
Finished Dec 31 12:47:50 PM PST 23
Peak memory 200720 kb
Host smart-a6cbdfca-eb90-4206-a00d-d4a117f99b1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097917139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.3097917139
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.621957905
Short name T601
Test name
Test status
Simulation time 318260298 ps
CPU time 0.93 seconds
Started Dec 31 12:33:38 PM PST 23
Finished Dec 31 12:33:41 PM PST 23
Peak memory 200472 kb
Host smart-25eed5e0-8882-4cf4-a3c4-d9208fd259c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621957905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.621957905
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.2983540425
Short name T147
Test name
Test status
Simulation time 331009088153 ps
CPU time 123.24 seconds
Started Dec 31 12:33:47 PM PST 23
Finished Dec 31 12:35:52 PM PST 23
Peak memory 200732 kb
Host smart-8d617f8d-152e-4f07-8aa5-c3c613470290
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983540425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.2983540425
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.843240178
Short name T329
Test name
Test status
Simulation time 327916975025 ps
CPU time 162.54 seconds
Started Dec 31 12:33:37 PM PST 23
Finished Dec 31 12:36:22 PM PST 23
Peak memory 200836 kb
Host smart-445f31a3-9035-4187-a48b-2bdd150bde76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843240178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.843240178
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.2528009347
Short name T268
Test name
Test status
Simulation time 494944507655 ps
CPU time 571.66 seconds
Started Dec 31 12:33:47 PM PST 23
Finished Dec 31 12:43:20 PM PST 23
Peak memory 200692 kb
Host smart-5b65037f-98fe-4fdc-956f-306b7d18c7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528009347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.2528009347
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.3389409956
Short name T636
Test name
Test status
Simulation time 320007626945 ps
CPU time 410.9 seconds
Started Dec 31 12:33:31 PM PST 23
Finished Dec 31 12:40:24 PM PST 23
Peak memory 200680 kb
Host smart-d34241df-6516-40fd-ba63-de0c7e44f1d9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389409956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.3389409956
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.432585652
Short name T735
Test name
Test status
Simulation time 162606656874 ps
CPU time 92.36 seconds
Started Dec 31 12:33:44 PM PST 23
Finished Dec 31 12:35:17 PM PST 23
Peak memory 200800 kb
Host smart-6b6c88b8-bd1c-48c5-b14c-69724f7f58ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432585652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.432585652
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.3257676298
Short name T568
Test name
Test status
Simulation time 323907234989 ps
CPU time 163.72 seconds
Started Dec 31 12:33:46 PM PST 23
Finished Dec 31 12:36:36 PM PST 23
Peak memory 200688 kb
Host smart-72296ada-a923-4dca-a40c-c7288425e546
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257676298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.3257676298
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.3452223935
Short name T691
Test name
Test status
Simulation time 169211678550 ps
CPU time 99.06 seconds
Started Dec 31 12:33:31 PM PST 23
Finished Dec 31 12:35:12 PM PST 23
Peak memory 200700 kb
Host smart-a5693544-3d22-46f9-bb72-86cdbe100655
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452223935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.3452223935
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.1600243115
Short name T858
Test name
Test status
Simulation time 494639207417 ps
CPU time 242.77 seconds
Started Dec 31 12:33:47 PM PST 23
Finished Dec 31 12:37:52 PM PST 23
Peak memory 200716 kb
Host smart-ebf4cb32-844a-4575-b4f8-9679ad6514de
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600243115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.1600243115
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.306128498
Short name T519
Test name
Test status
Simulation time 116343354830 ps
CPU time 429.51 seconds
Started Dec 31 12:33:41 PM PST 23
Finished Dec 31 12:40:52 PM PST 23
Peak memory 201180 kb
Host smart-13d0d221-d2e6-40b3-98e7-2f3de3cf95b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306128498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.306128498
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.1552575769
Short name T110
Test name
Test status
Simulation time 41995364531 ps
CPU time 24.23 seconds
Started Dec 31 12:33:57 PM PST 23
Finished Dec 31 12:34:23 PM PST 23
Peak memory 200552 kb
Host smart-221cf140-ab41-43af-a231-59dbef719536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552575769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.1552575769
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.1623640447
Short name T631
Test name
Test status
Simulation time 3045297888 ps
CPU time 7.35 seconds
Started Dec 31 12:33:38 PM PST 23
Finished Dec 31 12:33:47 PM PST 23
Peak memory 200548 kb
Host smart-2b654131-22f8-444f-9f32-ddb52ce2cee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623640447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.1623640447
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.1607251013
Short name T693
Test name
Test status
Simulation time 5732654365 ps
CPU time 7.33 seconds
Started Dec 31 12:33:50 PM PST 23
Finished Dec 31 12:33:58 PM PST 23
Peak memory 200660 kb
Host smart-83d4fa73-48bd-4d28-905c-f2d1446ea0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607251013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.1607251013
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.463609991
Short name T742
Test name
Test status
Simulation time 164608076523 ps
CPU time 102.63 seconds
Started Dec 31 12:33:43 PM PST 23
Finished Dec 31 12:35:27 PM PST 23
Peak memory 200704 kb
Host smart-7d1470bb-177b-4a6c-ac55-06cdcb7e8d7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463609991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all.
463609991
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.481228165
Short name T168
Test name
Test status
Simulation time 70856667283 ps
CPU time 108.12 seconds
Started Dec 31 12:33:52 PM PST 23
Finished Dec 31 12:35:42 PM PST 23
Peak memory 209352 kb
Host smart-0b292fb7-9ee4-4e8f-a06f-b9c7b86f8884
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481228165 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.481228165
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.2773074923
Short name T478
Test name
Test status
Simulation time 522111316 ps
CPU time 0.83 seconds
Started Dec 31 12:33:42 PM PST 23
Finished Dec 31 12:33:44 PM PST 23
Peak memory 200512 kb
Host smart-6c25771c-6733-40bd-9cf5-2ef8141036e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773074923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.2773074923
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.1156933018
Short name T294
Test name
Test status
Simulation time 508916998971 ps
CPU time 635.76 seconds
Started Dec 31 12:33:47 PM PST 23
Finished Dec 31 12:44:24 PM PST 23
Peak memory 199996 kb
Host smart-e96da6bf-d4a7-4486-a7b2-2d261acdfb06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156933018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.1156933018
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.3693818877
Short name T136
Test name
Test status
Simulation time 165050135773 ps
CPU time 95.5 seconds
Started Dec 31 12:33:31 PM PST 23
Finished Dec 31 12:35:09 PM PST 23
Peak memory 200740 kb
Host smart-0ad96dfd-db74-4906-8622-68f32ab2f7fc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693818877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.3693818877
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.2172520261
Short name T157
Test name
Test status
Simulation time 335270120871 ps
CPU time 202.68 seconds
Started Dec 31 12:33:42 PM PST 23
Finished Dec 31 12:37:06 PM PST 23
Peak memory 200736 kb
Host smart-fa7fac8c-9164-44c2-bae6-36e4d9fa2cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172520261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.2172520261
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.2375374783
Short name T162
Test name
Test status
Simulation time 160746461056 ps
CPU time 190.01 seconds
Started Dec 31 12:33:37 PM PST 23
Finished Dec 31 12:36:49 PM PST 23
Peak memory 200804 kb
Host smart-25569c05-526b-4497-8bf9-e6052f81dcda
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375374783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.2375374783
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.3637428356
Short name T648
Test name
Test status
Simulation time 331519889753 ps
CPU time 190.51 seconds
Started Dec 31 12:33:44 PM PST 23
Finished Dec 31 12:36:56 PM PST 23
Peak memory 200732 kb
Host smart-8ea64cf2-2383-4da4-8194-38fd9f8801eb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637428356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.3637428356
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.1733887254
Short name T565
Test name
Test status
Simulation time 495496692336 ps
CPU time 1198.5 seconds
Started Dec 31 12:33:49 PM PST 23
Finished Dec 31 12:53:49 PM PST 23
Peak memory 200740 kb
Host smart-7c1ddfaf-cf71-44f2-8391-93aab22a2790
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733887254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.1733887254
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.4024011921
Short name T797
Test name
Test status
Simulation time 87813026604 ps
CPU time 453.12 seconds
Started Dec 31 12:33:40 PM PST 23
Finished Dec 31 12:41:15 PM PST 23
Peak memory 201148 kb
Host smart-3287cf63-3d71-452c-bc97-8b98108a2866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024011921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.4024011921
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.2173388082
Short name T524
Test name
Test status
Simulation time 44636307863 ps
CPU time 23.79 seconds
Started Dec 31 12:33:47 PM PST 23
Finished Dec 31 12:34:12 PM PST 23
Peak memory 199868 kb
Host smart-f435cb6e-f5e8-42d2-b930-0729c489a1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173388082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.2173388082
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.1593684050
Short name T420
Test name
Test status
Simulation time 3889322201 ps
CPU time 9.79 seconds
Started Dec 31 12:33:37 PM PST 23
Finished Dec 31 12:33:49 PM PST 23
Peak memory 200616 kb
Host smart-57712074-1623-42ca-8f20-20057fc672ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593684050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.1593684050
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.2939229453
Short name T710
Test name
Test status
Simulation time 5791386570 ps
CPU time 7.22 seconds
Started Dec 31 12:33:39 PM PST 23
Finished Dec 31 12:33:49 PM PST 23
Peak memory 200560 kb
Host smart-76f80173-5bdc-49ff-8012-9976473bda94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939229453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.2939229453
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.3041205849
Short name T824
Test name
Test status
Simulation time 29381280178 ps
CPU time 86.46 seconds
Started Dec 31 12:33:40 PM PST 23
Finished Dec 31 12:35:08 PM PST 23
Peak memory 209400 kb
Host smart-7b5c48ff-fa10-4961-8d8f-ef4ba3719dcf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041205849 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.3041205849
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.2775283087
Short name T615
Test name
Test status
Simulation time 436777447 ps
CPU time 1.58 seconds
Started Dec 31 12:32:11 PM PST 23
Finished Dec 31 12:32:14 PM PST 23
Peak memory 200792 kb
Host smart-bf457e1c-ef5e-4a9e-9012-470f4a56b3e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775283087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.2775283087
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.4183545197
Short name T712
Test name
Test status
Simulation time 167379088135 ps
CPU time 73.92 seconds
Started Dec 31 12:32:15 PM PST 23
Finished Dec 31 12:33:31 PM PST 23
Peak memory 200724 kb
Host smart-3952b89e-f058-4f5f-bcea-18adb6b319a0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183545197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.4183545197
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.3602315380
Short name T298
Test name
Test status
Simulation time 489883453814 ps
CPU time 1174.41 seconds
Started Dec 31 12:32:14 PM PST 23
Finished Dec 31 12:51:50 PM PST 23
Peak memory 200844 kb
Host smart-d9d23978-6a5f-4588-af8d-26aaaa137002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602315380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.3602315380
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.1437235514
Short name T173
Test name
Test status
Simulation time 340203398139 ps
CPU time 809.8 seconds
Started Dec 31 12:32:13 PM PST 23
Finished Dec 31 12:45:44 PM PST 23
Peak memory 200732 kb
Host smart-7ce34f46-bedb-4f6e-974f-9b7d75d58031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437235514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.1437235514
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.2178927523
Short name T728
Test name
Test status
Simulation time 321814937532 ps
CPU time 383.24 seconds
Started Dec 31 12:31:54 PM PST 23
Finished Dec 31 12:38:18 PM PST 23
Peak memory 200736 kb
Host smart-338f980f-b4a1-4f4a-b215-5424aadfc823
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178927523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.2178927523
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.3583649660
Short name T196
Test name
Test status
Simulation time 161039070417 ps
CPU time 86.39 seconds
Started Dec 31 12:32:17 PM PST 23
Finished Dec 31 12:33:45 PM PST 23
Peak memory 200652 kb
Host smart-90211e4e-d2dd-4bd3-8890-4d8bf22ee87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583649660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.3583649660
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.1879841699
Short name T18
Test name
Test status
Simulation time 330181668904 ps
CPU time 118.57 seconds
Started Dec 31 12:32:14 PM PST 23
Finished Dec 31 12:34:15 PM PST 23
Peak memory 200704 kb
Host smart-29ffa3b4-a69f-4c0e-ab89-1b59df8139c8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879841699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.1879841699
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.4125655718
Short name T264
Test name
Test status
Simulation time 168031141090 ps
CPU time 341.47 seconds
Started Dec 31 12:32:16 PM PST 23
Finished Dec 31 12:37:59 PM PST 23
Peak memory 200756 kb
Host smart-e0ff9ede-0c6b-4411-b9a8-9cb2d2620cd2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125655718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.4125655718
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.1034180571
Short name T154
Test name
Test status
Simulation time 332121464418 ps
CPU time 198.92 seconds
Started Dec 31 12:32:06 PM PST 23
Finished Dec 31 12:35:26 PM PST 23
Peak memory 200700 kb
Host smart-d82dab8e-66d4-4ab9-ad39-e8de02848438
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034180571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.1034180571
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.3920675573
Short name T13
Test name
Test status
Simulation time 112290726309 ps
CPU time 394.86 seconds
Started Dec 31 12:32:01 PM PST 23
Finished Dec 31 12:38:38 PM PST 23
Peak memory 201204 kb
Host smart-f296ea7c-bdf0-49ba-bec1-34440cd8b9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920675573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.3920675573
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.1042171800
Short name T476
Test name
Test status
Simulation time 35398321864 ps
CPU time 30.58 seconds
Started Dec 31 12:32:21 PM PST 23
Finished Dec 31 12:32:58 PM PST 23
Peak memory 200620 kb
Host smart-12c8b640-aea4-4817-9e58-389584338bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042171800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.1042171800
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.1973897100
Short name T578
Test name
Test status
Simulation time 3846157399 ps
CPU time 9.86 seconds
Started Dec 31 12:32:18 PM PST 23
Finished Dec 31 12:32:30 PM PST 23
Peak memory 200536 kb
Host smart-b8839af6-4334-4b28-b782-42cab4f3a1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973897100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.1973897100
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.2757592885
Short name T549
Test name
Test status
Simulation time 5547045022 ps
CPU time 2.68 seconds
Started Dec 31 12:32:24 PM PST 23
Finished Dec 31 12:32:30 PM PST 23
Peak memory 200496 kb
Host smart-6832192f-53c0-4eb8-a560-570331db9599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757592885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.2757592885
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.2673525529
Short name T175
Test name
Test status
Simulation time 6595782536 ps
CPU time 4.64 seconds
Started Dec 31 12:31:57 PM PST 23
Finished Dec 31 12:32:03 PM PST 23
Peak memory 200612 kb
Host smart-2a704eba-6acd-40fb-bd75-57774f958bfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673525529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
2673525529
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.2570806567
Short name T289
Test name
Test status
Simulation time 129744305151 ps
CPU time 121.77 seconds
Started Dec 31 12:32:00 PM PST 23
Finished Dec 31 12:34:03 PM PST 23
Peak memory 208972 kb
Host smart-56757dea-4a0f-4c60-82bd-cc52890d1cce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570806567 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.2570806567
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.1889908401
Short name T433
Test name
Test status
Simulation time 419642852 ps
CPU time 0.79 seconds
Started Dec 31 12:32:22 PM PST 23
Finished Dec 31 12:32:28 PM PST 23
Peak memory 200468 kb
Host smart-26421c02-6d18-4f1d-8401-1fa99aa67180
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889908401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.1889908401
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.4171131983
Short name T239
Test name
Test status
Simulation time 169599654299 ps
CPU time 153.16 seconds
Started Dec 31 12:32:04 PM PST 23
Finished Dec 31 12:34:38 PM PST 23
Peak memory 200812 kb
Host smart-d6c98c2d-21ce-432d-a915-e844bbd7f1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171131983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.4171131983
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.2882224353
Short name T106
Test name
Test status
Simulation time 327167447510 ps
CPU time 196.97 seconds
Started Dec 31 12:32:04 PM PST 23
Finished Dec 31 12:35:22 PM PST 23
Peak memory 200792 kb
Host smart-66c9adb6-0866-4fb5-a76b-1f662ecae693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882224353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.2882224353
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.363454763
Short name T539
Test name
Test status
Simulation time 489871755408 ps
CPU time 1076.15 seconds
Started Dec 31 12:32:32 PM PST 23
Finished Dec 31 12:50:30 PM PST 23
Peak memory 200680 kb
Host smart-45c3c773-191e-4967-9a30-1c136d8ca0d2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=363454763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt
_fixed.363454763
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.3516797329
Short name T57
Test name
Test status
Simulation time 325838468778 ps
CPU time 681.93 seconds
Started Dec 31 12:32:04 PM PST 23
Finished Dec 31 12:43:27 PM PST 23
Peak memory 200716 kb
Host smart-ddead77d-24a4-46c9-be88-be0a93e337af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516797329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.3516797329
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.3448764334
Short name T852
Test name
Test status
Simulation time 157674116845 ps
CPU time 92.97 seconds
Started Dec 31 12:32:16 PM PST 23
Finished Dec 31 12:33:51 PM PST 23
Peak memory 200716 kb
Host smart-4e6ec4b4-f5ea-4884-8b30-ae09ad39c811
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448764334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.3448764334
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.985295434
Short name T23
Test name
Test status
Simulation time 481366098878 ps
CPU time 1067.3 seconds
Started Dec 31 12:32:25 PM PST 23
Finished Dec 31 12:50:15 PM PST 23
Peak memory 200828 kb
Host smart-02e264a5-ec8a-4709-a5ed-bd9c432aae6f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985295434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.a
dc_ctrl_filters_wakeup_fixed.985295434
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.2712608359
Short name T784
Test name
Test status
Simulation time 110045794818 ps
CPU time 385.14 seconds
Started Dec 31 12:32:05 PM PST 23
Finished Dec 31 12:38:32 PM PST 23
Peak memory 201104 kb
Host smart-ea9fd003-b6df-4976-8184-69b88610c46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712608359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.2712608359
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.190198859
Short name T111
Test name
Test status
Simulation time 39631660637 ps
CPU time 89.74 seconds
Started Dec 31 12:32:36 PM PST 23
Finished Dec 31 12:34:07 PM PST 23
Peak memory 200620 kb
Host smart-1bf8cdb0-31af-4702-849e-dc2aa9a1ef1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190198859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.190198859
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.3225865884
Short name T831
Test name
Test status
Simulation time 4940642834 ps
CPU time 1.52 seconds
Started Dec 31 12:32:42 PM PST 23
Finished Dec 31 12:32:44 PM PST 23
Peak memory 200640 kb
Host smart-eb98f4d7-1aca-4279-9817-00b5d868c90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225865884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.3225865884
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.4252009561
Short name T724
Test name
Test status
Simulation time 5819756686 ps
CPU time 4.11 seconds
Started Dec 31 12:32:06 PM PST 23
Finished Dec 31 12:32:11 PM PST 23
Peak memory 200584 kb
Host smart-68c9f43f-3558-4bec-96c4-5fa3c0cd9018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252009561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.4252009561
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.1406645909
Short name T86
Test name
Test status
Simulation time 565789791132 ps
CPU time 816.05 seconds
Started Dec 31 12:32:07 PM PST 23
Finished Dec 31 12:45:43 PM PST 23
Peak memory 210960 kb
Host smart-e3abeb00-8faf-4e43-ab09-7165e62638c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406645909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
1406645909
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.693979685
Short name T40
Test name
Test status
Simulation time 133637163328 ps
CPU time 145.29 seconds
Started Dec 31 12:32:07 PM PST 23
Finished Dec 31 12:34:33 PM PST 23
Peak memory 209364 kb
Host smart-d9ecd774-76c8-4473-a8c9-98d26ded7dab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693979685 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.693979685
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.1325572536
Short name T755
Test name
Test status
Simulation time 556471633 ps
CPU time 0.76 seconds
Started Dec 31 12:32:23 PM PST 23
Finished Dec 31 12:32:28 PM PST 23
Peak memory 200504 kb
Host smart-75381693-de4d-4dc5-96f5-163d86c0b430
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325572536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.1325572536
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.2410433418
Short name T167
Test name
Test status
Simulation time 506366426314 ps
CPU time 374.29 seconds
Started Dec 31 12:32:14 PM PST 23
Finished Dec 31 12:38:30 PM PST 23
Peak memory 200768 kb
Host smart-f97ae743-6511-48c5-b461-08eef76cc83c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410433418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.2410433418
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.3517066364
Short name T90
Test name
Test status
Simulation time 493951273327 ps
CPU time 1011.76 seconds
Started Dec 31 12:32:28 PM PST 23
Finished Dec 31 12:49:23 PM PST 23
Peak memory 200800 kb
Host smart-493b5c3e-6bcd-4709-88da-620904dc12b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517066364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.3517066364
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.2666836653
Short name T557
Test name
Test status
Simulation time 492865102042 ps
CPU time 1147.04 seconds
Started Dec 31 12:32:14 PM PST 23
Finished Dec 31 12:51:23 PM PST 23
Peak memory 200684 kb
Host smart-176f7691-9992-460e-8899-a33aff3f2d4a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666836653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.2666836653
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.3184968937
Short name T726
Test name
Test status
Simulation time 486280685978 ps
CPU time 355.2 seconds
Started Dec 31 12:32:18 PM PST 23
Finished Dec 31 12:38:15 PM PST 23
Peak memory 200812 kb
Host smart-0466cbef-1e75-4977-93b2-c0120603006a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184968937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.3184968937
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.874435587
Short name T423
Test name
Test status
Simulation time 507413539237 ps
CPU time 302.33 seconds
Started Dec 31 12:32:19 PM PST 23
Finished Dec 31 12:37:26 PM PST 23
Peak memory 200716 kb
Host smart-3f29a4d5-c656-4b4b-92c9-0e73beee129c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=874435587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixed
.874435587
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.1252160373
Short name T232
Test name
Test status
Simulation time 492464791849 ps
CPU time 605.9 seconds
Started Dec 31 12:32:26 PM PST 23
Finished Dec 31 12:42:36 PM PST 23
Peak memory 200696 kb
Host smart-784adba2-b906-4bdd-a31c-9c11bcc53b3b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252160373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.1252160373
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.4066207670
Short name T590
Test name
Test status
Simulation time 498537597234 ps
CPU time 1211.66 seconds
Started Dec 31 12:32:07 PM PST 23
Finished Dec 31 12:52:20 PM PST 23
Peak memory 200720 kb
Host smart-0d8e96bb-f699-4361-9762-a6baa038354c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066207670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.4066207670
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.3155639360
Short name T781
Test name
Test status
Simulation time 139535735090 ps
CPU time 688.67 seconds
Started Dec 31 12:32:33 PM PST 23
Finished Dec 31 12:44:04 PM PST 23
Peak memory 201092 kb
Host smart-063960c9-6c97-469f-8db6-c278cc877c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155639360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.3155639360
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.3378413058
Short name T715
Test name
Test status
Simulation time 44817170968 ps
CPU time 112.97 seconds
Started Dec 31 12:31:58 PM PST 23
Finished Dec 31 12:33:52 PM PST 23
Peak memory 200596 kb
Host smart-59e92d61-9c09-439e-90eb-ae1d3398ca54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378413058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.3378413058
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.3804385359
Short name T625
Test name
Test status
Simulation time 2950243977 ps
CPU time 5.24 seconds
Started Dec 31 12:32:06 PM PST 23
Finished Dec 31 12:32:12 PM PST 23
Peak memory 200588 kb
Host smart-94b3080a-7688-496a-92bc-e9675790ce67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804385359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.3804385359
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.1569268213
Short name T822
Test name
Test status
Simulation time 6072649669 ps
CPU time 8.38 seconds
Started Dec 31 12:32:14 PM PST 23
Finished Dec 31 12:32:24 PM PST 23
Peak memory 200560 kb
Host smart-2249b656-d3e4-4845-9bec-778cceb96a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569268213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.1569268213
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.638591434
Short name T829
Test name
Test status
Simulation time 499615455687 ps
CPU time 651.51 seconds
Started Dec 31 12:32:13 PM PST 23
Finished Dec 31 12:43:06 PM PST 23
Peak memory 209384 kb
Host smart-26ff5009-3f8a-4075-b66c-3762fe8a2e64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638591434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.638591434
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.15154849
Short name T188
Test name
Test status
Simulation time 162320837405 ps
CPU time 348.09 seconds
Started Dec 31 12:31:58 PM PST 23
Finished Dec 31 12:37:47 PM PST 23
Peak memory 209424 kb
Host smart-b63122e1-a8d6-4527-be82-1df379841832
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15154849 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.15154849
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.1650414672
Short name T548
Test name
Test status
Simulation time 363942588 ps
CPU time 1.09 seconds
Started Dec 31 12:32:16 PM PST 23
Finished Dec 31 12:32:19 PM PST 23
Peak memory 200548 kb
Host smart-456b435e-842c-4fcd-bb41-2b1f93e86775
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650414672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.1650414672
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.621316139
Short name T800
Test name
Test status
Simulation time 516150408160 ps
CPU time 516.27 seconds
Started Dec 31 12:32:18 PM PST 23
Finished Dec 31 12:40:56 PM PST 23
Peak memory 200720 kb
Host smart-24ae005c-eeac-42af-8673-2de405a5d3c4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621316139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gatin
g.621316139
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.792236504
Short name T161
Test name
Test status
Simulation time 496281318067 ps
CPU time 565.59 seconds
Started Dec 31 12:32:25 PM PST 23
Finished Dec 31 12:41:53 PM PST 23
Peak memory 200748 kb
Host smart-55afd83b-1717-47cb-98b4-883dded0ce42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792236504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.792236504
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.699323261
Short name T143
Test name
Test status
Simulation time 486760220726 ps
CPU time 312.03 seconds
Started Dec 31 12:32:31 PM PST 23
Finished Dec 31 12:37:45 PM PST 23
Peak memory 200772 kb
Host smart-2742596e-301e-46ee-a445-b5b041d915f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699323261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.699323261
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.2008564958
Short name T503
Test name
Test status
Simulation time 327659675605 ps
CPU time 92.52 seconds
Started Dec 31 12:32:12 PM PST 23
Finished Dec 31 12:33:46 PM PST 23
Peak memory 200616 kb
Host smart-3d2c0d85-d3c0-425c-8350-f7e56666739f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008564958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.2008564958
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.346007681
Short name T254
Test name
Test status
Simulation time 493685183190 ps
CPU time 562.27 seconds
Started Dec 31 12:32:32 PM PST 23
Finished Dec 31 12:41:56 PM PST 23
Peak memory 200784 kb
Host smart-7ec7bbd8-3719-44eb-ad5f-5622cd4554b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346007681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.346007681
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.290284331
Short name T492
Test name
Test status
Simulation time 493789946936 ps
CPU time 201.97 seconds
Started Dec 31 12:32:16 PM PST 23
Finished Dec 31 12:35:40 PM PST 23
Peak memory 200852 kb
Host smart-318b3fcf-7364-4d57-adbb-c9122f071332
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=290284331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixed
.290284331
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.4007786559
Short name T242
Test name
Test status
Simulation time 503257833662 ps
CPU time 589.83 seconds
Started Dec 31 12:32:14 PM PST 23
Finished Dec 31 12:42:05 PM PST 23
Peak memory 200752 kb
Host smart-2b10d5c1-8e36-459e-9b00-42296812f8fb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007786559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.4007786559
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.777271422
Short name T576
Test name
Test status
Simulation time 337255119853 ps
CPU time 780.15 seconds
Started Dec 31 12:32:23 PM PST 23
Finished Dec 31 12:45:27 PM PST 23
Peak memory 200708 kb
Host smart-dbcbef8f-4e36-4650-89b5-c7fd8ac74abf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777271422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.a
dc_ctrl_filters_wakeup_fixed.777271422
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.2909488849
Short name T769
Test name
Test status
Simulation time 118059164801 ps
CPU time 627.79 seconds
Started Dec 31 12:32:09 PM PST 23
Finished Dec 31 12:42:38 PM PST 23
Peak memory 201244 kb
Host smart-1afbcff2-0532-43ba-8411-03fbf674f9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909488849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.2909488849
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.1459260126
Short name T591
Test name
Test status
Simulation time 32283656192 ps
CPU time 18.81 seconds
Started Dec 31 12:32:15 PM PST 23
Finished Dec 31 12:32:36 PM PST 23
Peak memory 200572 kb
Host smart-eba1e19b-418f-4e63-81e8-1cca4b5d0189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459260126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.1459260126
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.3479252623
Short name T689
Test name
Test status
Simulation time 4234618289 ps
CPU time 6.09 seconds
Started Dec 31 12:32:03 PM PST 23
Finished Dec 31 12:32:10 PM PST 23
Peak memory 200564 kb
Host smart-02750c43-bc78-4cbb-aead-12c2e8ebf729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479252623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.3479252623
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.3083930799
Short name T540
Test name
Test status
Simulation time 5761487622 ps
CPU time 7.6 seconds
Started Dec 31 12:32:24 PM PST 23
Finished Dec 31 12:32:35 PM PST 23
Peak memory 200536 kb
Host smart-0d5ce5fd-857b-4e2d-9bdf-40d48e62f3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083930799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.3083930799
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.2390245000
Short name T583
Test name
Test status
Simulation time 159664206986 ps
CPU time 160.98 seconds
Started Dec 31 12:32:08 PM PST 23
Finished Dec 31 12:34:50 PM PST 23
Peak memory 217080 kb
Host smart-adc5c09e-22c3-4a83-8921-5cb9f97eed0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390245000 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.2390245000
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.2301979286
Short name T637
Test name
Test status
Simulation time 536986133 ps
CPU time 0.87 seconds
Started Dec 31 12:32:04 PM PST 23
Finished Dec 31 12:32:06 PM PST 23
Peak memory 200476 kb
Host smart-a2ef1e0e-2e57-44c5-9abe-9700c1cd9678
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301979286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.2301979286
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.204102594
Short name T158
Test name
Test status
Simulation time 177254196420 ps
CPU time 224.71 seconds
Started Dec 31 12:32:20 PM PST 23
Finished Dec 31 12:36:11 PM PST 23
Peak memory 200880 kb
Host smart-5a45f898-5db7-4954-b3ec-b616eed312fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204102594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.204102594
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.820735384
Short name T684
Test name
Test status
Simulation time 330676157861 ps
CPU time 190.93 seconds
Started Dec 31 12:32:03 PM PST 23
Finished Dec 31 12:35:15 PM PST 23
Peak memory 200748 kb
Host smart-7f326cf9-db4c-4a72-aa89-c7a161edf360
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=820735384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt
_fixed.820735384
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.101766372
Short name T145
Test name
Test status
Simulation time 487860851871 ps
CPU time 242.46 seconds
Started Dec 31 12:32:09 PM PST 23
Finished Dec 31 12:36:12 PM PST 23
Peak memory 200744 kb
Host smart-0caaebc0-59c0-40ef-99e2-f594f40a2095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101766372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.101766372
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.2830969396
Short name T788
Test name
Test status
Simulation time 334048043913 ps
CPU time 146.34 seconds
Started Dec 31 12:32:10 PM PST 23
Finished Dec 31 12:34:37 PM PST 23
Peak memory 200688 kb
Host smart-3c4779b6-7263-4960-a122-2566a5251cae
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830969396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.2830969396
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.3228376810
Short name T573
Test name
Test status
Simulation time 166519435231 ps
CPU time 101.78 seconds
Started Dec 31 12:32:09 PM PST 23
Finished Dec 31 12:34:02 PM PST 23
Peak memory 200728 kb
Host smart-e094f559-d2a7-461e-b414-0087b088bb25
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228376810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.3228376810
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.2662298275
Short name T346
Test name
Test status
Simulation time 136846492916 ps
CPU time 499.23 seconds
Started Dec 31 12:32:09 PM PST 23
Finished Dec 31 12:40:29 PM PST 23
Peak memory 201332 kb
Host smart-2f1b7992-caa3-40f5-9e0e-929689f9810b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662298275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.2662298275
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.3305909710
Short name T844
Test name
Test status
Simulation time 39594194771 ps
CPU time 92.76 seconds
Started Dec 31 12:32:13 PM PST 23
Finished Dec 31 12:33:48 PM PST 23
Peak memory 200580 kb
Host smart-89045099-48ae-4d53-ac72-6233b025c28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305909710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.3305909710
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.2512245483
Short name T437
Test name
Test status
Simulation time 5753822890 ps
CPU time 12.79 seconds
Started Dec 31 12:32:06 PM PST 23
Finished Dec 31 12:32:20 PM PST 23
Peak memory 200676 kb
Host smart-0745ebc4-18f0-4e37-badf-57057e15c386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512245483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.2512245483
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.3571486982
Short name T765
Test name
Test status
Simulation time 5844343825 ps
CPU time 13.6 seconds
Started Dec 31 12:32:19 PM PST 23
Finished Dec 31 12:32:34 PM PST 23
Peak memory 200588 kb
Host smart-5d67864c-9b0c-4821-a0f0-0e68a37b892f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571486982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.3571486982
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.3546289927
Short name T217
Test name
Test status
Simulation time 169307907863 ps
CPU time 93.26 seconds
Started Dec 31 12:32:16 PM PST 23
Finished Dec 31 12:33:51 PM PST 23
Peak memory 200700 kb
Host smart-14b6fbf3-52b4-49b6-bd82-c12732f834a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546289927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
3546289927
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.3220291136
Short name T97
Test name
Test status
Simulation time 36498606415 ps
CPU time 116.63 seconds
Started Dec 31 12:31:58 PM PST 23
Finished Dec 31 12:33:55 PM PST 23
Peak memory 215908 kb
Host smart-27402c9f-bbc4-4cf6-99bc-7af298c29c4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220291136 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.3220291136
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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