Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6402	1			T12	7		T14	82		T15	9
testmodes[AdcCtrlTestmodeNormal]	5100	1			T11	1		T12	8		T13	2
testmodes[AdcCtrlTestmodeLowpower]	5303	1			T14	76		T15	49		T16	2
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3494	1			T12	1		T14	44		T15	2
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1634	1			T12	6		T14	16		T15	7
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1170	1			T14	22		T21	1		T22	4
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1601	1			T12	5		T14	20		T15	6
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1917	1			T12	2		T13	1		T14	16
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1229	1			T14	17		T15	2		T22	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1194	1			T14	18		T15	1		T22	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1208	1			T14	21		T15	2		T21	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2673	1			T14	36		T15	46		T16	1