Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24282

1

T5

3

T24

2

T25

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20966

1

T5

3

T24

2

T25

1

auto[ADC_CTRL_FILTER_COND_OUT]

3316

1

T13

10

T14

37

T15

29

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18892

1

T5

3

T24

2

T25

1

auto[1]

5390

1

T11

1

T13

10

T15

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20268

1

T11

1

T12

15

T13

2

auto[1]

4014

1

T5

3

T24

2

T25

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	13	1			T200	12		T201	1		-	-
values[0]	69	1			T94	10		T202	17		T120	6
values[1]	566	1			T15	7		T16	8		T103	10
values[2]	734	1			T15	9		T21	1		T22	10
values[3]	689	1			T13	2		T14	17		T203	5
values[4]	536	1			T34	33		T204	3		T96	28
values[5]	2568	1			T11	1		T20	33		T23	1
values[6]	526	1			T16	1		T57	15		T59	16
values[7]	670	1			T14	20		T15	13		T60	31
values[8]	641	1			T13	10		T21	14		T109	9
values[9]	1353	1			T19	8		T61	16		T91	1
minimum	15917	1			T5	3		T24	2		T25	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	876	1			T15	16		T16	8		T21	1
values[1]	593	1			T14	17		T22	10		T203	5
values[2]	642	1			T13	2		T205	34		T204	3
values[3]	2559	1			T11	1		T20	33		T23	1
values[4]	629	1			T104	14		T206	34		T207	1
values[5]	501	1			T16	1		T57	15		T59	16
values[6]	745	1			T14	20		T15	13		T21	14
values[7]	659	1			T13	10		T91	4		T109	9
values[8]	1001	1			T19	8		T61	16		T91	1
values[9]	159	1			T208	1		T209	7		T210	3
minimum	15918	1			T5	3		T24	2		T25	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20819

1

T5

3

T24

2

T25

1

auto[1]

3463

1

T14

18

T15

15

T16

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T16	8		T21	1		T211	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T15	8		T103	1		T94	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T203	2		T205	5		T120	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T14	9		T22	8		T106	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T13	1		T205	13		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T204	2		T212	9		T130	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1210	1			T11	1		T20	33		T23	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T54	1		T34	15		T203	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T177	3		T100	1		T213	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T104	1		T206	16		T207	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T16	1		T57	9		T120	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T59	1		T34	1		T214	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T60	9		T95	9		T141	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T14	11		T15	11		T21	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T109	9		T96	8		T122	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T13	1		T91	3		T55	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T57	14		T184	1		T97	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T19	4		T61	9		T91	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T208	1		T210	1		T215	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T209	1		T216	15		T217	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15775	1			T12	15		T14	209		T15	65
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T141	9		T218	14		T219	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T15	8		T103	9		T94	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T203	3		T169	17		T220	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T14	8		T22	2		T106	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T13	1		T205	21		T174	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T204	1		T212	8		T130	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	992	1			T121	12		T140	12		T221	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T54	10		T34	18		T203	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T213	3		T222	2		T152	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T104	13		T206	18		T223	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T57	6		T224	10		T125	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T59	15		T34	1		T218	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T60	5		T95	11		T110	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T14	9		T15	2		T21	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T125	3		T225	19		T226	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T13	9		T91	1		T55	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T57	12		T184	14		T97	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T19	4		T61	7		T206	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T210	2		T215	7		T227	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T209	6		T216	16		T217	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	3		T24	2		T25	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T200	1		T201	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T120	6		T201	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T94	3		T202	17		T200	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T16	8		T208	1		T141	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T15	4		T103	1		T97	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T21	1		T205	5		T211	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T15	4		T22	8		T95	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T13	1		T203	2		T205	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T14	9		T214	13		T130	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T228	3		T219	1		T210	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T34	15		T204	2		T96	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1202	1			T11	1		T20	33		T23	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T54	1		T104	1		T206	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T16	1		T57	9		T224	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T59	1		T34	1		T207	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T60	9		T95	9		T110	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T14	11		T15	11		T60	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T109	9		T141	8		T96	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T13	1		T21	1		T55	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	341	1			T57	14		T208	1		T184	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T19	4		T61	9		T91	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15774	1			T12	15		T14	209		T15	65
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T200	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T201	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T94	7		T200	8		T229	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T141	9		T218	14		T219	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T15	3		T103	9		T97	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T230	11		T220	4		T231	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T15	5		T22	2		T95	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T13	1		T203	3		T205	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T14	8		T214	11		T130	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T228	7		T219	12		T210	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T34	18		T204	1		T96	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	994	1			T121	12		T140	12		T221	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T54	10		T104	13		T206	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T57	6		T224	10		T232	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T59	15		T34	1		T223	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T60	5		T95	11		T110	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T14	9		T15	2		T60	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T225	19		T153	11		T233	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T13	9		T21	13		T55	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T57	12		T184	14		T97	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	391	1			T19	4		T61	7		T206	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	3		T24	2		T25	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T16	1		T21	1		T211	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T15	11		T103	10		T94	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T203	5		T205	1		T120	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T14	9		T22	8		T106	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T13	2		T205	23		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T204	2		T212	9		T130	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1323	1			T11	1		T20	3		T23	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T54	11		T34	19		T203	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T177	1		T100	1		T213	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T104	14		T206	19		T207	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T16	1		T57	7		T120	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T59	16		T34	2		T214	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T60	6		T95	12		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T14	10		T15	3		T21	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T109	1		T96	1		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T13	10		T91	3		T55	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T57	13		T184	15		T97	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T19	5		T61	8		T91	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T208	1		T210	3		T215	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T209	7		T216	17		T217	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15918	1			T5	3		T24	2		T25	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T16	7		T211	2		T141	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T15	5		T94	2		T95	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T205	4		T120	10		T169	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T14	8		T22	2		T106	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T205	11		T118	10		T234	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T204	1		T212	8		T130	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	879	1			T20	30		T235	5		T236	26
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T34	14		T203	2		T96	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T177	2		T222	7		T237	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T206	15		T98	9		T223	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T57	8		T120	7		T224	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T218	2		T169	7		T238	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T60	8		T95	8		T141	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T14	10		T15	10		T60	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T109	8		T96	7		T122	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T91	1		T55	4		T107	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T57	13		T98	4		T118	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T19	3		T61	8		T206	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T227	4		T239	10		T240	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T216	14		T217	2		T241	16

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T200	12		T201	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T120	1		T201	14		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T94	8		T202	1		T200	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T16	1		T208	1		T141	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T15	5		T103	10		T97	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T21	1		T205	1		T211	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T15	6		T22	8		T95	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T13	2		T203	5		T205	23
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T14	9		T214	12		T130	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T228	8		T219	13		T210	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T34	19		T204	2		T96	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1318	1			T11	1		T20	3		T23	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T54	11		T104	14		T206	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T16	1		T57	7		T224	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T59	16		T34	2		T207	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T60	6		T95	12		T110	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T14	10		T15	3		T60	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T109	1		T141	1		T96	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T13	10		T21	14		T55	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	385	1			T57	13		T208	1		T184	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	461	1			T19	5		T61	8		T91	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15917	1			T5	3		T24	2		T25	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T120	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T94	2		T202	16		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T16	7		T141	8		T218	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T15	2		T98	4		T160	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T205	4		T211	2		T118	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T15	3		T22	2		T95	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T205	11		T120	10		T234	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T14	8		T214	12		T130	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T228	2		T222	7		T242	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T34	14		T204	1		T96	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	878	1			T20	30		T235	5		T236	26
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T206	15		T203	2		T98	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T57	8		T224	10		T232	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T223	4		T238	2		T243	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T60	8		T95	8		T110	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T14	10		T15	10		T60	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T109	8		T141	7		T96	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T55	4		T96	12		T158	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T57	13		T98	4		T118	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T19	3		T61	8		T206	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20819

1

T5

3

T24

2

T25

1

auto[1]

auto[0]

3463

1

T14

18

T15

15

T16

7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24282

1

T5

3

T24

2

T25

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21033

1

T5

3

T24

2

T25

1

auto[ADC_CTRL_FILTER_COND_OUT]

3249

1

T13

10

T14

37

T16

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18654

1

T5

3

T24

2

T25

1

auto[1]

5628

1

T11

1

T13

2

T14

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20268

1

T11

1

T12

15

T13

2

auto[1]

4014

1

T5

3

T24

2

T25

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	30	1			T244	30		-	-		-	-
values[0]	77	1			T115	12		T111	14		T245	1
values[1]	653	1			T55	19		T34	1		T206	23
values[2]	702	1			T16	1		T34	33		T130	1
values[3]	560	1			T14	17		T19	8		T60	17
values[4]	603	1			T13	2		T103	10		T95	23
values[5]	628	1			T60	14		T91	4		T57	26
values[6]	418	1			T59	9		T214	1		T96	28
values[7]	577	1			T14	20		T15	9		T16	8
values[8]	666	1			T15	7		T22	10		T59	16
values[9]	3451	1			T11	1		T13	10		T15	13
minimum	15917	1			T5	3		T24	2		T25	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	869	1			T16	1		T55	19		T34	1
values[1]	667	1			T19	8		T61	16		T57	15
values[2]	690	1			T14	17		T60	17		T103	10
values[3]	544	1			T13	2		T91	4		T208	2
values[4]	516	1			T60	14		T57	26		T207	1
values[5]	495	1			T15	9		T16	8		T21	1
values[6]	2632	1			T11	1		T14	20		T20	33
values[7]	703	1			T15	7		T22	10		T91	1
values[8]	992	1			T13	10		T21	14		T109	9
values[9]	244	1			T15	13		T54	11		T246	1
minimum	15930	1			T5	3		T24	2		T25	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20819

1

T5

3

T24

2

T25

1

auto[1]

3463

1

T14

18

T15

15

T16

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T16	1		T55	5		T34	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T115	8		T107	3		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T57	9		T108	1		T99	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T19	4		T61	9		T214	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T184	1		T98	5		T122	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T14	9		T60	9		T103	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T13	1		T91	3		T208	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T149	1		T179	1		T247	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T207	1		T212	9		T96	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T60	9		T57	14		T205	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T15	4		T21	1		T214	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T16	8		T123	14		T120	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1251	1			T11	1		T20	33		T23	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T14	11		T59	1		T203	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T15	4		T22	8		T94	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T91	1		T59	1		T94	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T21	1		T109	9		T34	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T13	1		T206	16		T95	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T15	11		T125	6		T248	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T54	1		T246	1		T179	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15787	1			T12	15		T14	209		T15	65
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T55	14		T206	11		T141	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T115	4		T107	3		T228	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T57	6		T99	14		T209	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T19	4		T61	7		T214	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T184	14		T218	7		T249	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T14	8		T60	8		T103	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T13	1		T91	1		T250	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T179	3		T169	11		T174	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T212	8		T96	17		T230	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T60	5		T57	12		T205	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T15	5		T101	13		T169	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T251	1		T215	7		T216	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1053	1			T121	12		T140	12		T221	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T14	9		T59	8		T203	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T15	3		T22	2		T94	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T59	15		T94	7		T224	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T21	13		T34	1		T203	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T13	9		T206	18		T95	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T15	2		T125	3		T248	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T54	10		T179	12		T213	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	3		T24	2		T25	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T244	15		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T111	1		T252	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T115	8		T245	1		T156	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T55	5		T34	1		T206	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T107	3		T228	3		T219	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T16	1		T99	6		T209	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T34	15		T130	1		T112	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T57	9		T98	5		T108	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T14	9		T19	4		T60	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T13	1		T208	1		T184	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T103	1		T95	13		T97	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T91	3		T207	1		T212	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T60	9		T57	14		T205	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T214	1		T96	11		T101	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T59	1		T113	1		T247	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T15	4		T21	1		T205	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T14	11		T16	8		T203	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T15	4		T22	8		T203	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T59	1		T94	3		T96	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1422	1			T11	1		T15	11		T20	33
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	415	1			T13	1		T91	1		T54	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15774	1			T12	15		T14	209		T15	65
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T244	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T111	13		T252	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T115	4		T156	7		T253	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T55	14		T206	11		T141	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T107	3		T228	7		T219	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T99	14		T209	6		T218	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T34	18		T232	13		T254	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T57	6		T249	15		T152	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T14	8		T19	4		T60	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T13	1		T184	14		T250	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T103	9		T95	10		T97	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T91	1		T212	8		T200	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T60	5		T57	12		T205	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T96	17		T101	13		T230	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T59	8		T216	8		T255	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T15	5		T96	11		T97	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T14	9		T203	3		T110	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T15	3		T22	2		T203	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T59	15		T94	7		T210	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1217	1			T15	2		T21	13		T121	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	397	1			T13	9		T54	10		T206	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	3		T24	2		T25	1