Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24282

1

T5

3

T24

2

T25

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20921

1

T5

3

T24

2

T25

1

auto[ADC_CTRL_FILTER_COND_OUT]

3361

1

T14

17

T15

9

T16

9

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18929

1

T5

3

T24

2

T25

1

auto[1]

5353

1

T11

1

T13

2

T14

20

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20268

1

T11

1

T12

15

T13

2

auto[1]

4014

1

T5

3

T24

2

T25

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	238	1			T13	10		T96	28		T218	26
values[0]	22	1			T233	9		T315	13		-	-
values[1]	725	1			T60	17		T95	20		T205	15
values[2]	585	1			T14	20		T19	8		T205	24
values[3]	572	1			T15	13		T22	10		T34	2
values[4]	2754	1			T11	1		T15	7		T16	8
values[5]	513	1			T15	9		T34	1		T214	24
values[6]	710	1			T21	1		T109	9		T54	11
values[7]	661	1			T14	17		T60	14		T103	10
values[8]	549	1			T16	1		T57	15		T206	34
values[9]	1036	1			T13	2		T21	14		T61	16
minimum	15917	1			T5	3		T24	2		T25	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	705	1			T60	17		T95	20		T205	5
values[1]	656	1			T14	20		T19	8		T22	10
values[2]	504	1			T15	13		T55	19		T34	2
values[3]	2785	1			T11	1		T15	16		T16	8
values[4]	475	1			T109	9		T95	23		T214	24
values[5]	774	1			T21	1		T54	11		T57	26
values[6]	628	1			T14	17		T16	1		T60	14
values[7]	546	1			T206	34		T115	12		T208	2
values[8]	927	1			T13	10		T21	14		T61	16
values[9]	164	1			T13	2		T213	4		T280	13
minimum	16118	1			T5	3		T24	2		T25	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20819

1

T5

3

T24

2

T25

1

auto[1]

3463

1

T14

18

T15

15

T16

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T60	9		T205	5		T101	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T95	9		T204	2		T123	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T14	11		T19	4		T205	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T22	8		T97	1		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T15	11		T34	1		T122	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T55	5		T184	1		T177	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1354	1			T11	1		T15	4		T20	33
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T15	4		T16	8		T91	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T95	13		T212	9		T97	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T109	9		T214	13		T202	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T21	1		T57	14		T104	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T54	1		T203	2		T158	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T103	1		T141	8		T209	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T14	9		T16	1		T60	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T206	16		T115	8		T208	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T208	1		T100	1		T118	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T13	1		T61	9		T34	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T21	1		T207	1		T208	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T13	1		T280	1		T242	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T213	1		T284	15		T316	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15811	1			T12	15		T14	209		T15	65
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T205	3		T141	9		T218	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T60	8		T101	13		T215	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T95	11		T204	1		T179	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T14	9		T19	4		T205	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T22	2		T97	10		T124	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T15	2		T34	1		T179	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T55	14		T184	14		T111	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1058	1			T15	3		T121	12		T140	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T15	5		T59	8		T94	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T95	10		T212	8		T97	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T214	11		T260	2		T200	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T57	12		T104	13		T272	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T54	10		T203	3		T280	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T103	9		T209	6		T231	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T14	8		T60	5		T91	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T206	18		T115	4		T99	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T228	7		T111	9		T224	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T13	9		T61	7		T34	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T21	13		T96	28		T110	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T13	1		T280	12		T242	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T213	3		T284	13		T316	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T5	3		T24	2		T25	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T205	12		T141	9		T218	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T13	1		T280	1		T190	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T96	11		T218	12		T112	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T233	1		T315	8		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T60	9		T101	9		T251	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T95	9		T205	3		T141	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T14	11		T19	4		T205	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T204	2		T97	1		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T15	11		T34	1		T122	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T22	8		T184	1		T111	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1326	1			T11	1		T15	4		T20	33
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T16	8		T91	1		T55	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T212	9		T97	1		T130	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T15	4		T34	1		T214	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T21	1		T57	14		T95	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T109	9		T54	1		T203	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T103	1		T104	1		T141	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T14	9		T60	9		T91	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T206	16		T209	1		T120	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T16	1		T57	9		T100	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T13	1		T61	9		T34	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T21	1		T207	1		T208	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15774	1			T12	15		T14	209		T15	65
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T13	9		T280	12		T242	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T96	17		T218	14		T215	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T233	8		T315	5		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T60	8		T101	13		T251	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T95	11		T205	12		T141	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T14	9		T19	4		T205	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T204	1		T97	10		T124	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T15	2		T34	1		T179	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T22	2		T184	14		T111	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1056	1			T15	3		T121	12		T140	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T55	14		T59	8		T94	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T212	8		T97	8		T130	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T15	5		T214	11		T260	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T57	12		T95	10		T272	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T54	10		T203	3		T223	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T103	9		T104	13		T231	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T14	8		T60	5		T91	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T206	18		T209	6		T271	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T57	6		T228	7		T111	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T13	1		T61	7		T34	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T21	13		T96	11		T110	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	3		T24	2		T25	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T60	9		T205	1		T101	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T95	12		T204	2		T123	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T14	10		T19	5		T205	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T22	8		T97	11		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T15	3		T34	2		T122	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T55	15		T184	15		T177	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1402	1			T11	1		T15	5		T20	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T15	6		T16	1		T91	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T95	11		T212	9		T97	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T109	1		T214	12		T202	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T21	1		T57	13		T104	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T54	11		T203	5		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T103	10		T141	1		T209	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T14	9		T16	1		T60	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T206	19		T115	5		T208	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T208	1		T100	1		T118	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T13	10		T61	8		T34	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T21	14		T207	1		T208	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T13	2		T280	13		T242	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T213	4		T284	14		T316	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15946	1			T5	3		T24	2		T25	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T205	13		T141	10		T218	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T60	8		T205	4		T101	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T95	8		T204	1		T123	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T14	10		T19	3		T205	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T22	2		T124	3		T250	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T15	10		T122	2		T174	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T55	4		T177	2		T144	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1010	1			T15	2		T20	30		T235	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T15	3		T16	7		T94	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T95	12		T212	8		T130	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T109	8		T214	12		T202	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T57	13		T234	14		T143	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T158	11		T120	5		T223	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T141	7		T271	2		T151	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T14	8		T60	8		T91	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T206	15		T115	7		T99	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T118	9		T228	2		T270	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T61	8		T34	14		T206	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T96	22		T110	10		T218	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T242	2		T317	6		T244	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T284	14		T316	16		T318	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T232	2		T302	8		T319	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T205	2		T141	8		T218	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T13	10		T280	13		T190	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T96	18		T218	15		T112	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T233	9		T315	6		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T60	9		T101	14		T251	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T95	12		T205	13		T141	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T14	10		T19	5		T205	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T204	2		T97	11		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T15	3		T34	2		T122	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T22	8		T184	15		T111	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1393	1			T11	1		T15	5		T20	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T16	1		T91	1		T55	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T212	9		T97	9		T130	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T15	6		T34	1		T214	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T21	1		T57	13		T95	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T109	1		T54	11		T203	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T103	10		T104	14		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T14	9		T60	6		T91	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T206	19		T209	7		T120	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T16	1		T57	7		T100	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T13	2		T61	8		T34	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T21	14		T207	1		T208	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15917	1			T5	3		T24	2		T25	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T242	2		T317	6		T309	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T96	10		T218	11		T174	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T315	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T60	8		T101	8		T232	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T95	8		T205	2		T141	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T14	10		T19	3		T205	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T204	1		T123	13		T124	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T15	10		T122	2		T174	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T22	2		T250	14		T225	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	989	1			T15	2		T20	30		T235	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T16	7		T55	4		T94	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T212	8		T130	11		T118	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T15	3		T214	12		T98	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T57	13		T95	12		T234	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T109	8		T158	11		T120	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T141	7		T151	22		T227	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T14	8		T60	8		T91	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T206	15		T120	7		T320	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T57	8		T118	9		T228	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T61	8		T34	14		T206	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T96	12		T110	10		T276	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20819

1

T5

3

T24

2

T25

1

auto[1]

auto[0]

3463

1

T14

18

T15

15

T16

7