Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24282

1

T5

3

T24

2

T25

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20921

1

T5

3

T24

2

T25

1

auto[ADC_CTRL_FILTER_COND_OUT]

3361

1

T14

17

T15

9

T16

9

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18913

1

T5

3

T24

2

T25

1

auto[1]

5369

1

T11

1

T13

2

T14

20

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20268

1

T11

1

T12

15

T13

2

auto[1]

4014

1

T5

3

T24

2

T25

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	6	1			T112	1		T126	1		T238	3
values[0]	79	1			T218	10		T280	15		T273	16
values[1]	629	1			T60	17		T95	20		T205	20
values[2]	631	1			T14	20		T19	8		T211	3
values[3]	566	1			T15	13		T22	10		T34	2
values[4]	2691	1			T11	1		T15	7		T16	8
values[5]	569	1			T15	9		T214	24		T212	17
values[6]	676	1			T21	1		T109	9		T54	11
values[7]	666	1			T14	17		T60	14		T103	10
values[8]	560	1			T16	1		T57	15		T206	34
values[9]	1292	1			T13	12		T21	14		T61	16
minimum	15917	1			T5	3		T24	2		T25	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	879	1			T60	17		T95	20		T205	20
values[1]	662	1			T14	20		T19	8		T22	10
values[2]	508	1			T15	13		T55	19		T59	9
values[3]	2774	1			T11	1		T15	16		T16	8
values[4]	487	1			T109	9		T95	23		T214	24
values[5]	812	1			T21	1		T54	11		T57	26
values[6]	623	1			T14	17		T60	14		T103	10
values[7]	466	1			T16	1		T206	34		T94	11
values[8]	885	1			T13	10		T21	14		T61	16
values[9]	252	1			T13	2		T34	33		T207	1
minimum	15934	1			T5	3		T24	2		T25	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20819

1

T5

3

T24

2

T25

1

auto[1]

3463

1

T14

18

T15

15

T16

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T60	9		T205	5		T98	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T95	9		T205	3		T204	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T14	11		T19	4		T205	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T22	8		T184	1		T97	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T15	11		T34	1		T122	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T55	5		T59	1		T111	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1351	1			T11	1		T15	4		T20	33
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T15	4		T16	8		T91	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T95	13		T212	9		T97	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T109	9		T214	13		T98	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T21	1		T57	14		T141	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T54	1		T203	2		T158	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T103	1		T104	1		T209	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T14	9		T60	9		T91	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T206	16		T94	1		T115	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T16	1		T208	1		T100	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T13	1		T61	9		T206	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T21	1		T208	1		T96	24
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T13	1		T34	15		T232	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T207	1		T219	1		T213	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15778	1			T12	15		T14	209		T15	65
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T315	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T60	8		T101	13		T251	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T95	11		T205	12		T204	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T14	9		T19	4		T205	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T22	2		T184	14		T97	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T15	2		T34	1		T179	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T55	14		T59	8		T111	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1068	1			T15	3		T121	12		T140	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T15	5		T94	7		T101	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T95	10		T212	8		T97	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T214	11		T260	2		T200	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T57	12		T130	11		T308	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T54	10		T203	3		T280	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T103	9		T104	13		T209	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T14	8		T60	5		T91	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T206	18		T94	10		T115	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T228	7		T111	9		T224	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T13	9		T61	7		T206	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T21	13		T96	28		T110	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T13	1		T34	18		T232	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T219	12		T213	3		T284	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	3		T24	2		T25	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T315	5		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T126	1		T238	3		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T112	1		T300	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T273	16		T243	7		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T218	3		T280	1		T146	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T60	9		T205	5		T101	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T95	9		T205	3		T204	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T14	11		T19	4		T211	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T97	1		T130	1		T108	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T15	11		T34	1		T205	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T22	8		T184	1		T111	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1289	1			T11	1		T15	4		T20	33
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T16	8		T91	1		T55	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T212	9		T97	1		T130	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T15	4		T214	13		T98	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T21	1		T57	14		T95	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T109	9		T54	1		T203	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T103	1		T104	1		T141	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T14	9		T60	9		T91	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T206	16		T209	1		T120	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T16	1		T57	9		T118	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T13	2		T61	9		T34	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T21	1		T207	1		T208	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15774	1			T12	15		T14	209		T15	65
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T243	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T218	7		T280	14		T233	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T60	8		T101	13		T251	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T95	11		T205	12		T204	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T14	9		T19	4		T210	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T97	10		T124	9		T179	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T15	2		T34	1		T205	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T22	2		T184	14		T111	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1044	1			T15	3		T121	12		T140	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T55	14		T59	8		T94	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T212	8		T97	8		T130	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T15	5		T214	11		T101	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T57	12		T95	10		T272	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T54	10		T203	3		T223	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T103	9		T104	13		T231	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T14	8		T60	5		T91	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T206	18		T209	6		T271	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T57	6		T228	7		T224	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T13	10		T61	7		T34	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	391	1			T21	13		T96	28		T110	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	3		T24	2		T25	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T60	9		T205	1		T98	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T95	12		T205	13		T204	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T14	10		T19	5		T205	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T22	8		T184	15		T97	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T15	3		T34	2		T122	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T55	15		T59	9		T111	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1411	1			T11	1		T15	5		T20	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T15	6		T16	1		T91	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T95	11		T212	9		T97	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T109	1		T214	12		T98	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T21	1		T57	13		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T54	11		T203	5		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T103	10		T104	14		T209	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T14	9		T60	6		T91	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T206	19		T94	11		T115	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T16	1		T208	1		T100	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T13	10		T61	8		T206	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T21	14		T208	1		T96	30
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T13	2		T34	19		T232	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T207	1		T219	13		T213	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15919	1			T5	3		T24	2		T25	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T315	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T60	8		T205	4		T98	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T95	8		T205	2		T204	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T14	10		T19	3		T205	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T22	2		T124	3		T250	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T15	10		T122	2		T174	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T55	4		T144	14		T145	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1008	1			T15	2		T20	30		T235	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T15	3		T16	7		T94	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T95	12		T212	8		T118	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T109	8		T214	12		T98	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T57	13		T141	7		T130	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T158	11		T120	5		T223	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T320	11		T271	2		T151	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T14	8		T60	8		T91	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T206	15		T115	7		T120	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T118	9		T228	2		T270	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T61	8		T206	11		T107	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T96	22		T110	10		T218	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T34	14		T232	10		T242	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T284	14		T316	16		T318	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T232	2		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T315	7		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T126	1		T238	3		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T112	1		T300	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T273	1		T243	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T218	8		T280	15		T146	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T60	9		T205	1		T101	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T95	12		T205	13		T204	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T14	10		T19	5		T211	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T97	11		T130	1		T108	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T15	3		T34	2		T205	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T22	8		T184	15		T111	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1378	1			T11	1		T15	5		T20	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T16	1		T91	1		T55	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T212	9		T97	9		T130	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T15	6		T214	12		T98	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T21	1		T57	13		T95	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T109	1		T54	11		T203	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T103	10		T104	14		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T14	9		T60	6		T91	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T206	19		T209	7		T120	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T16	1		T57	7		T118	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	336	1			T13	12		T61	8		T34	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	469	1			T21	14		T207	1		T208	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15917	1			T5	3		T24	2		T25	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T273	15		T243	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T218	2		T278	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T60	8		T205	4		T101	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T95	8		T205	2		T204	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T14	10		T19	3		T211	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T123	13		T124	3		T230	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T15	10		T205	9		T96	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T22	2		T250	14		T225	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	955	1			T15	2		T20	30		T235	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T16	7		T55	4		T94	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T212	8		T130	11		T118	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T15	3		T214	12		T98	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T57	13		T95	12		T143	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T109	8		T158	11		T120	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T141	7		T234	14		T151	22
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T14	8		T60	8		T91	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T206	15		T120	7		T320	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T57	8		T118	9		T228	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T61	8		T34	14		T206	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T96	22		T110	10		T218	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20819

1

T5

3

T24

2

T25

1

auto[1]

auto[0]

3463

1

T14

18

T15

15

T16

7