Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24282

1

T5

3

T24

2

T25

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20772

1

T5

3

T24

2

T25

1

auto[ADC_CTRL_FILTER_COND_OUT]

3510

1

T13

10

T14

17

T15

29

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18990

1

T5

3

T24

2

T25

1

auto[1]

5292

1

T11

1

T13

10

T14

20

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20268

1

T11

1

T12

15

T13

2

auto[1]

4014

1

T5

3

T24

2

T25

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	163	1			T91	1		T206	23		T149	1
values[0]	17	1			T120	6		T229	11		-	-
values[1]	649	1			T15	7		T16	8		T103	10
values[2]	681	1			T14	17		T15	9		T21	1
values[3]	668	1			T13	2		T203	5		T214	24
values[4]	568	1			T34	33		T204	3		T96	28
values[5]	2598	1			T11	1		T20	33		T23	1
values[6]	509	1			T16	1		T57	15		T59	16
values[7]	687	1			T14	20		T15	13		T21	14
values[8]	617	1			T13	10		T109	9		T55	19
values[9]	1208	1			T19	8		T61	16		T57	26
minimum	15917	1			T5	3		T24	2		T25	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	641	1			T15	16		T21	1		T103	10
values[1]	640	1			T14	17		T22	10		T203	5
values[2]	612	1			T13	2		T205	34		T204	3
values[3]	2559	1			T11	1		T20	33		T23	1
values[4]	651	1			T54	11		T104	14		T206	34
values[5]	482	1			T16	1		T57	15		T59	16
values[6]	727	1			T14	20		T15	13		T21	14
values[7]	578	1			T13	10		T109	9		T55	19
values[8]	1109	1			T19	8		T91	1		T57	26
values[9]	134	1			T61	16		T280	15		T215	8
minimum	16149	1			T5	3		T24	2		T25	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20819

1

T5

3

T24

2

T25

1

auto[1]

3463

1

T14

18

T15

15

T16

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T21	1		T211	3		T208	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T15	8		T103	1		T95	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T22	8		T203	2		T205	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T14	9		T106	4		T214	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T13	1		T205	13		T204	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T212	9		T130	12		T321	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1245	1			T11	1		T20	33		T23	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T34	15		T203	4		T96	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T177	3		T100	1		T213	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T54	1		T104	1		T206	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T16	1		T120	8		T224	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T57	9		T59	1		T214	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T14	11		T60	9		T95	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T15	11		T21	1		T60	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T109	9		T96	8		T122	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T13	1		T55	5		T34	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T57	14		T115	8		T208	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T19	4		T91	1		T206	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T215	1		T322	1		T323	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T61	9		T280	1		T216	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15840	1			T12	15		T14	209		T15	65
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T94	3		T108	1		T160	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T141	9		T218	14		T219	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T15	8		T103	9		T95	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T22	2		T203	3		T169	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T14	8		T106	2		T214	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T13	1		T205	21		T204	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T212	8		T130	11		T321	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	999	1			T121	12		T140	12		T221	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T34	18		T203	2		T96	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T213	3		T175	15		T249	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T54	10		T104	13		T206	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T224	10		T125	1		T150	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T57	6		T59	15		T218	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T14	9		T60	5		T95	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T15	2		T21	13		T60	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T125	3		T226	1		T153	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T13	9		T55	14		T179	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T57	12		T115	4		T184	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T19	4		T206	11		T94	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T215	7		T323	4		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T61	7		T280	14		T216	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T5	3		T24	2		T25	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T94	7		T200	8		T324	19

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T149	1		T320	12		T325	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T91	1		T206	12		T223	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T120	6		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T229	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T16	8		T208	1		T141	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T15	4		T103	1		T94	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T21	1		T22	8		T205	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T14	9		T15	4		T106	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T13	1		T203	2		T205	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T214	13		T212	9		T130	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T204	2		T118	7		T228	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T34	15		T96	11		T99	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1197	1			T11	1		T20	33		T23	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T54	1		T104	1		T206	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T16	1		T224	11		T143	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T57	9		T59	1		T207	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T14	11		T60	9		T95	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T15	11		T21	1		T60	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T109	9		T141	8		T96	21
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T13	1		T55	5		T158	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	317	1			T57	14		T115	8		T208	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T19	4		T61	9		T34	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15774	1			T12	15		T14	209		T15	65
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T239	10		T173	8		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T206	11		T223	11		T217	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T229	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T141	9		T97	8		T218	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T15	3		T103	9		T94	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T22	2		T230	11		T231	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T14	8		T15	5		T106	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T13	1		T203	3		T205	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T214	11		T212	8		T130	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T204	1		T228	7		T219	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T34	18		T96	17		T99	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	998	1			T121	12		T140	12		T221	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T54	10		T104	13		T206	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T224	10		T284	13		T170	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T57	6		T59	15		T223	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T14	9		T60	5		T95	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T15	2		T21	13		T60	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T96	11		T226	1		T153	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T13	9		T55	14		T232	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T57	12		T115	4		T184	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	363	1			T19	4		T61	7		T94	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	3		T24	2		T25	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T21	1		T211	1		T208	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T15	11		T103	10		T95	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T22	8		T203	5		T205	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T14	9		T106	5		T214	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T13	2		T205	23		T204	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T212	9		T130	12		T321	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1333	1			T11	1		T20	3		T23	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T34	19		T203	4		T96	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T177	1		T100	1		T213	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T54	11		T104	14		T206	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T16	1		T120	1		T224	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T57	7		T59	16		T214	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T14	10		T60	6		T95	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T15	3		T21	14		T60	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T109	1		T96	1		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T13	10		T55	15		T34	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	323	1			T57	13		T115	5		T208	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	382	1			T19	5		T91	1		T206	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T215	8		T322	1		T323	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T61	8		T280	15		T216	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15974	1			T5	3		T24	2		T25	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T94	8		T108	1		T160	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T211	2		T141	8		T98	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T15	5		T95	12		T202	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T22	2		T205	4		T120	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T14	8		T106	1		T214	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T205	11		T204	1		T234	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T212	8		T130	11		T126	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	911	1			T20	30		T235	5		T236	26
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T34	14		T203	2		T96	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T177	2		T298	9		T326	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T206	15		T98	9		T223	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T120	7		T224	10		T143	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T57	8		T218	2		T169	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T14	10		T60	8		T95	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T15	10		T60	8		T91	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T109	8		T96	7		T122	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T55	4		T270	6		T234	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T57	13		T115	7		T98	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T19	3		T206	11		T118	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T323	9		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T61	8		T216	14		T217	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T16	7		T120	5		T279	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T94	2		T160	6		T327	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T149	1		T320	1		T325	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T91	1		T206	12		T223	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T120	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T229	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T16	1		T208	1		T141	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T15	5		T103	10		T94	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T21	1		T22	8		T205	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T14	9		T15	6		T106	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T13	2		T203	5		T205	23
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T214	12		T212	9		T130	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T204	2		T118	1		T228	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T34	19		T96	18		T99	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1322	1			T11	1		T20	3		T23	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T54	11		T104	14		T206	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T16	1		T224	11		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T57	7		T59	16		T207	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T14	10		T60	6		T95	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T15	3		T21	14		T60	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T109	1		T141	1		T96	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T13	10		T55	15		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	333	1			T57	13		T115	5		T208	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	426	1			T19	5		T61	8		T34	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15917	1			T5	3		T24	2		T25	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T320	11		T239	10		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T206	11		T223	11		T217	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T120	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T16	7		T141	8		T98	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T15	2		T94	2		T95	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T22	2		T205	4		T211	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T14	8		T15	3		T106	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T205	11		T120	10		T234	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T214	12		T212	8		T130	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T204	1		T118	6		T228	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T34	14		T96	10		T99	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	873	1			T20	30		T235	5		T236	26
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T206	15		T203	2		T98	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T224	10		T143	12		T150	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T57	8		T223	4		T169	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T14	10		T60	8		T95	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T15	10		T60	8		T91	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T109	8		T141	7		T96	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T55	4		T158	11		T270	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T57	13		T115	7		T98	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T19	3		T61	8		T118	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20819

1

T5

3

T24

2

T25

1

auto[1]

auto[0]

3463

1

T14

18

T15

15

T16

7