Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24282

1

T5

3

T24

2

T25

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20992

1

T5

3

T24

2

T25

1

auto[ADC_CTRL_FILTER_COND_OUT]

3290

1

T13

10

T14

37

T16

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18592

1

T5

3

T24

2

T25

1

auto[1]

5690

1

T11

1

T13

2

T14

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20268

1

T11

1

T12

15

T13

2

auto[1]

4014

1

T5

3

T24

2

T25

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	267	1			T15	13		T21	14		T206	34
values[0]	13	1			T115	12		T245	1		-	-
values[1]	666	1			T55	19		T34	1		T206	23
values[2]	690	1			T16	1		T19	8		T130	1
values[3]	606	1			T14	17		T60	17		T61	16
values[4]	576	1			T13	2		T103	10		T95	23
values[5]	645	1			T60	14		T91	4		T57	26
values[6]	424	1			T21	1		T59	9		T214	1
values[7]	609	1			T14	20		T15	9		T16	8
values[8]	637	1			T15	7		T22	10		T59	16
values[9]	3232	1			T11	1		T13	10		T20	33
minimum	15917	1			T5	3		T24	2		T25	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	582	1			T16	1		T55	19		T206	23
values[1]	706	1			T19	8		T61	16		T214	24
values[2]	665	1			T14	17		T60	17		T103	10
values[3]	584	1			T13	2		T91	4		T208	2
values[4]	582	1			T60	14		T57	26		T207	1
values[5]	445	1			T15	9		T16	8		T21	1
values[6]	2556	1			T11	1		T14	20		T20	33
values[7]	762	1			T15	7		T22	10		T59	16
values[8]	1079	1			T13	10		T21	14		T91	1
values[9]	140	1			T15	13		T54	11		T179	13
minimum	16181	1			T5	3		T24	2		T25	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20819

1

T5

3

T24

2

T25

1

auto[1]

3463

1

T14

18

T15

15

T16

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T16	1		T55	5		T206	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T107	3		T130	1		T228	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T99	6		T209	1		T118	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T19	4		T61	9		T214	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T57	9		T184	1		T98	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T14	9		T60	9		T103	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T13	1		T91	3		T208	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T97	1		T149	1		T179	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T207	1		T212	9		T96	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T60	9		T57	14		T205	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T15	4		T21	1		T214	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T16	8		T59	1		T123	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1229	1			T11	1		T20	33		T23	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T14	11		T203	2		T110	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T15	4		T22	8		T94	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T59	1		T94	3		T208	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T21	1		T109	9		T34	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	381	1			T13	1		T91	1		T206	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T15	11		T125	6		T176	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T54	1		T179	1		T242	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15856	1			T12	15		T14	209		T15	65
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T115	8		T201	1		T154	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T55	14		T206	11		T141	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T107	3		T228	7		T219	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T99	14		T209	6		T218	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T19	4		T61	7		T214	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T57	6		T184	14		T218	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T14	8		T60	8		T103	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T13	1		T91	1		T250	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T97	15		T179	3		T169	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T212	8		T96	17		T230	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T60	5		T57	12		T205	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T15	5		T101	13		T169	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T59	8		T251	1		T215	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1026	1			T121	12		T140	12		T221	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T14	9		T203	3		T110	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T15	3		T22	2		T94	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T59	15		T94	7		T223	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T21	13		T34	1		T97	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T13	9		T206	18		T95	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T15	2		T125	3		T176	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T54	10		T179	12		T242	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T5	3		T24	2		T25	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T115	4		T154	13		T156	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T15	11		T21	1		T130	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T206	16		T213	1		T200	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T245	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T115	8		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T55	5		T34	1		T206	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T107	3		T228	3		T219	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T16	1		T99	6		T209	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T19	4		T130	1		T112	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T57	9		T98	5		T218	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T14	9		T60	9		T61	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T13	1		T208	2		T184	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T103	1		T95	13		T97	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T91	3		T207	1		T212	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T60	9		T57	14		T205	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T21	1		T214	1		T96	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T59	1		T269	1		T113	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T15	4		T205	5		T141	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T14	11		T16	8		T203	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T15	4		T22	8		T204	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T59	1		T94	3		T96	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1373	1			T11	1		T20	33		T23	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	365	1			T13	1		T91	1		T54	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15774	1			T12	15		T14	209		T15	65
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T15	2		T21	13		T111	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T206	18		T213	3		T200	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T115	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T55	14		T206	11		T141	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T107	3		T228	7		T219	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T99	14		T209	6		T218	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T19	4		T232	13		T254	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T57	6		T218	7		T249	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T14	8		T60	8		T61	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T13	1		T184	14		T250	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T103	9		T95	10		T97	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T91	1		T212	8		T200	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T60	5		T57	12		T205	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T96	17		T230	1		T283	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T59	8		T216	8		T263	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T15	5		T96	11		T97	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T14	9		T203	3		T110	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T15	3		T22	2		T204	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T59	15		T94	7		T223	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1140	1			T121	12		T140	12		T34	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	354	1			T13	9		T54	10		T95	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	3		T24	2		T25	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T16	1		T55	15		T206	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T107	5		T130	1		T228	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T99	15		T209	7		T118	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T19	5		T61	8		T214	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T57	7		T184	15		T98	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T14	9		T60	9		T103	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T13	2		T91	3		T208	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T97	16		T149	1		T179	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T207	1		T212	9		T96	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T60	6		T57	13		T205	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T15	6		T21	1		T214	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T16	1		T59	9		T123	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1353	1			T11	1		T20	3		T23	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T14	10		T203	5		T110	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T15	5		T22	8		T94	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T59	16		T94	8		T208	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T21	14		T109	1		T34	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	396	1			T13	10		T91	1		T206	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T15	3		T125	5		T176	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T54	11		T179	13		T242	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16013	1			T5	3		T24	2		T25	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T115	5		T201	1		T154	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T55	4		T206	11		T141	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T107	1		T228	2		T260	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T99	5		T118	6		T218	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T19	3		T61	8		T214	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T57	8		T98	4		T202	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T14	8		T60	8		T34	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T91	1		T118	9		T158	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T234	14		T169	9		T174	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T212	8		T96	10		T230	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T60	8		T57	13		T205	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T15	3		T101	8		T232	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T16	7		T123	13		T120	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	902	1			T20	30		T235	5		T236	26
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T14	10		T110	10		T118	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T15	2		T22	2		T203	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T94	2		T96	7		T223	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T109	8		T120	5		T276	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T206	15		T95	8		T205	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T15	10		T125	4		T328	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T256	14		T257	2		T329	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T124	3		T224	13		T223	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T115	7		T156	7		T259	15

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T15	3		T21	14		T130	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T206	19		T213	4		T200	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T245	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T115	5		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T55	15		T34	1		T206	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T107	5		T228	8		T219	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T16	1		T99	15		T209	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T19	5		T130	1		T112	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T57	7		T98	1		T218	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T14	9		T60	9		T61	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T13	2		T208	2		T184	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T103	10		T95	11		T97	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T91	3		T207	1		T212	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T60	6		T57	13		T205	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T21	1		T214	1		T96	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T59	9		T269	1		T113	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T15	6		T205	1		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T14	10		T16	1		T203	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T15	5		T22	8		T204	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T59	16		T94	8		T96	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1493	1			T11	1		T20	3		T23	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	438	1			T13	10		T91	1		T54	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15917	1			T5	3		T24	2		T25	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T15	10		T120	5		T125	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T206	15		T256	14		T329	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T115	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T55	4		T206	11		T141	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T107	1		T228	2		T260	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T99	5		T118	6		T218	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T19	3		T232	10		T163	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T57	8		T98	4		T218	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T14	8		T60	8		T61	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T118	9		T202	16		T158	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T95	12		T160	6		T120	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T91	1		T212	8		T163	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T60	8		T57	13		T205	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T96	10		T230	1		T232	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T234	7		T143	9		T216	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T15	3		T205	4		T141	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T14	10		T16	7		T110	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T15	2		T22	2		T204	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T94	2		T96	7		T223	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1020	1			T20	30		T109	8		T235	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T95	8		T205	9		T177	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20819

1

T5

3

T24

2

T25

1

auto[1]

auto[0]

3463

1

T14

18

T15

15

T16

7