Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24282

1

T5

3

T24

2

T25

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20962

1

T5

3

T24

2

T25

1

auto[ADC_CTRL_FILTER_COND_OUT]

3320

1

T13

12

T14

37

T15

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18914

1

T5

3

T24

2

T25

1

auto[1]

5368

1

T11

1

T15

9

T19

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20268

1

T11

1

T12

15

T13

2

auto[1]

4014

1

T5

3

T24

2

T25

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	173	1			T203	5		T111	10		T224	26
values[0]	57	1			T263	9		T266	7		T330	23
values[1]	674	1			T13	10		T94	11		T214	24
values[2]	625	1			T15	9		T34	1		T104	14
values[3]	610	1			T14	17		T15	13		T16	1
values[4]	561	1			T15	7		T22	10		T61	16
values[5]	2863	1			T11	1		T20	33		T21	14
values[6]	498	1			T13	2		T60	14		T103	10
values[7]	825	1			T14	20		T16	8		T91	4
values[8]	653	1			T60	17		T109	9		T57	15
values[9]	826	1			T19	8		T57	26		T115	12
minimum	15917	1			T5	3		T24	2		T25	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	669	1			T15	9		T94	11		T214	24
values[1]	601	1			T15	13		T34	1		T104	14
values[2]	613	1			T14	17		T16	1		T21	1
values[3]	2789	1			T11	1		T15	7		T20	33
values[4]	548	1			T13	2		T21	14		T34	33
values[5]	675	1			T60	14		T103	10		T59	9
values[6]	720	1			T14	20		T16	8		T60	17
values[7]	644	1			T109	9		T55	19		T57	15
values[8]	803	1			T19	8		T203	5		T115	12
values[9]	83	1			T57	26		T111	10		T247	1
minimum	16137	1			T5	3		T24	2		T25	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20819

1

T5

3

T24

2

T25

1

auto[1]

3463

1

T14

18

T15

15

T16

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T15	4		T94	1		T219	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T214	13		T205	3		T107	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T34	1		T141	9		T179	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T15	11		T104	1		T141	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T21	1		T34	1		T177	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T14	9		T16	1		T61	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1280	1			T11	1		T15	4		T20	33
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T22	8		T94	3		T95	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T21	1		T96	8		T97	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T13	1		T34	15		T203	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T103	1		T59	1		T95	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T60	9		T206	12		T106	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T91	3		T59	1		T214	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T14	11		T16	8		T60	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T109	9		T57	9		T99	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T55	5		T206	16		T205	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T19	4		T115	8		T204	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T203	2		T178	1		T110	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T111	1		T247	1		T331	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T57	14		T238	3		T146	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15842	1			T12	15		T14	209		T15	65
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T13	1		T100	1		T142	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T15	5		T94	10		T219	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T214	11		T205	12		T107	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T141	9		T179	3		T215	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T15	2		T104	13		T215	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T34	1		T218	14		T179	28
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T14	8		T61	7		T228	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1055	1			T15	3		T121	12		T140	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T22	2		T94	7		T95	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T21	13		T97	10		T260	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T13	1		T34	18		T203	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T103	9		T59	8		T95	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T60	5		T206	11		T106	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T91	1		T59	15		T97	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T14	9		T60	8		T272	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T57	6		T99	14		T209	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T55	14		T206	18		T205	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T19	4		T115	4		T204	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T203	3		T110	4		T224	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T111	9		T275	2		T310	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T57	12		T265	11		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T5	3		T24	2		T25	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T13	9		T284	16		T145	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T111	1		T224	14		T250	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T203	2		T146	1		T332	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T263	5		T266	7		T330	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T268	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T94	1		T118	10		T219	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T13	1		T214	13		T205	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T15	4		T34	1		T141	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T104	1		T130	1		T270	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T21	1		T34	1		T177	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T14	9		T15	11		T16	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T15	4		T91	1		T207	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T22	8		T61	9		T108	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1274	1			T11	1		T20	33		T21	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T34	15		T206	12		T94	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T103	1		T95	9		T211	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T13	1		T60	9		T106	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T91	3		T59	2		T214	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T14	11		T16	8		T55	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T109	9		T57	9		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T60	9		T206	16		T205	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T19	4		T115	8		T204	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T57	14		T178	1		T110	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15774	1			T12	15		T14	209		T15	65
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T111	9		T224	12		T250	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T203	3		T332	14		T333	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T263	4		T330	11		T334	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T268	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T94	10		T219	2		T223	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T13	9		T214	11		T205	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T15	5		T141	9		T179	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T104	13		T215	3		T174	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T34	1		T218	14		T179	28
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T14	8		T15	2		T228	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T15	3		T96	11		T218	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T22	2		T61	7		T111	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1052	1			T21	13		T121	12		T140	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T34	18		T206	11		T94	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T103	9		T95	11		T101	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T13	1		T60	5		T106	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T91	1		T59	23		T97	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T14	9		T55	14		T124	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T57	6		T223	4		T125	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T60	8		T206	18		T205	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T19	4		T115	4		T204	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T57	12		T110	4		T224	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	3		T24	2		T25	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T15	6		T94	11		T219	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T214	12		T205	13		T107	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T34	1		T141	10		T179	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T15	3		T104	14		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T21	1		T34	2		T177	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T14	9		T16	1		T61	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1402	1			T11	1		T15	5		T20	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T22	8		T94	8		T95	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T21	14		T96	1		T97	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T13	2		T34	19		T203	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T103	10		T59	9		T95	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T60	6		T206	12		T106	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T91	3		T59	16		T214	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T14	10		T16	1		T60	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T109	1		T57	7		T99	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T55	15		T206	19		T205	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	350	1			T19	5		T115	5		T204	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T203	5		T178	1		T110	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T111	10		T247	1		T331	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T57	13		T238	3		T146	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15982	1			T5	3		T24	2		T25	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T13	10		T100	1		T142	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T15	3		T223	11		T126	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T214	12		T205	2		T107	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T141	8		T273	15		T143	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T15	10		T141	7		T270	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T177	2		T118	6		T218	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T14	8		T61	8		T228	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	933	1			T15	2		T20	30		T235	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T22	2		T94	2		T95	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T96	7		T122	2		T260	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T34	14		T203	2		T101	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T95	8		T211	2		T130	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T60	8		T206	11		T106	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T91	1		T120	5		T223	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T14	10		T16	7		T60	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T109	8		T57	8		T99	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T55	4		T206	15		T205	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T19	3		T115	7		T204	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T110	10		T224	10		T169	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T275	4		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T57	13		T265	14		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T118	9		T271	1		T313	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T284	11		T145	12		T315	3

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T111	10		T224	13		T250	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T203	5		T146	1		T332	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T263	5		T266	1		T330	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T268	13		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T94	11		T118	1		T219	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T13	10		T214	12		T205	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T15	6		T34	1		T141	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T104	14		T130	1		T270	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T21	1		T34	2		T177	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T14	9		T15	3		T16	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T15	5		T91	1		T207	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T22	8		T61	8		T108	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1407	1			T11	1		T20	3		T21	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T34	19		T206	12		T94	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T103	10		T95	12		T211	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T13	2		T60	6		T106	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T91	3		T59	25		T214	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T14	10		T16	1		T55	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T109	1		T57	7		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T60	9		T206	19		T205	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	342	1			T19	5		T115	5		T204	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T57	13		T178	1		T110	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15917	1			T5	3		T24	2		T25	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T224	13		T250	13		T335	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T333	2		T262	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T263	4		T266	6		T330	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T118	9		T223	11		T126	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T214	12		T205	2		T107	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T15	3		T141	8		T273	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T270	6		T174	2		T271	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T177	2		T118	6		T218	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T14	8		T15	10		T141	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T15	2		T96	12		T218	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T22	2		T61	8		T276	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	919	1			T20	30		T235	5		T236	26
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T34	14		T206	11		T94	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T95	8		T211	2		T98	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T60	8		T106	1		T120	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T91	1		T130	11		T120	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T14	10		T16	7		T55	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T109	8		T57	8		T223	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T60	8		T206	15		T205	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T19	3		T115	7		T204	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T57	13		T110	10		T224	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20819

1

T5

3

T24

2

T25

1

auto[1]

auto[0]

3463

1

T14

18

T15

15

T16

7