Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24282

1

T5

3

T24

2

T25

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

18965

1

T5

3

T24

2

T25

1

auto[ADC_CTRL_FILTER_COND_OUT]

5317

1

T11

1

T13

2

T15

22

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18788

1

T5

3

T24

2

T25

1

auto[1]

5494

1

T11

1

T13

10

T14

37

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20268

1

T11

1

T12

15

T13

2

auto[1]

4014

1

T5

3

T24

2

T25

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	200	1			T19	8		T118	7		T111	14
values[0]	17	1			T203	6		T126	1		T290	1
values[1]	567	1			T14	17		T61	16		T206	34
values[2]	666	1			T91	1		T54	11		T59	16
values[3]	725	1			T13	10		T16	1		T21	14
values[4]	683	1			T203	5		T207	1		T177	3
values[5]	591	1			T14	20		T15	9		T109	9
values[6]	737	1			T15	13		T103	10		T205	15
values[7]	739	1			T21	1		T22	10		T60	31
values[8]	607	1			T13	2		T95	20		T106	6
values[9]	2833	1			T11	1		T15	7		T16	8
minimum	15917	1			T5	3		T24	2		T25	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	566	1			T61	16		T34	1		T107	6
values[1]	2706	1			T11	1		T20	33		T23	1
values[2]	664	1			T13	10		T16	1		T21	14
values[3]	700	1			T14	20		T109	9		T203	5
values[4]	597	1			T15	22		T57	15		T59	9
values[5]	774	1			T22	10		T103	10		T205	15
values[6]	681	1			T21	1		T60	31		T91	4
values[7]	599	1			T13	2		T95	20		T106	6
values[8]	785	1			T15	7		T16	8		T57	26
values[9]	109	1			T19	8		T55	19		T179	13
minimum	16101	1			T5	3		T24	2		T25	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20819

1

T5

3

T24

2

T25

1

auto[1]

3463

1

T14

18

T15

15

T16

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T107	3		T97	2		T108	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T61	9		T34	1		T211	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T91	1		T54	1		T34	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1270	1			T11	1		T20	33		T23	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T13	1		T104	1		T205	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T16	1		T21	1		T100	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T14	11		T109	9		T203	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T207	1		T177	3		T160	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T96	11		T247	1		T272	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T15	15		T57	9		T59	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T22	8		T205	3		T212	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T103	1		T184	1		T219	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T60	9		T214	13		T141	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T21	1		T60	9		T91	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T106	4		T214	1		T96	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T13	1		T95	9		T205	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T15	4		T208	1		T141	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T16	8		T57	14		T34	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T19	4		T151	13		T294	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T55	5		T179	1		T188	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15838	1			T12	15		T14	218		T15	65
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T203	4		T281	1		T200	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T107	3		T97	23		T99	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T61	7		T230	11		T286	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T54	10		T34	18		T110	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1045	1			T121	12		T140	12		T59	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T13	9		T104	13		T209	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T21	13		T124	3		T272	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T14	9		T203	3		T115	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T276	7		T230	1		T223	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T96	17		T272	14		T248	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T15	7		T57	6		T59	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T22	2		T205	12		T212	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T103	9		T184	14		T219	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T60	5		T214	11		T97	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T60	8		T91	1		T204	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T106	2		T96	11		T130	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T13	1		T95	11		T205	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T15	3		T141	9		T101	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T57	12		T34	1		T206	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T19	4		T336	6		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T55	14		T179	12		T275	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T5	3		T24	2		T25	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T203	2		T200	11		T174	15

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T19	4		T118	7		T311	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T111	1		T179	1		T143	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T290	1		T291	1		T264	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T203	4		T126	1		T296	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T14	9		T206	16		T95	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T61	9		T211	3		T230	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T91	1		T54	1		T107	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T59	1		T34	1		T94	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T13	1		T34	15		T104	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T16	1		T21	1		T100	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T203	2		T158	12		T112	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T207	1		T177	3		T160	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T14	11		T109	9		T115	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T15	4		T57	9		T59	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T205	3		T212	9		T208	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T15	11		T103	1		T178	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T22	8		T60	9		T141	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T21	1		T60	9		T91	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T106	4		T214	14		T96	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T13	1		T95	9		T205	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T15	4		T208	1		T141	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1326	1			T11	1		T16	8		T20	33
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15774	1			T12	15		T14	209		T15	65
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T19	4		T311	3		T225	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T111	13		T179	12		T337	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T291	3		T264	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T203	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T14	8		T206	18		T95	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T61	7		T230	11		T200	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T54	10		T107	3		T110	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T59	15		T94	10		T272	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T13	9		T34	18		T104	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T21	13		T280	14		T284	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T203	3		T280	9		T232	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T124	3		T276	7		T230	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T14	9		T115	4		T248	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T15	5		T57	6		T59	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T205	12		T212	8		T96	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T15	2		T103	9		T219	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T22	2		T60	5		T97	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T60	8		T91	1		T204	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T106	2		T214	11		T96	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T13	1		T95	11		T205	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T15	3		T141	9		T130	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1163	1			T121	12		T140	12		T55	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	3		T24	2		T25	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T107	5		T97	25		T108	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T61	8		T34	1		T211	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T91	1		T54	11		T34	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1372	1			T11	1		T20	3		T23	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T13	10		T104	14		T205	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T16	1		T21	14		T100	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T14	10		T109	1		T203	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T207	1		T177	1		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T96	18		T247	1		T272	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T15	9		T57	7		T59	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T22	8		T205	13		T212	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T103	10		T184	15		T219	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T60	6		T214	12		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T21	1		T60	9		T91	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T106	5		T214	1		T96	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T13	2		T95	12		T205	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T15	5		T208	1		T141	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T16	1		T57	13		T34	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T19	5		T151	1		T294	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T55	15		T179	13		T188	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15968	1			T5	3		T24	2		T25	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T203	4		T281	1		T200	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T107	1		T99	5		T338	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T61	8		T211	2		T230	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T34	14		T110	10		T202	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	943	1			T20	30		T235	5		T236	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T205	4		T123	13		T158	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T124	15		T232	2		T284	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T14	10		T109	8		T115	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T177	2		T160	6		T276	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T96	10		T248	16		T293	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T15	13		T57	8		T98	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T22	2		T205	2		T212	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T101	8		T224	13		T169	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T60	8		T214	12		T141	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T60	8		T91	1		T204	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T106	1		T96	12		T130	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T95	8		T205	9		T150	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T15	2		T141	8		T98	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T16	7		T57	13		T206	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T19	3		T151	12		T294	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T55	4		T295	6		T275	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T14	8		T206	15		T95	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T203	2		T174	3		T329	3

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T19	5		T118	1		T311	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T111	14		T179	13		T143	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T290	1		T291	4		T264	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T203	4		T126	1		T296	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T14	9		T206	19		T95	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T61	8		T211	1		T230	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T91	1		T54	11		T107	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T59	16		T34	1		T94	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T13	10		T34	19		T104	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T16	1		T21	14		T100	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T203	5		T158	1		T112	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T207	1		T177	1		T160	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T14	10		T109	1		T115	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T15	6		T57	7		T59	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T205	13		T212	9		T208	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T15	3		T103	10		T178	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T22	8		T60	6		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T21	1		T60	9		T91	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T106	5		T214	13		T96	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T13	2		T95	12		T205	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T15	5		T208	1		T141	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1515	1			T11	1		T16	1		T20	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15917	1			T5	3		T24	2		T25	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T19	3		T118	6		T151	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T143	12		T339	11		T340	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T203	2		T296	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T14	8		T206	15		T95	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T61	8		T211	2		T230	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T107	1		T110	10		T202	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T118	10		T286	14		T216	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T34	14		T205	4		T123	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T232	2		T284	11		T298	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T158	11		T120	5		T232	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T177	2		T160	6		T124	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T14	10		T109	8		T115	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T15	3		T57	8		T98	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T205	2		T212	8		T96	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T15	10		T101	8		T224	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T22	2		T60	8		T141	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T60	8		T91	1		T204	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T106	1		T214	12		T96	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T95	8		T205	9		T231	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T15	2		T141	8		T130	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	974	1			T16	7		T20	30		T55	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20819

1

T5

3

T24

2

T25

1

auto[1]

auto[0]

3463

1

T14

18

T15

15

T16

7