Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24282

1

T5

3

T24

2

T25

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21030

1

T5

3

T24

2

T25

1

auto[ADC_CTRL_FILTER_COND_OUT]

3252

1

T13

2

T14

20

T16

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18957

1

T5

3

T24

2

T25

1

auto[1]

5325

1

T11

1

T13

12

T19

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20268

1

T11

1

T12

15

T13

2

auto[1]

4014

1

T5

3

T24

2

T25

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	302	1			T13	2		T57	15		T203	6
values[0]	21	1			T308	6		T309	4		T244	11
values[1]	639	1			T14	37		T21	1		T60	14
values[2]	790	1			T91	4		T109	9		T55	19
values[3]	663	1			T91	1		T34	33		T95	20
values[4]	710	1			T13	10		T15	9		T22	10
values[5]	507	1			T206	23		T204	3		T211	3
values[6]	627	1			T15	7		T16	9		T104	14
values[7]	611	1			T61	16		T97	11		T130	1
values[8]	2645	1			T11	1		T19	8		T20	33
values[9]	850	1			T15	13		T59	16		T206	34
minimum	15917	1			T5	3		T24	2		T25	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	651	1			T14	37		T21	1		T60	14
values[1]	797	1			T109	9		T55	19		T34	35
values[2]	657	1			T91	1		T95	20		T98	5
values[3]	542	1			T13	10		T15	9		T22	10
values[4]	633	1			T15	7		T206	23		T204	3
values[5]	605	1			T16	9		T104	14		T111	14
values[6]	2576	1			T11	1		T20	33		T23	1
values[7]	649	1			T19	8		T21	14		T59	16
values[8]	826	1			T15	13		T203	5		T205	19
values[9]	209	1			T13	2		T57	15		T206	34
minimum	16137	1			T5	3		T24	2		T25	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20819

1

T5

3

T24

2

T25

1

auto[1]

3463

1

T14

18

T15

15

T16

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T14	9		T21	1		T60	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T14	11		T94	1		T208	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T120	11		T270	7		T232	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T109	9		T55	5		T34	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T91	1		T95	9		T98	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T218	3		T112	1		T230	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T13	1		T15	4		T115	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T22	8		T60	9		T57	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T15	4		T112	1		T272	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T206	12		T204	2		T211	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T16	1		T111	1		T218	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T16	8		T104	1		T247	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1236	1			T11	1		T20	33		T23	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T61	9		T34	1		T207	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T19	4		T21	1		T59	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T95	13		T212	9		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T15	11		T203	2		T205	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T208	1		T108	1		T118	21
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T57	9		T206	16		T205	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T13	1		T203	4		T122	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15830	1			T12	15		T14	209		T15	65
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T103	1		T54	1		T214	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T14	8		T60	5		T91	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T14	9		T94	10		T184	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T284	16		T152	14		T192	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T55	14		T34	19		T214	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T95	11		T179	28		T250	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T218	7		T230	1		T280	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T13	9		T15	5		T115	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T22	2		T60	8		T57	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T15	3		T272	14		T280	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T206	11		T204	1		T141	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T111	13		T218	14		T101	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T104	13		T280	9		T200	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1022	1			T121	12		T140	12		T221	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T61	7		T97	10		T272	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T19	4		T21	13		T59	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T95	10		T212	8		T111	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T15	2		T203	3		T205	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T219	2		T301	11		T174	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T57	6		T206	18		T205	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T13	1		T203	2		T176	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T5	3		T24	2		T25	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T103	9		T54	10		T308	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T57	9		T205	3		T160	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T13	1		T203	4		T122	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T309	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T308	1		T244	6		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T14	9		T21	1		T60	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T14	11		T103	1		T54	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T91	3		T120	11		T270	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T109	9		T55	5		T34	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T91	1		T95	9		T98	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T34	15		T178	1		T112	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T13	1		T15	4		T115	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T22	8		T60	9		T57	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T112	1		T272	1		T176	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T206	12		T204	2		T211	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T15	4		T16	1		T111	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T16	8		T104	1		T247	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T130	1		T100	1		T113	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T61	9		T97	1		T100	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1230	1			T11	1		T19	4		T20	33
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T34	1		T95	13		T207	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T15	11		T59	1		T206	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T208	1		T108	1		T118	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15774	1			T12	15		T14	209		T15	65
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T57	6		T205	12		T251	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T13	1		T203	2		T174	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T309	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T308	5		T244	5		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T14	8		T60	5		T59	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T14	9		T103	9		T54	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T91	1		T276	7		T125	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T55	14		T34	1		T214	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T95	11		T179	28		T250	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T34	18		T230	1		T210	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T13	9		T15	5		T115	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T22	2		T60	8		T57	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T272	14		T176	11		T311	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T206	11		T204	1		T141	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T15	3		T111	13		T218	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T104	13		T280	9		T210	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T169	17		T150	15		T242	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T61	7		T97	10		T272	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1022	1			T19	4		T21	13		T121	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T95	10		T212	8		T111	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T15	2		T59	15		T206	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T219	2		T301	11		T174	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	3		T24	2		T25	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T14	9		T21	1		T60	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T14	10		T94	11		T208	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T120	1		T270	1		T232	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T109	1		T55	15		T34	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T91	1		T95	12		T98	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T218	8		T112	1		T230	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T13	10		T15	6		T115	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T22	8		T60	9		T57	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T15	5		T112	1		T272	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T206	12		T204	2		T211	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T16	1		T111	14		T218	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T16	1		T104	14		T247	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1357	1			T11	1		T20	3		T23	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T61	8		T34	1		T207	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T19	5		T21	14		T59	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T95	11		T212	9		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T15	3		T203	5		T205	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T208	1		T108	1		T118	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T57	7		T206	19		T205	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T13	2		T203	4		T122	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15957	1			T5	3		T24	2		T25	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T103	10		T54	11		T214	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T14	8		T60	8		T91	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T14	10		T96	12		T118	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T120	10		T270	6		T232	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T109	8		T55	4		T34	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T95	8		T98	4		T250	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T218	2		T230	1		T143	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T15	3		T115	7		T96	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T22	2		T60	8		T57	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T15	2		T261	2		T313	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T206	11		T204	1		T211	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T218	11		T101	5		T220	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T16	7		T169	7		T143	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	901	1			T20	30		T235	5		T236	26
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T61	8		T222	7		T312	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T19	3		T101	8		T260	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T95	12		T212	8		T98	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T15	10		T205	9		T107	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T118	19		T174	3		T220	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T57	8		T206	15		T205	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T203	2		T122	2		T151	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T123	13		T223	4		T242	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T177	2		T150	10		T244	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T57	7		T205	13		T160	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T13	2		T203	4		T122	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T309	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T308	6		T244	6		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T14	9		T21	1		T60	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T14	10		T103	10		T54	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T91	3		T120	1		T270	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T109	1		T55	15		T34	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T91	1		T95	12		T98	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T34	19		T178	1		T112	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T13	10		T15	6		T115	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T22	8		T60	9		T57	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T112	1		T272	15		T176	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T206	12		T204	2		T211	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T15	5		T16	1		T111	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T16	1		T104	14		T247	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T130	1		T100	1		T113	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T61	8		T97	11		T100	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1363	1			T11	1		T19	5		T20	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T34	1		T95	11		T207	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T15	3		T59	16		T206	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T208	1		T108	1		T118	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15917	1			T5	3		T24	2		T25	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T57	8		T205	2		T160	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T203	2		T122	2		T118	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T309	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T244	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T14	8		T60	8		T94	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T14	10		T177	2		T118	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T91	1		T120	10		T270	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T109	8		T55	4		T214	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T95	8		T98	4		T250	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T34	14		T230	1		T143	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T15	3		T115	7		T96	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T22	2		T60	8		T57	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T261	2		T313	12		T341	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T206	11		T204	1		T211	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T15	2		T218	11		T101	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T16	7		T169	7		T143	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T169	15		T261	11		T150	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T61	8		T222	7		T312	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	889	1			T19	3		T20	30		T235	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T95	12		T212	8		T98	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T15	10		T206	15		T205	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T118	9		T174	2		T220	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20819

1

T5

3

T24

2

T25

1

auto[1]

auto[0]

3463

1

T14

18

T15

15

T16

7