Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T16	1		T55	15		T34	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T115	5		T107	5		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T57	7		T108	1		T99	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T19	5		T61	8		T214	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T184	15		T98	1		T122	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T14	9		T60	9		T103	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T13	2		T91	3		T208	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T149	1		T179	4		T247	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T207	1		T212	9		T96	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T60	6		T57	13		T205	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T15	6		T21	1		T214	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T16	1		T123	1		T120	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1383	1			T11	1		T20	3		T23	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T14	10		T59	9		T203	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T15	5		T22	8		T94	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T91	1		T59	16		T94	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T21	14		T109	1		T34	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T13	10		T206	19		T95	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T15	3		T125	5		T248	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T54	11		T246	1		T179	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15918	1			T5	3		T24	2		T25	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T55	4		T206	11		T141	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T115	7		T107	1		T228	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T57	8		T99	5		T118	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T19	3		T61	8		T214	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T98	4		T122	2		T202	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T14	8		T60	8		T34	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T91	1		T118	9		T250	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T234	14		T169	9		T174	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T212	8		T96	10		T230	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T60	8		T57	13		T205	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T15	3		T101	8		T232	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T16	7		T123	13		T120	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	921	1			T20	30		T235	5		T236	26
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T14	10		T110	10		T118	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T15	2		T22	2		T211	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T94	2		T96	7		T224	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T109	8		T203	2		T204	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T206	15		T95	8		T205	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T15	10		T125	4		T248	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T256	14		T257	2		T258	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T143	12		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T244	16		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T111	14		T252	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T115	5		T245	1		T156	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T55	15		T34	1		T206	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T107	5		T228	8		T219	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T16	1		T99	15		T209	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T34	19		T130	1		T112	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T57	7		T98	1		T108	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T14	9		T19	5		T60	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T13	2		T208	1		T184	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T103	10		T95	11		T97	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T91	3		T207	1		T212	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T60	6		T57	13		T205	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T214	1		T96	18		T101	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T59	9		T113	1		T247	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T15	6		T21	1		T205	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T14	10		T16	1		T203	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T15	5		T22	8		T203	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T59	16		T94	8		T96	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1581	1			T11	1		T15	3		T20	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	498	1			T13	10		T91	1		T54	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15917	1			T5	3		T24	2		T25	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T244	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T252	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T115	7		T156	7		T259	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T55	4		T206	11		T141	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T107	1		T228	2		T260	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T99	5		T118	6		T218	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T34	14		T232	10		T231	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T57	8		T98	4		T122	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T14	8		T19	3		T60	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T118	9		T202	16		T158	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T95	12		T160	6		T234	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T91	1		T212	8		T163	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T60	8		T57	13		T205	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T96	10		T101	8		T230	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T234	7		T216	8		T151	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T15	3		T205	4		T141	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T14	10		T16	7		T110	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T15	2		T22	2		T203	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T94	2		T96	7		T261	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1058	1			T15	10		T20	30		T109	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T206	15		T95	8		T205	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20819

1

T5

3

T24

2

T25

1

auto[1]

auto[0]

3463

1

T14

18

T15

15

T16

7