Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24282

1

T5

3

T24

2

T25

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21129

1

T5

3

T24

2

T25

1

auto[ADC_CTRL_FILTER_COND_OUT]

3153

1

T13

12

T14

37

T15

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18298

1

T5

3

T24

2

T25

1

auto[1]

5984

1

T11

1

T13

10

T14

26

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20268

1

T11

1

T12

15

T13

2

auto[1]

4014

1

T5

3

T24

2

T25

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	377	1			T14	9		T22	3		T37	4
values[0]	54	1			T13	2		T143	10		T298	9
values[1]	675	1			T14	20		T15	9		T57	26
values[2]	2734	1			T11	1		T14	17		T16	8
values[3]	678	1			T13	10		T16	1		T21	14
values[4]	661	1			T15	7		T206	34		T203	6
values[5]	675	1			T55	19		T59	16		T205	5
values[6]	597	1			T19	8		T115	12		T107	6
values[7]	647	1			T15	13		T57	15		T95	20
values[8]	638	1			T109	9		T206	23		T94	11
values[9]	992	1			T21	1		T22	10		T60	14
minimum	15554	1			T5	3		T24	2		T25	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	898	1			T13	2		T14	37		T15	9
values[1]	2683	1			T11	1		T16	1		T20	33
values[2]	871	1			T13	10		T15	7		T21	14
values[3]	512	1			T59	16		T211	3		T212	17
values[4]	744	1			T55	19		T115	12		T205	5
values[5]	540	1			T15	13		T19	8		T95	20
values[6]	662	1			T109	9		T57	15		T204	3
values[7]	549	1			T206	23		T94	11		T96	24
values[8]	782	1			T21	1		T22	10		T61	16
values[9]	97	1			T60	14		T91	1		T203	5
minimum	15944	1			T5	3		T24	2		T25	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20819

1

T5

3

T24

2

T25

1

auto[1]

3463

1

T14

18

T15

15

T16

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T15	4		T57	14		T59	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T13	1		T14	20		T16	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1244	1			T11	1		T20	33		T23	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T16	1		T34	15		T208	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T15	4		T21	1		T60	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T13	1		T91	3		T106	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T108	1		T113	1		T215	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T59	1		T211	3		T212	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T55	5		T115	8		T96	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T205	5		T123	14		T113	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T19	4		T95	9		T98	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T15	11		T107	3		T202	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T57	9		T96	11		T99	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T109	9		T204	2		T208	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T98	10		T177	3		T228	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T206	12		T94	1		T96	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T21	1		T22	8		T61	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T54	1		T34	1		T214	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T97	1		-	-		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T60	9		T91	1		T203	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15777	1			T12	15		T14	209		T15	65
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T261	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T15	5		T57	12		T59	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T13	1		T14	17		T124	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1041	1			T121	12		T140	12		T221	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T34	18		T101	11		T210	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T15	3		T21	13		T60	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T13	9		T91	1		T106	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T215	7		T176	12		T220	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T59	15		T212	8		T111	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T55	14		T115	4		T101	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T280	14		T125	1		T232	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T19	4		T95	11		T110	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T15	2		T107	3		T101	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T57	6		T96	17		T99	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T204	1		T184	14		T218	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T228	7		T218	7		T272	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T206	11		T94	10		T96	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T22	2		T61	7		T104	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T54	10		T34	1		T209	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T97	10		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T60	5		T203	3		T172	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T5	3		T24	2		T25	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	364	1			T14	9		T22	3		T37	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T143	10		T298	3		T299	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T13	1		T289	3		T300	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T15	4		T57	14		T59	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T14	11		T208	2		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1198	1			T11	1		T20	33		T23	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T14	9		T16	8		T34	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T21	1		T60	9		T214	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T13	1		T16	1		T91	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T15	4		T206	16		T203	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T212	9		T100	1		T111	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T55	5		T113	1		T223	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T59	1		T205	5		T211	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T19	4		T115	8		T96	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T107	3		T202	17		T101	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T57	9		T95	9		T96	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T15	11		T204	2		T208	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T177	3		T118	7		T228	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T109	9		T206	12		T94	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T21	1		T22	8		T61	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T60	9		T91	1		T54	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15411	1			T12	15		T14	200		T15	65
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T104	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T298	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T13	1		T253	14		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T15	5		T57	12		T59	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T14	9		T124	9		T169	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1040	1			T103	9		T121	12		T140	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T14	8		T34	18		T130	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T21	13		T60	8		T214	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T13	9		T91	1		T106	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T15	3		T206	18		T203	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T212	8		T111	9		T276	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T55	14		T223	11		T251	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T59	15		T280	14		T125	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T19	4		T115	4		T110	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T107	3		T101	13		T301	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T57	6		T95	11		T96	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T15	2		T204	1		T184	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T228	7		T219	2		T272	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T206	11		T94	10		T96	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T22	2		T61	7		T97	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T60	5		T54	10		T34	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	3		T24	2		T25	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T15	6		T57	13		T59	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T13	2		T14	19		T16	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1369	1			T11	1		T20	3		T23	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T16	1		T34	19		T208	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T15	5		T21	14		T60	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T13	10		T91	3		T106	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T108	1		T113	1		T215	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T59	16		T211	1		T212	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T55	15		T115	5		T96	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T205	1		T123	1		T113	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T19	5		T95	12		T98	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T15	3		T107	5		T202	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T57	7		T96	18		T99	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T109	1		T204	2		T208	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T98	1		T177	1		T228	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T206	12		T94	11		T96	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T21	1		T22	8		T61	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T54	11		T34	2		T214	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T97	11		-	-		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T60	6		T91	1		T203	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15930	1			T5	3		T24	2		T25	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T261	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T15	3		T57	13		T95	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T14	18		T16	7		T124	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	916	1			T20	30		T235	5		T236	26
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T34	14		T101	5		T120	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T15	2		T60	8		T206	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T91	1		T106	1		T130	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T220	14		T263	4		T302	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T211	2		T212	8		T160	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T55	4		T115	7		T96	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T205	4		T123	13		T232	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T19	3		T95	8		T98	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T15	10		T107	1		T202	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T57	8		T96	10		T99	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T109	8		T204	1		T141	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T98	9		T177	2		T228	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T206	11		T96	12		T98	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T22	2		T61	8		T120	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T260	1		T270	6		T124	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T60	8		T163	11		T241	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T205	2		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T261	11		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	377	1			T14	9		T22	3		T37	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T143	1		T298	7		T299	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T13	2		T289	1		T300	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T15	6		T57	13		T59	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T14	10		T208	2		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1363	1			T11	1		T20	3		T23	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T14	9		T16	1		T34	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T21	14		T60	9		T214	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T13	10		T16	1		T91	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T15	5		T206	19		T203	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T212	9		T100	1		T111	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T55	15		T113	1		T223	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T59	16		T205	1		T211	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T19	5		T115	5		T96	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T107	5		T202	1		T101	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T57	7		T95	12		T96	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T15	3		T204	2		T208	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T177	1		T118	1		T228	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T109	1		T206	12		T94	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T21	1		T22	8		T61	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	343	1			T60	6		T91	1		T54	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15554	1			T5	3		T24	2		T25	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T143	9		T298	2		T299	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T289	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T15	3		T57	13		T205	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T14	10		T124	3		T169	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	875	1			T20	30		T235	5		T236	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T14	8		T16	7		T34	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T60	8		T214	12		T205	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T91	1		T106	1		T216	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T15	2		T206	15		T203	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T212	8		T123	13		T160	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T55	4		T223	11		T169	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T205	4		T211	2		T232	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T19	3		T115	7		T96	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T107	1		T202	16		T101	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T57	8		T95	8		T96	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T15	10		T204	1		T118	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T177	2		T118	6		T228	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T109	8		T206	11		T141	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T22	2		T61	8		T98	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T60	8		T98	4		T260	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20819

1

T5

3

T24

2

T25

1

auto[1]

auto[0]

3463

1

T14

18

T15

15

T16

7