Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24282

1

T5

3

T24

2

T25

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21145

1

T5

3

T24

2

T25

1

auto[ADC_CTRL_FILTER_COND_OUT]

3137

1

T13

12

T14

37

T16

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18240

1

T5

3

T24

2

T25

1

auto[1]

6042

1

T11

1

T13

10

T14

26

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20268

1

T11

1

T12

15

T13

2

auto[1]

4014

1

T5

3

T24

2

T25

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	558	1			T14	9		T21	1		T22	3
values[0]	38	1			T261	12		T143	10		T289	3
values[1]	672	1			T13	2		T14	20		T15	9
values[2]	2777	1			T11	1		T14	17		T16	8
values[3]	665	1			T13	10		T16	1		T21	14
values[4]	606	1			T15	7		T206	34		T203	6
values[5]	753	1			T55	19		T59	16		T205	5
values[6]	568	1			T19	8		T115	12		T107	6
values[7]	664	1			T15	13		T57	15		T95	20
values[8]	602	1			T109	9		T206	23		T94	11
values[9]	825	1			T22	10		T61	16		T91	1
minimum	15554	1			T5	3		T24	2		T25	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	717	1			T14	20		T15	9		T16	8
values[1]	2657	1			T11	1		T14	17		T16	1
values[2]	815	1			T13	10		T15	7		T21	14
values[3]	540	1			T59	16		T211	3		T212	17
values[4]	726	1			T55	19		T205	5		T96	8
values[5]	584	1			T15	13		T19	8		T95	20
values[6]	600	1			T109	9		T57	15		T204	3
values[7]	605	1			T206	23		T94	11		T96	24
values[8]	793	1			T21	1		T22	10		T61	16
values[9]	91	1			T60	14		T203	5		T207	1
minimum	16154	1			T5	3		T24	2		T25	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20819

1

T5

3

T24

2

T25

1

auto[1]

3463

1

T14

18

T15

15

T16

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T15	4		T205	3		T208	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T14	11		T16	8		T57	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1218	1			T11	1		T16	1		T20	33
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T14	9		T34	15		T94	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T15	4		T21	1		T60	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T13	1		T103	1		T203	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T108	1		T111	1		T160	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T59	1		T211	3		T212	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T55	5		T96	8		T112	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T205	5		T123	14		T280	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T15	11		T19	4		T95	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T107	3		T202	17		T101	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T57	9		T184	1		T96	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T109	9		T204	2		T208	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T206	12		T94	1		T228	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T96	13		T98	5		T177	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T22	8		T61	9		T91	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T21	1		T54	1		T34	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T203	2		T207	1		T97	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T60	9		T163	12		T238	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15865	1			T12	15		T14	209		T15	65
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T13	1		T169	16		T192	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T15	5		T205	12		T213	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T14	9		T57	12		T95	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1017	1			T121	12		T140	12		T221	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T14	8		T34	18		T94	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T15	3		T21	13		T60	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T13	9		T103	9		T203	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T111	9		T263	4		T256	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T59	15		T212	8		T101	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T55	14		T223	11		T125	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T280	14		T251	1		T232	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T15	2		T19	4		T95	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T107	3		T101	13		T301	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T57	6		T184	14		T96	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T204	1		T219	12		T215	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T206	11		T94	10		T228	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T96	11		T223	4		T220	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T22	2		T61	7		T104	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T54	10		T34	1		T209	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T203	3		T97	10		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T60	5		T302	12		T303	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T5	3		T24	2		T25	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T13	1		T169	17		T192	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	398	1			T14	9		T22	3		T37	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T21	1		T60	9		T238	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T261	12		T143	10		T289	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T15	4		T59	1		T205	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T13	1		T14	11		T57	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1215	1			T11	1		T20	33		T23	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T14	9		T16	8		T103	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T16	1		T21	1		T60	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T13	1		T106	4		T214	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T15	4		T206	16		T108	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T203	4		T212	9		T100	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T55	5		T96	8		T160	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T59	1		T205	5		T211	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T19	4		T115	8		T98	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T107	3		T202	17		T101	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T15	11		T57	9		T95	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T204	2		T208	1		T122	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T206	12		T94	1		T118	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T109	9		T141	8		T96	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T22	8		T61	9		T91	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T54	1		T34	2		T214	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15411	1			T12	15		T14	200		T15	65
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T104	13		T230	1		T174	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T60	5		T304	15		T302	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T15	5		T59	8		T205	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T13	1		T14	9		T57	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1034	1			T121	12		T140	12		T221	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T14	8		T103	9		T34	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T21	13		T60	8		T91	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T13	9		T106	2		T214	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T15	3		T206	18		T111	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T203	2		T212	8		T101	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T55	14		T223	11		T125	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T59	15		T280	14		T251	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T19	4		T115	4		T110	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T107	3		T101	13		T301	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T15	2		T57	6		T95	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T204	1		T219	12		T250	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T206	11		T94	10		T218	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T96	11		T215	3		T153	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T22	2		T61	7		T203	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T54	10		T34	1		T209	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	3		T24	2		T25	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T15	6		T205	13		T208	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T14	10		T16	1		T57	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1346	1			T11	1		T16	1		T20	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T14	9		T34	19		T94	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T15	5		T21	14		T60	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T13	10		T103	10		T203	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T108	1		T111	10		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T59	16		T211	1		T212	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T55	15		T96	1		T112	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T205	1		T123	1		T280	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T15	3		T19	5		T95	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T107	5		T202	1		T101	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T57	7		T184	15		T96	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T109	1		T204	2		T208	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T206	12		T94	11		T228	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T96	12		T98	1		T177	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T22	8		T61	8		T91	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T21	1		T54	11		T34	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T203	5		T207	1		T97	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T60	6		T163	1		T238	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15983	1			T5	3		T24	2		T25	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T13	2		T169	18		T192	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T15	3		T205	2		T242	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T14	10		T16	7		T57	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	889	1			T20	30		T235	5		T236	26
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T14	8		T34	14		T94	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T15	2		T60	8		T91	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T203	2		T106	1		T150	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T160	6		T263	4		T256	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T211	2		T212	8		T276	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T55	4		T96	7		T223	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T205	4		T123	13		T232	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T15	10		T19	3		T95	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T107	1		T202	16		T101	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T57	8		T96	10		T99	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T109	8		T204	1		T141	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T206	11		T228	2		T218	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T96	12		T98	4		T177	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T22	2		T61	8		T98	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T260	1		T270	6		T124	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T60	8		T163	11		T241	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T174	1		T261	11		T143	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T169	15		T192	10		T305	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	420	1			T14	9		T22	3		T37	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T21	1		T60	6		T238	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T261	1		T143	1		T289	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T15	6		T59	9		T205	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T13	2		T14	10		T57	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1361	1			T11	1		T20	3		T23	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T14	9		T16	1		T103	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T16	1		T21	14		T60	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T13	10		T106	5		T214	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T15	5		T206	19		T108	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T203	4		T212	9		T100	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T55	15		T96	1		T160	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T59	16		T205	1		T211	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T19	5		T115	5		T98	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T107	5		T202	1		T101	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T15	3		T57	7		T95	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T204	2		T208	1		T122	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T206	12		T94	11		T118	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T109	1		T141	1		T96	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T22	8		T61	8		T91	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T54	11		T34	3		T214	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15554	1			T5	3		T24	2		T25	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T120	5		T230	1		T174	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T60	8		T304	7		T241	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T261	11		T143	9		T289	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T15	3		T205	2		T174	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T14	10		T57	13		T124	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	888	1			T20	30		T235	5		T236	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T14	8		T16	7		T34	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T60	8		T91	1		T205	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T106	1		T214	12		T150	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T15	2		T206	15		T169	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T203	2		T212	8		T276	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T55	4		T96	7		T160	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T205	4		T211	2		T123	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T19	3		T115	7		T98	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T107	1		T202	16		T101	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T15	10		T57	8		T95	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T204	1		T122	2		T118	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T206	11		T118	6		T218	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T109	8		T141	7		T96	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T22	2		T61	8		T98	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T98	4		T260	1		T270	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20819

1

T5

3

T24

2

T25

1

auto[1]

auto[0]

3463

1

T14

18

T15

15

T16

7