Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24282

1

T5

3

T24

2

T25

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20985

1

T5

3

T24

2

T25

1

auto[ADC_CTRL_FILTER_COND_OUT]

3297

1

T13

2

T14

20

T16

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18815

1

T5

3

T24

2

T25

1

auto[1]

5467

1

T11

1

T13

12

T19

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20268

1

T11

1

T12

15

T13

2

auto[1]

4014

1

T5

3

T24

2

T25

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	8	1			T306	1		T274	6		T307	1
values[0]	32	1			T21	1		T308	6		T309	4
values[1]	546	1			T14	20		T103	10		T54	11
values[2]	912	1			T14	17		T60	14		T91	4
values[3]	633	1			T91	1		T34	33		T95	20
values[4]	672	1			T13	10		T15	9		T60	17
values[5]	494	1			T22	10		T206	23		T204	3
values[6]	652	1			T15	7		T16	9		T104	14
values[7]	590	1			T61	16		T97	11		T100	1
values[8]	2642	1			T11	1		T19	8		T20	33
values[9]	1184	1			T13	2		T15	13		T57	15
minimum	15917	1			T5	3		T24	2		T25	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	908	1			T14	37		T21	1		T60	14
values[1]	718	1			T109	9		T55	19		T34	35
values[2]	675	1			T91	1		T95	20		T98	5
values[3]	603	1			T13	10		T15	9		T22	10
values[4]	609	1			T15	7		T206	23		T204	3
values[5]	585	1			T16	9		T111	14		T101	17
values[6]	2564	1			T11	1		T20	33		T23	1
values[7]	635	1			T19	8		T21	14		T59	16
values[8]	804	1			T15	13		T203	5		T205	19
values[9]	251	1			T13	2		T57	15		T206	34
minimum	15930	1			T5	3		T24	2		T25	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20819

1

T5

3

T24

2

T25

1

auto[1]

3463

1

T14

18

T15

15

T16

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T14	9		T21	1		T60	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T14	11		T103	1		T54	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T270	7		T232	3		T200	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T109	9		T55	5		T34	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T91	1		T95	9		T98	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T218	3		T112	1		T230	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T13	1		T15	4		T115	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T22	8		T60	9		T57	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T15	4		T218	12		T112	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T206	12		T204	2		T211	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T16	1		T111	1		T101	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T16	8		T247	1		T280	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1227	1			T11	1		T20	33		T23	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T61	9		T34	1		T104	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T19	4		T21	1		T59	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T95	13		T207	1		T212	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T15	11		T203	2		T107	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T205	10		T208	1		T130	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T57	9		T206	16		T205	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T13	1		T203	4		T122	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15774	1			T12	15		T14	209		T15	65
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T215	1		T310	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T14	8		T60	5		T91	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T14	9		T103	9		T54	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T200	11		T284	16		T152	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T55	14		T34	19		T214	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T95	11		T179	28		T250	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T218	7		T230	1		T280	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T13	9		T15	5		T115	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T22	2		T60	8		T57	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T15	3		T218	14		T280	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T206	11		T204	1		T141	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T111	13		T101	11		T272	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T280	9		T200	8		T169	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1041	1			T121	12		T140	12		T221	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T61	7		T104	13		T97	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T19	4		T21	13		T59	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T95	10		T212	8		T124	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T15	2		T203	3		T107	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T205	9		T130	11		T219	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T57	6		T206	18		T205	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T13	1		T203	2		T176	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	3		T24	2		T25	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T215	7		T310	4		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T306	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T274	3		T307	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T21	1		T296	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T308	1		T309	3		T244	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T59	1		T94	3		T123	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T14	11		T103	1		T54	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T14	9		T60	9		T91	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T109	9		T55	5		T34	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T91	1		T95	9		T98	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T34	15		T178	1		T112	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T13	1		T15	4		T115	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T60	9		T57	14		T106	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T112	1		T120	8		T272	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T22	8		T206	12		T204	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T15	4		T16	1		T111	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T16	8		T104	1		T141	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T100	1		T113	1		T190	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T61	9		T97	1		T272	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1242	1			T11	1		T19	4		T20	33
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T34	1		T95	13		T207	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	346	1			T15	11		T57	9		T59	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T13	1		T203	4		T205	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15774	1			T12	15		T14	209		T15	65
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T274	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T308	5		T309	1		T244	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T59	8		T94	7		T223	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T14	9		T103	9		T54	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T14	8		T60	5		T91	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T55	14		T34	1		T214	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T95	11		T179	16		T250	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T34	18		T230	1		T210	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T13	9		T15	5		T115	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T60	8		T57	12		T106	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T272	14		T176	11		T311	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T22	2		T206	11		T204	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T15	3		T111	13		T218	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T104	13		T141	9		T97	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T150	15		T242	1		T293	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T61	7		T97	10		T272	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1028	1			T19	4		T21	13		T121	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T95	10		T212	8		T111	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T15	2		T57	6		T59	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T13	1		T203	2		T205	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	3		T24	2		T25	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T14	9		T21	1		T60	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T14	10		T103	10		T54	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T270	1		T232	1		T200	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T109	1		T55	15		T34	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T91	1		T95	12		T98	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T218	8		T112	1		T230	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T13	10		T15	6		T115	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T22	8		T60	9		T57	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T15	5		T218	15		T112	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T206	12		T204	2		T211	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T16	1		T111	14		T101	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T16	1		T247	1		T280	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1380	1			T11	1		T20	3		T23	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T61	8		T34	1		T104	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T19	5		T21	14		T59	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T95	11		T207	1		T212	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T15	3		T203	5		T107	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T205	10		T208	1		T130	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T57	7		T206	19		T205	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T13	2		T203	4		T122	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15917	1			T5	3		T24	2		T25	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T215	8		T310	5		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T14	8		T60	8		T91	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T14	10		T96	12		T177	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T270	6		T232	2		T284	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T109	8		T55	4		T34	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T95	8		T98	4		T250	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T218	2		T230	1		T143	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T15	3		T115	7		T96	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T22	2		T60	8		T57	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T15	2		T218	11		T261	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T206	11		T204	1		T211	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T101	5		T220	2		T150	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T16	7		T169	7		T143	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	888	1			T20	30		T235	5		T236	26
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T61	8		T222	7		T312	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T19	3		T141	7		T101	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T95	12		T212	8		T98	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T15	10		T107	1		T98	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T205	9		T130	11		T118	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T57	8		T206	15		T205	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T203	2		T122	2		T151	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T306	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T274	5		T307	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T21	1		T296	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T308	6		T309	2		T244	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T59	9		T94	8		T123	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T14	10		T103	10		T54	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T14	9		T60	6		T91	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T109	1		T55	15		T34	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T91	1		T95	12		T98	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T34	19		T178	1		T112	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T13	10		T15	6		T115	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T60	9		T57	13		T106	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T112	1		T120	1		T272	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T22	8		T206	12		T204	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T15	5		T16	1		T111	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T16	1		T104	14		T141	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T100	1		T113	1		T190	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T61	8		T97	11		T272	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1368	1			T11	1		T19	5		T20	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T34	1		T95	11		T207	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	338	1			T15	3		T57	7		T59	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T13	2		T203	4		T205	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15917	1			T5	3		T24	2		T25	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T274	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T309	2		T244	5		T262	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T94	2		T123	13		T223	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T14	10		T177	2		T118	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T14	8		T60	8		T91	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T109	8		T55	4		T214	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T95	8		T98	4		T250	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T34	14		T230	1		T143	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T15	3		T115	7		T96	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T60	8		T57	13		T106	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T120	7		T261	2		T313	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T22	2		T206	11		T204	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T15	2		T218	11		T101	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T16	7		T141	8		T169	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T261	11		T150	15		T293	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T61	8		T222	7		T312	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	902	1			T19	3		T20	30		T235	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T95	12		T212	8		T124	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T15	10		T57	8		T206	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T203	2		T205	9		T130	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20819

1

T5

3

T24

2

T25

1

auto[1]

auto[0]

3463

1

T14

18

T15

15

T16

7