Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24282

1

T5

3

T24

2

T25

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21113

1

T5

3

T24

2

T25

1

auto[ADC_CTRL_FILTER_COND_OUT]

3169

1

T13

12

T14

37

T15

22

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18753

1

T5

3

T24

2

T25

1

auto[1]

5529

1

T11

1

T13

12

T14

20

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20268

1

T11

1

T12

15

T13

2

auto[1]

4014

1

T5

3

T24

2

T25

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	355	1			T14	17		T16	8		T104	14
values[0]	4	1			T13	2		T247	1		T162	1
values[1]	620	1			T15	9		T60	14		T91	4
values[2]	2520	1			T11	1		T14	20		T20	33
values[3]	707	1			T16	1		T103	10		T95	23
values[4]	719	1			T19	8		T21	14		T22	10
values[5]	648	1			T13	10		T109	9		T55	19
values[6]	656	1			T21	1		T57	26		T34	36
values[7]	426	1			T203	6		T202	17		T219	3
values[8]	676	1			T15	20		T141	18		T97	11
values[9]	1034	1			T61	16		T59	9		T115	12
minimum	15917	1			T5	3		T24	2		T25	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	653	1			T15	9		T60	14		T91	4
values[1]	2575	1			T11	1		T14	20		T20	33
values[2]	745	1			T16	1		T21	14		T205	20
values[3]	685	1			T19	8		T22	10		T60	17
values[4]	574	1			T13	10		T21	1		T109	9
values[5]	655	1			T57	26		T34	1		T206	34
values[6]	517	1			T15	13		T203	6		T100	1
values[7]	678	1			T15	7		T214	24		T141	18
values[8]	981	1			T14	17		T16	8		T61	16
values[9]	215	1			T104	14		T95	20		T111	14
minimum	16004	1			T5	3		T24	2		T25	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20819

1

T5

3

T24

2

T25

1

auto[1]

3463

1

T14

18

T15

15

T16

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T60	9		T97	1		T98	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T15	4		T91	3		T54	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1239	1			T11	1		T20	33		T23	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T14	11		T203	2		T95	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T16	1		T21	1		T205	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T205	5		T179	3		T210	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T19	4		T22	8		T60	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T208	1		T97	1		T101	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T109	9		T34	15		T94	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T13	1		T21	1		T55	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T130	1		T219	1		T280	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T57	14		T34	1		T206	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T203	4		T101	6		T160	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T15	11		T100	1		T202	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T15	4		T214	13		T96	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T141	9		T130	12		T99	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T61	9		T106	4		T211	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T14	9		T16	8		T59	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T104	1		T95	9		T220	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T111	1		T246	1		T250	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15792	1			T12	15		T14	209		T15	65
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T13	1		T212	9		T124	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T60	5		T97	8		T110	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T15	5		T91	1		T54	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1011	1			T103	9		T121	12		T140	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T14	9		T203	3		T95	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T21	13		T205	12		T204	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T179	31		T210	14		T251	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T19	4		T22	2		T60	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T97	15		T101	13		T125	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T34	18		T94	10		T107	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T13	9		T55	14		T57	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T219	2		T280	9		T222	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T57	12		T206	18		T218	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T203	2		T101	11		T124	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T15	2		T232	7		T284	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T15	3		T214	11		T96	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T141	9		T130	11		T99	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T61	7		T106	2		T260	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T14	8		T59	8		T115	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T104	13		T95	11		T220	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T111	13		T250	12		T176	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T5	3		T24	2		T25	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T13	1		T212	8		T124	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T104	1		T95	9		T118	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T14	9		T16	8		T111	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T13	1		T247	1		T162	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T60	9		T96	8		T97	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T15	4		T91	3		T59	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1242	1			T11	1		T20	33		T23	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T14	11		T54	1		T203	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T16	1		T103	1		T205	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T95	13		T205	5		T179	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T19	4		T21	1		T22	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T101	9		T149	1		T113	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T109	9		T94	1		T207	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T13	1		T55	5		T57	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T34	15		T130	1		T280	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T21	1		T57	14		T34	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T203	4		T219	1		T160	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T202	17		T112	1		T247	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T15	4		T97	1		T209	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T15	11		T141	9		T130	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	320	1			T61	9		T106	4		T214	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T59	1		T115	8		T214	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15774	1			T12	15		T14	209		T15	65
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T104	13		T95	11		T230	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T14	8		T111	13		T250	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T13	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T60	5		T97	8		T110	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T15	5		T91	1		T59	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	984	1			T121	12		T140	12		T221	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T14	9		T54	10		T203	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T103	9		T205	12		T213	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T95	10		T179	19		T251	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T19	4		T21	13		T22	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T101	13		T179	12		T210	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T94	10		T107	3		T228	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T13	9		T55	14		T57	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T34	18		T280	9		T283	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T57	12		T34	1		T206	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T203	2		T219	2		T124	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T272	14		T232	7		T237	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T15	3		T97	10		T209	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T15	2		T141	9		T130	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T61	7		T106	2		T214	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T59	8		T115	4		T96	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	3		T24	2		T25	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T60	6		T97	9		T98	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T15	6		T91	3		T54	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1347	1			T11	1		T20	3		T23	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T14	10		T203	5		T95	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T16	1		T21	14		T205	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T205	1		T179	34		T210	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T19	5		T22	8		T60	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T208	1		T97	16		T101	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T109	1		T34	19		T94	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T13	10		T21	1		T55	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T130	1		T219	3		T280	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T57	13		T34	1		T206	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T203	4		T101	12		T160	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T15	3		T100	1		T202	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T15	5		T214	12		T96	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T141	10		T130	12		T99	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T61	8		T106	5		T211	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T14	9		T16	1		T59	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T104	14		T95	12		T220	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T111	14		T246	1		T250	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15945	1			T5	3		T24	2		T25	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T13	2		T212	9		T124	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T60	8		T98	4		T110	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T15	3		T91	1		T206	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	903	1			T20	30		T235	5		T236	26
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T14	10		T95	12		T232	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T205	2		T204	1		T120	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T205	4		T169	15		T143	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T19	3		T22	2		T60	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T101	8		T125	4		T169	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T109	8		T34	14		T107	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T55	4		T57	8		T123	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T150	10		T222	7		T172	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T57	13		T206	15		T141	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T203	2		T101	5		T160	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T15	10		T202	16		T234	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T15	2		T214	12		T96	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T141	8		T130	11		T99	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T61	8		T106	1		T211	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T14	8		T16	7		T115	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T95	8		T220	14		T151	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T250	14		T314	11		T258	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T96	7		T305	1		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T212	8		T124	3		T293	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T104	14		T95	12		T118	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T14	9		T16	1		T111	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T13	2		T247	1		T162	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T60	6		T96	1		T97	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T15	6		T91	3		T59	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1314	1			T11	1		T20	3		T23	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T14	10		T54	11		T203	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T16	1		T103	10		T205	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T95	11		T205	1		T179	21
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T19	5		T21	14		T22	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T101	14		T149	1		T113	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T109	1		T94	11		T207	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T13	10		T55	15		T57	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T34	19		T130	1		T280	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T21	1		T57	13		T34	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T203	4		T219	3		T160	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T202	1		T112	1		T247	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T15	5		T97	11		T209	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T15	3		T141	10		T130	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	337	1			T61	8		T106	5		T214	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T59	9		T115	5		T214	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15917	1			T5	3		T24	2		T25	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T95	8		T118	9		T230	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T14	8		T16	7		T250	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T60	8		T96	7		T98	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T15	3		T91	1		T206	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	912	1			T20	30		T235	5		T236	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T14	10		T118	10		T143	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T205	2		T120	5		T220	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T95	12		T205	4		T232	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T19	3		T22	2		T60	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T101	8		T169	7		T216	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T109	8		T107	1		T177	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T55	4		T57	8		T125	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T34	14		T150	10		T172	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T57	13		T206	15		T141	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T203	2		T160	6		T124	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T202	16		T234	7		T232	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T15	2		T101	5		T158	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T15	10		T141	8		T130	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T61	8		T106	1		T214	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T115	7		T96	10		T122	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20819

1

T5

3

T24

2

T25

1

auto[1]

auto[0]

3463

1

T14

18

T15

15

T16

7