Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.49	98.98	95.70	100.00	100.00	98.18	98.64	90.95

Total test records in report: 905

T771	/workspace/coverage/default/17.adc_ctrl_lowpower_counter.1858417818	Jan 03 01:15:22 PM PST 24	Jan 03 01:16:46 PM PST 24	28026989926 ps
T772	/workspace/coverage/default/10.adc_ctrl_clock_gating.1710980049	Jan 03 01:15:09 PM PST 24	Jan 03 01:22:00 PM PST 24	318732000792 ps
T773	/workspace/coverage/default/49.adc_ctrl_filters_wakeup.2910994269	Jan 03 01:18:47 PM PST 24	Jan 03 01:23:15 PM PST 24	341919786609 ps
T774	/workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.2045690456	Jan 03 01:17:40 PM PST 24	Jan 03 01:36:31 PM PST 24	494982252726 ps
T775	/workspace/coverage/default/27.adc_ctrl_lowpower_counter.1118868772	Jan 03 01:17:23 PM PST 24	Jan 03 01:17:50 PM PST 24	23062678930 ps
T776	/workspace/coverage/default/22.adc_ctrl_poweron_counter.1700950866	Jan 03 01:15:50 PM PST 24	Jan 03 01:16:47 PM PST 24	5084720380 ps
T777	/workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.2961590388	Jan 03 01:17:27 PM PST 24	Jan 03 01:19:12 PM PST 24	490320720021 ps
T778	/workspace/coverage/default/15.adc_ctrl_poweron_counter.1553529821	Jan 03 01:15:19 PM PST 24	Jan 03 01:16:30 PM PST 24	4017459446 ps
T167	/workspace/coverage/default/20.adc_ctrl_filters_wakeup.2818734666	Jan 03 01:15:49 PM PST 24	Jan 03 01:20:06 PM PST 24	323079251613 ps
T779	/workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.1352033103	Jan 03 01:18:47 PM PST 24	Jan 03 01:22:12 PM PST 24	163160134008 ps
T780	/workspace/coverage/default/6.adc_ctrl_filters_both.3572054302	Jan 03 01:14:52 PM PST 24	Jan 03 01:21:11 PM PST 24	495528053638 ps
T781	/workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.360843741	Jan 03 01:16:20 PM PST 24	Jan 03 01:22:30 PM PST 24	161238412294 ps
T782	/workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.1338359834	Jan 03 01:14:52 PM PST 24	Jan 03 01:22:36 PM PST 24	327854892872 ps
T783	/workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.1925223875	Jan 03 01:15:23 PM PST 24	Jan 03 01:17:52 PM PST 24	81794824106 ps
T784	/workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.2730041815	Jan 03 01:17:42 PM PST 24	Jan 03 01:21:15 PM PST 24	97161761265 ps
T310	/workspace/coverage/default/22.adc_ctrl_filters_interrupt.733552373	Jan 03 01:15:48 PM PST 24	Jan 03 01:30:14 PM PST 24	322351940387 ps
T785	/workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.1757950820	Jan 03 01:16:47 PM PST 24	Jan 03 01:23:06 PM PST 24	162230915444 ps
T786	/workspace/coverage/default/39.adc_ctrl_poweron_counter.1083156591	Jan 03 01:17:41 PM PST 24	Jan 03 01:17:46 PM PST 24	2746277839 ps
T787	/workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.2470698769	Jan 03 01:15:07 PM PST 24	Jan 03 01:18:40 PM PST 24	497534444824 ps
T788	/workspace/coverage/default/42.adc_ctrl_fsm_reset.1486048159	Jan 03 01:17:56 PM PST 24	Jan 03 01:24:26 PM PST 24	98261375183 ps
T292	/workspace/coverage/default/15.adc_ctrl_filters_wakeup.3991109382	Jan 03 01:15:15 PM PST 24	Jan 03 01:17:52 PM PST 24	328081905467 ps
T789	/workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.3223067684	Jan 03 01:17:23 PM PST 24	Jan 03 01:18:40 PM PST 24	128708066075 ps
T790	/workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.4061018600	Jan 03 01:18:27 PM PST 24	Jan 03 01:19:39 PM PST 24	29643869362 ps
T791	/workspace/coverage/default/33.adc_ctrl_smoke.2537521332	Jan 03 01:17:34 PM PST 24	Jan 03 01:17:51 PM PST 24	5789508129 ps
T296	/workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.2902722114	Jan 03 01:18:42 PM PST 24	Jan 03 01:23:44 PM PST 24	409800165078 ps
T792	/workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.2012820052	Jan 03 01:15:23 PM PST 24	Jan 03 01:18:18 PM PST 24	165942933954 ps
T793	/workspace/coverage/default/49.adc_ctrl_fsm_reset.447360441	Jan 03 01:19:04 PM PST 24	Jan 03 01:24:35 PM PST 24	80232393836 ps
T330	/workspace/coverage/default/49.adc_ctrl_filters_both.3847248650	Jan 03 01:18:49 PM PST 24	Jan 03 01:29:04 PM PST 24	499415004845 ps
T794	/workspace/coverage/default/43.adc_ctrl_smoke.578677563	Jan 03 01:18:07 PM PST 24	Jan 03 01:18:45 PM PST 24	5713568652 ps
T795	/workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.3164916598	Jan 03 01:15:47 PM PST 24	Jan 03 01:19:55 PM PST 24	332377218974 ps
T796	/workspace/coverage/default/30.adc_ctrl_smoke.784674083	Jan 03 01:17:15 PM PST 24	Jan 03 01:17:23 PM PST 24	5950756645 ps
T797	/workspace/coverage/default/2.adc_ctrl_smoke.3232564158	Jan 03 01:15:08 PM PST 24	Jan 03 01:16:17 PM PST 24	5748518355 ps
T798	/workspace/coverage/default/0.adc_ctrl_filters_both.1504876672	Jan 03 01:14:44 PM PST 24	Jan 03 01:22:21 PM PST 24	165577903627 ps
T799	/workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.893255391	Jan 03 01:17:44 PM PST 24	Jan 03 01:18:37 PM PST 24	18507370625 ps
T800	/workspace/coverage/default/21.adc_ctrl_poweron_counter.2978161984	Jan 03 01:15:24 PM PST 24	Jan 03 01:16:32 PM PST 24	3364524095 ps
T801	/workspace/coverage/default/15.adc_ctrl_fsm_reset.1548162901	Jan 03 01:15:17 PM PST 24	Jan 03 01:27:51 PM PST 24	120078360868 ps
T278	/workspace/coverage/default/35.adc_ctrl_filters_both.3090552945	Jan 03 01:17:35 PM PST 24	Jan 03 01:20:52 PM PST 24	506220974668 ps
T802	/workspace/coverage/default/10.adc_ctrl_filters_both.3080244434	Jan 03 01:14:54 PM PST 24	Jan 03 01:22:43 PM PST 24	329514894421 ps
T803	/workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.500944482	Jan 03 01:14:50 PM PST 24	Jan 03 01:17:41 PM PST 24	167029290177 ps
T804	/workspace/coverage/default/26.adc_ctrl_poweron_counter.1290429393	Jan 03 01:17:45 PM PST 24	Jan 03 01:18:00 PM PST 24	5561159813 ps
T805	/workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.1644374636	Jan 03 01:18:45 PM PST 24	Jan 03 01:21:48 PM PST 24	192548635180 ps
T265	/workspace/coverage/default/36.adc_ctrl_clock_gating.586365100	Jan 03 01:17:39 PM PST 24	Jan 03 01:21:24 PM PST 24	326638056205 ps
T806	/workspace/coverage/default/31.adc_ctrl_stress_all.2401536814	Jan 03 01:17:27 PM PST 24	Jan 03 01:22:52 PM PST 24	250576371330 ps
T50	/workspace/coverage/default/1.adc_ctrl_sec_cm.915141254	Jan 03 01:14:55 PM PST 24	Jan 03 01:16:07 PM PST 24	4490402596 ps
T807	/workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.3810874570	Jan 03 01:15:05 PM PST 24	Jan 03 01:17:00 PM PST 24	19801216518 ps
T808	/workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.3710330600	Jan 03 01:15:20 PM PST 24	Jan 03 01:18:30 PM PST 24	329478660280 ps
T809	/workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.2292333587	Jan 03 01:17:29 PM PST 24	Jan 03 01:17:57 PM PST 24	39334894771 ps
T810	/workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.2131560735	Jan 03 01:15:07 PM PST 24	Jan 03 01:17:49 PM PST 24	162123918895 ps
T811	/workspace/coverage/default/27.adc_ctrl_stress_all.110425400	Jan 03 01:16:45 PM PST 24	Jan 03 01:26:53 PM PST 24	357128068305 ps
T812	/workspace/coverage/default/24.adc_ctrl_alert_test.3059057340	Jan 03 01:16:31 PM PST 24	Jan 03 01:16:56 PM PST 24	407012003 ps
T813	/workspace/coverage/default/27.adc_ctrl_filters_polled.494114183	Jan 03 01:17:42 PM PST 24	Jan 03 01:24:43 PM PST 24	325913093500 ps
T334	/workspace/coverage/default/2.adc_ctrl_filters_interrupt.2822573465	Jan 03 01:15:01 PM PST 24	Jan 03 01:19:25 PM PST 24	335179267953 ps
T814	/workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.3151061776	Jan 03 01:15:29 PM PST 24	Jan 03 01:22:17 PM PST 24	259355737680 ps
T815	/workspace/coverage/default/29.adc_ctrl_filters_wakeup.2693612855	Jan 03 01:17:39 PM PST 24	Jan 03 01:28:54 PM PST 24	368285174519 ps
T816	/workspace/coverage/default/31.adc_ctrl_filters_wakeup.3051044969	Jan 03 01:17:30 PM PST 24	Jan 03 01:21:37 PM PST 24	169011718998 ps
T817	/workspace/coverage/default/24.adc_ctrl_poweron_counter.2607936403	Jan 03 01:17:41 PM PST 24	Jan 03 01:17:47 PM PST 24	3681507441 ps
T818	/workspace/coverage/default/7.adc_ctrl_filters_wakeup.3828253043	Jan 03 01:15:10 PM PST 24	Jan 03 01:21:31 PM PST 24	331148163632 ps
T819	/workspace/coverage/default/39.adc_ctrl_smoke.1867027647	Jan 03 01:17:31 PM PST 24	Jan 03 01:17:39 PM PST 24	5922652507 ps
T346	/workspace/coverage/default/18.adc_ctrl_fsm_reset.4285184042	Jan 03 01:15:27 PM PST 24	Jan 03 01:22:30 PM PST 24	71596926233 ps
T820	/workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.3157928901	Jan 03 01:19:02 PM PST 24	Jan 03 01:36:37 PM PST 24	494121330457 ps
T821	/workspace/coverage/default/4.adc_ctrl_filters_interrupt.2005976113	Jan 03 01:14:47 PM PST 24	Jan 03 01:16:08 PM PST 24	162018421308 ps
T822	/workspace/coverage/default/17.adc_ctrl_filters_polled.2644751972	Jan 03 01:15:16 PM PST 24	Jan 03 01:19:28 PM PST 24	328214611472 ps
T168	/workspace/coverage/default/21.adc_ctrl_filters_polled.2425257280	Jan 03 01:15:21 PM PST 24	Jan 03 01:17:51 PM PST 24	495390729504 ps
T823	/workspace/coverage/default/40.adc_ctrl_filters_both.2754800123	Jan 03 01:17:29 PM PST 24	Jan 03 01:24:06 PM PST 24	162708725231 ps
T824	/workspace/coverage/default/35.adc_ctrl_filters_wakeup.2389784533	Jan 03 01:17:31 PM PST 24	Jan 03 01:23:48 PM PST 24	325477618437 ps
T825	/workspace/coverage/default/48.adc_ctrl_alert_test.1397593123	Jan 03 01:18:44 PM PST 24	Jan 03 01:19:03 PM PST 24	497586510 ps
T826	/workspace/coverage/default/36.adc_ctrl_filters_wakeup.1004712103	Jan 03 01:17:40 PM PST 24	Jan 03 01:18:08 PM PST 24	166046461758 ps
T827	/workspace/coverage/default/23.adc_ctrl_alert_test.1573216540	Jan 03 01:17:21 PM PST 24	Jan 03 01:17:25 PM PST 24	395513379 ps
T828	/workspace/coverage/default/27.adc_ctrl_clock_gating.3864929647	Jan 03 01:17:24 PM PST 24	Jan 03 01:30:04 PM PST 24	333874664622 ps
T829	/workspace/coverage/default/15.adc_ctrl_lowpower_counter.1695615482	Jan 03 01:15:22 PM PST 24	Jan 03 01:17:52 PM PST 24	38293171466 ps
T268	/workspace/coverage/default/8.adc_ctrl_filters_interrupt.1959374747	Jan 03 01:15:13 PM PST 24	Jan 03 01:19:49 PM PST 24	326665662153 ps
T830	/workspace/coverage/default/6.adc_ctrl_lowpower_counter.1041256652	Jan 03 01:15:07 PM PST 24	Jan 03 01:16:29 PM PST 24	28216184424 ps
T831	/workspace/coverage/default/1.adc_ctrl_lowpower_counter.2479678611	Jan 03 01:14:56 PM PST 24	Jan 03 01:16:34 PM PST 24	29640432430 ps
T832	/workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.2909555100	Jan 03 01:15:07 PM PST 24	Jan 03 01:19:59 PM PST 24	495250765801 ps
T833	/workspace/coverage/default/37.adc_ctrl_fsm_reset.1088093092	Jan 03 01:17:28 PM PST 24	Jan 03 01:24:55 PM PST 24	136947620653 ps
T253	/workspace/coverage/default/19.adc_ctrl_filters_interrupt.3940155860	Jan 03 01:15:32 PM PST 24	Jan 03 01:22:07 PM PST 24	491976257042 ps
T834	/workspace/coverage/default/32.adc_ctrl_stress_all.2858456198	Jan 03 01:17:34 PM PST 24	Jan 03 01:37:57 PM PST 24	329228012855 ps
T835	/workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.1336753979	Jan 03 01:15:31 PM PST 24	Jan 03 01:26:27 PM PST 24	488677548407 ps
T336	/workspace/coverage/default/44.adc_ctrl_filters_both.455070861	Jan 03 01:19:03 PM PST 24	Jan 03 01:20:32 PM PST 24	330063240483 ps
T836	/workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.463123838	Jan 03 01:17:37 PM PST 24	Jan 03 01:36:55 PM PST 24	491273082421 ps
T837	/workspace/coverage/default/42.adc_ctrl_filters_polled.1331592318	Jan 03 01:18:03 PM PST 24	Jan 03 01:19:35 PM PST 24	493976400761 ps
T838	/workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.1485398100	Jan 03 01:19:00 PM PST 24	Jan 03 01:27:37 PM PST 24	324364030396 ps
T839	/workspace/coverage/default/32.adc_ctrl_clock_gating.1110551724	Jan 03 01:17:33 PM PST 24	Jan 03 01:20:10 PM PST 24	329118763894 ps
T840	/workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.3848734655	Jan 03 01:17:44 PM PST 24	Jan 03 01:21:07 PM PST 24	318164436230 ps
T841	/workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.3509123866	Jan 03 01:17:12 PM PST 24	Jan 03 01:22:04 PM PST 24	488448563515 ps
T842	/workspace/coverage/default/28.adc_ctrl_clock_gating.3050354015	Jan 03 01:17:30 PM PST 24	Jan 03 01:20:44 PM PST 24	167371710947 ps
T843	/workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.781567153	Jan 03 01:17:41 PM PST 24	Jan 03 01:20:54 PM PST 24	336120939741 ps
T844	/workspace/coverage/default/30.adc_ctrl_lowpower_counter.2954606406	Jan 03 01:17:14 PM PST 24	Jan 03 01:18:41 PM PST 24	35431819723 ps
T845	/workspace/coverage/default/27.adc_ctrl_filters_both.1938441299	Jan 03 01:16:46 PM PST 24	Jan 03 01:36:06 PM PST 24	506536323919 ps
T846	/workspace/coverage/default/23.adc_ctrl_smoke.69342188	Jan 03 01:15:45 PM PST 24	Jan 03 01:16:49 PM PST 24	5576554366 ps
T847	/workspace/coverage/default/7.adc_ctrl_clock_gating.796675869	Jan 03 01:15:02 PM PST 24	Jan 03 01:20:30 PM PST 24	490251231188 ps
T848	/workspace/coverage/default/39.adc_ctrl_filters_polled.3146009145	Jan 03 01:17:35 PM PST 24	Jan 03 01:21:10 PM PST 24	492611328130 ps
T849	/workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.2487204190	Jan 03 01:14:49 PM PST 24	Jan 03 01:36:22 PM PST 24	500532495849 ps
T264	/workspace/coverage/default/12.adc_ctrl_stress_all.1909252272	Jan 03 01:15:25 PM PST 24	Jan 03 01:18:37 PM PST 24	356971919223 ps
T850	/workspace/coverage/default/32.adc_ctrl_smoke.4133238504	Jan 03 01:17:34 PM PST 24	Jan 03 01:17:53 PM PST 24	5795190007 ps
T851	/workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2982991282	Jan 03 12:59:11 PM PST 24	Jan 03 01:00:42 PM PST 24	25635610999 ps
T852	/workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3001539860	Jan 03 12:59:10 PM PST 24	Jan 03 01:00:03 PM PST 24	1188807911 ps
T853	/workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.1868845094	Jan 03 12:58:43 PM PST 24	Jan 03 12:59:14 PM PST 24	1010584715 ps
T854	/workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3675184435	Jan 03 12:58:49 PM PST 24	Jan 03 12:59:25 PM PST 24	4570866960 ps
T83	/workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1989893217	Jan 03 12:58:43 PM PST 24	Jan 03 12:59:15 PM PST 24	863493097 ps
T855	/workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.21714215	Jan 03 12:59:03 PM PST 24	Jan 03 12:59:49 PM PST 24	1039344943 ps
T856	/workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3055235173	Jan 03 12:58:54 PM PST 24	Jan 03 12:59:30 PM PST 24	525597385 ps
T857	/workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.496561496	Jan 03 12:59:11 PM PST 24	Jan 03 01:00:04 PM PST 24	541303162 ps
T858	/workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.1966871193	Jan 03 12:59:06 PM PST 24	Jan 03 12:59:52 PM PST 24	351924197 ps
T859	/workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3383837160	Jan 03 12:59:00 PM PST 24	Jan 03 12:59:43 PM PST 24	352596866 ps
T860	/workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2803428614	Jan 03 12:58:34 PM PST 24	Jan 03 12:59:08 PM PST 24	517501367 ps
T861	/workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1377340945	Jan 03 12:58:47 PM PST 24	Jan 03 12:59:23 PM PST 24	4211425278 ps
T862	/workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3542407984	Jan 03 12:58:56 PM PST 24	Jan 03 12:59:38 PM PST 24	9680277718 ps
T863	/workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2280642067	Jan 03 12:59:08 PM PST 24	Jan 03 01:00:08 PM PST 24	2669865614 ps
T864	/workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2252397824	Jan 03 12:59:11 PM PST 24	Jan 03 01:00:07 PM PST 24	503979370 ps
T865	/workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.1983370000	Jan 03 12:58:47 PM PST 24	Jan 03 12:59:19 PM PST 24	332288942 ps
T866	/workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.3230369622	Jan 03 12:58:47 PM PST 24	Jan 03 12:59:29 PM PST 24	4799105779 ps
T867	/workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.4068330159	Jan 03 12:58:49 PM PST 24	Jan 03 12:59:31 PM PST 24	4830593248 ps
T868	/workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2392316218	Jan 03 12:59:13 PM PST 24	Jan 03 01:00:08 PM PST 24	605593288 ps
T869	/workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3489159459	Jan 03 12:58:52 PM PST 24	Jan 03 12:59:36 PM PST 24	5080351570 ps
T870	/workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.677122646	Jan 03 12:59:03 PM PST 24	Jan 03 12:59:50 PM PST 24	651616246 ps
T86	/workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.4040493663	Jan 03 12:59:15 PM PST 24	Jan 03 01:00:26 PM PST 24	25550212990 ps
T871	/workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.2576779446	Jan 03 12:58:50 PM PST 24	Jan 03 12:59:23 PM PST 24	514160898 ps
T872	/workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3898429527	Jan 03 12:59:07 PM PST 24	Jan 03 12:59:57 PM PST 24	389989000 ps
T873	/workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3399682575	Jan 03 12:58:47 PM PST 24	Jan 03 12:59:27 PM PST 24	2598973746 ps
T874	/workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.560265319	Jan 03 12:58:47 PM PST 24	Jan 03 12:59:39 PM PST 24	8311447729 ps
T875	/workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1741700816	Jan 03 12:58:47 PM PST 24	Jan 03 12:59:19 PM PST 24	956844723 ps
T87	/workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2445772340	Jan 03 12:59:06 PM PST 24	Jan 03 01:00:14 PM PST 24	22824253552 ps
T876	/workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1511726289	Jan 03 12:59:12 PM PST 24	Jan 03 01:00:07 PM PST 24	460716957 ps
T877	/workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.1146012092	Jan 03 12:59:13 PM PST 24	Jan 03 01:00:08 PM PST 24	322368105 ps
T878	/workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.4199483971	Jan 03 12:58:45 PM PST 24	Jan 03 12:59:17 PM PST 24	352581778 ps
T879	/workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.21193395	Jan 03 12:58:55 PM PST 24	Jan 03 12:59:34 PM PST 24	498627668 ps
T880	/workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.4195084157	Jan 03 12:58:50 PM PST 24	Jan 03 12:59:35 PM PST 24	4218521497 ps
T881	/workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1383941101	Jan 03 12:58:51 PM PST 24	Jan 03 12:59:25 PM PST 24	570670137 ps
T882	/workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3848724307	Jan 03 12:59:21 PM PST 24	Jan 03 01:00:16 PM PST 24	315297689 ps
T883	/workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2657769717	Jan 03 12:58:47 PM PST 24	Jan 03 12:59:21 PM PST 24	511256423 ps
T884	/workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2084615914	Jan 03 12:59:09 PM PST 24	Jan 03 01:00:02 PM PST 24	309958069 ps
T885	/workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3162975631	Jan 03 12:58:43 PM PST 24	Jan 03 12:59:24 PM PST 24	3993081629 ps
T886	/workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2447405406	Jan 03 12:58:48 PM PST 24	Jan 03 12:59:35 PM PST 24	8508801554 ps
T88	/workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.4195432414	Jan 03 12:58:47 PM PST 24	Jan 03 12:59:18 PM PST 24	464933826 ps
T887	/workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.274318738	Jan 03 12:59:01 PM PST 24	Jan 03 12:59:45 PM PST 24	496172434 ps
T888	/workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2131406854	Jan 03 12:58:49 PM PST 24	Jan 03 12:59:23 PM PST 24	495663463 ps
T889	/workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2799937800	Jan 03 12:58:46 PM PST 24	Jan 03 12:59:23 PM PST 24	2207661015 ps
T890	/workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.1651896935	Jan 03 12:59:06 PM PST 24	Jan 03 12:59:54 PM PST 24	446375642 ps
T891	/workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1428238904	Jan 03 12:58:54 PM PST 24	Jan 03 12:59:31 PM PST 24	503801868 ps
T89	/workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.6900330	Jan 03 12:59:06 PM PST 24	Jan 03 12:59:51 PM PST 24	433543374 ps
T892	/workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1661360746	Jan 03 12:58:56 PM PST 24	Jan 03 12:59:35 PM PST 24	607308403 ps
T893	/workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.1904000247	Jan 03 12:58:49 PM PST 24	Jan 03 12:59:22 PM PST 24	355594571 ps
T894	/workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1635818208	Jan 03 12:58:41 PM PST 24	Jan 03 12:59:12 PM PST 24	342816352 ps
T895	/workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.711937557	Jan 03 12:58:43 PM PST 24	Jan 03 12:59:23 PM PST 24	4186678036 ps
T896	/workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1248913487	Jan 03 12:58:52 PM PST 24	Jan 03 12:59:31 PM PST 24	4520067358 ps
T897	/workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.457661811	Jan 03 12:58:58 PM PST 24	Jan 03 12:59:40 PM PST 24	341698124 ps
T898	/workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3728292188	Jan 03 12:59:03 PM PST 24	Jan 03 12:59:49 PM PST 24	553642617 ps
T899	/workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.3975018660	Jan 03 12:59:01 PM PST 24	Jan 03 12:59:44 PM PST 24	406263558 ps
T900	/workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.594816934	Jan 03 12:58:46 PM PST 24	Jan 03 12:59:18 PM PST 24	474103702 ps
T901	/workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3778516459	Jan 03 12:58:46 PM PST 24	Jan 03 12:59:18 PM PST 24	421268249 ps
T902	/workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.3351386623	Jan 03 12:59:03 PM PST 24	Jan 03 12:59:47 PM PST 24	317452996 ps
T903	/workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3187120545	Jan 03 12:59:00 PM PST 24	Jan 03 12:59:41 PM PST 24	488372381 ps
T904	/workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3883197118	Jan 03 12:58:49 PM PST 24	Jan 03 12:59:22 PM PST 24	479919281 ps
T905	/workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1888122710	Jan 03 12:58:48 PM PST 24	Jan 03 12:59:24 PM PST 24	2892560358 ps

Test location	/workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.621612235
Short name	T1
Test name
Test status
Simulation time	4691005974 ps
CPU time	4.67 seconds
Started	Jan 03 12:59:06 PM PST 24
Finished	Jan 03 12:59:57 PM PST 24
Peak memory	200820 kb
Host	smart-5313ef3f-2731-4a41-825e-701f226f7155
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621612235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_int g_err.621612235
Directory	/workspace/1.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.900909462
Short name	T15
Test name
Test status
Simulation time	582973275407 ps
CPU time	141.61 seconds
Started	Jan 03 01:14:56 PM PST 24
Finished	Jan 03 01:18:19 PM PST 24
Peak memory	200924 kb
Host	smart-e268e00d-3a94-42dc-8e58-f3e824c789bc
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900909462 -assert nopo stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.900909462
Directory	/workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/46.adc_ctrl_stress_all.75204151
Short name	T14
Test name
Test status
Simulation time	470678567355 ps
CPU time	1394.52 seconds
Started	Jan 03 01:19:02 PM PST 24
Finished	Jan 03 01:42:25 PM PST 24
Peak memory	201256 kb
Host	smart-5a5f7b7e-3d67-4706-9b7e-52d3a40cb98f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75204151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_ all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all.75204151
Directory	/workspace/46.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.568075994
Short name	T25
Test name
Test status
Simulation time	509376697 ps
CPU time	0.89 seconds
Started	Jan 03 12:59:09 PM PST 24
Finished	Jan 03 01:00:01 PM PST 24
Peak memory	200464 kb
Host	smart-9cc66730-7c55-4da3-92b3-3a76b2956ca3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568075994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.568075994
Directory	/workspace/45.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3528677628
Short name	T30
Test name
Test status
Simulation time	37011886554 ps
CPU time	189 seconds
Started	Jan 03 12:58:58 PM PST 24
Finished	Jan 03 01:02:46 PM PST 24
Peak memory	200848 kb
Host	smart-a03d0888-caca-42dc-a4b0-e212e6093389
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528677628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_ bash.3528677628
Directory	/workspace/0.adc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/default/29.adc_ctrl_clock_gating.2207287608
Short name	T96
Test name
Test status
Simulation time	494947907690 ps
CPU time	141.91 seconds
Started	Jan 03 01:17:12 PM PST 24
Finished	Jan 03 01:19:37 PM PST 24
Peak memory	201004 kb
Host	smart-b76cf81b-105a-4e4e-b2a5-2324fde36461
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207287608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat ing.2207287608
Directory	/workspace/29.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/39.adc_ctrl_filters_both.3765453046
Short name	T205
Test name
Test status
Simulation time	494953990390 ps
CPU time	1130.75 seconds
Started	Jan 03 01:17:39 PM PST 24
Finished	Jan 03 01:36:33 PM PST 24
Peak memory	200952 kb
Host	smart-42d1e341-5af2-40ef-91d1-09d38fec2af7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3765453046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.3765453046
Directory	/workspace/39.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/19.adc_ctrl_clock_gating.1932246685
Short name	T34
Test name
Test status
Simulation time	498958075483 ps
CPU time	490.85 seconds
Started	Jan 03 01:15:38 PM PST 24
Finished	Jan 03 01:24:47 PM PST 24
Peak memory	200940 kb
Host	smart-298b165f-a1bb-4025-9abd-45c1702f7c29
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932246685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat ing.1932246685
Directory	/workspace/19.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/25.adc_ctrl_clock_gating.4077871827
Short name	T169
Test name
Test status
Simulation time	484865901604 ps
CPU time	268.88 seconds
Started	Jan 03 01:16:30 PM PST 24
Finished	Jan 03 01:21:24 PM PST 24
Peak memory	200960 kb
Host	smart-ff82fe18-5ce6-46c0-91ad-7d3e3dac363a
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077871827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat ing.4077871827
Directory	/workspace/25.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/19.adc_ctrl_filters_both.249870418
Short name	T124
Test name
Test status
Simulation time	495796676688 ps
CPU time	1112.77 seconds
Started	Jan 03 01:15:29 PM PST 24
Finished	Jan 03 01:35:04 PM PST 24
Peak memory	200808 kb
Host	smart-b1e202c8-152e-41ab-9570-daadb56fae90
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=249870418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.249870418
Directory	/workspace/19.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1890492669
Short name	T64
Test name
Test status
Simulation time	490422995 ps
CPU time	2.37 seconds
Started	Jan 03 12:59:14 PM PST 24
Finished	Jan 03 01:00:11 PM PST 24
Peak memory	200860 kb
Host	smart-619c8000-26cb-4621-afb0-b1c38c82f1c6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890492669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.1890492669
Directory	/workspace/9.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/default/18.adc_ctrl_clock_gating.4247199052
Short name	T19
Test name
Test status
Simulation time	183277746170 ps
CPU time	259 seconds
Started	Jan 03 01:15:23 PM PST 24
Finished	Jan 03 01:20:48 PM PST 24
Peak memory	200880 kb
Host	smart-2cdb064c-c9b2-49fd-98b3-2a4e66adb8ac
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247199052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat ing.4247199052
Directory	/workspace/18.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/33.adc_ctrl_filters_wakeup.2271014967
Short name	T120
Test name
Test status
Simulation time	494739425775 ps
CPU time	167.57 seconds
Started	Jan 03 01:17:34 PM PST 24
Finished	Jan 03 01:20:26 PM PST 24
Peak memory	201024 kb
Host	smart-8facf725-7c90-414e-8ceb-c9855cf9ea1d
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271014967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters _wakeup.2271014967
Directory	/workspace/33.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/37.adc_ctrl_clock_gating.11083316
Short name	T57
Test name
Test status
Simulation time	332166744363 ps
CPU time	702.9 seconds
Started	Jan 03 01:17:56 PM PST 24
Finished	Jan 03 01:29:55 PM PST 24
Peak memory	200932 kb
Host	smart-e89b6e6f-01c7-455a-a98e-005af8f5140e
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11083316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gatin g.11083316
Directory	/workspace/37.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/16.adc_ctrl_filters_wakeup.3860252095
Short name	T118
Test name
Test status
Simulation time	507032114161 ps
CPU time	1110.53 seconds
Started	Jan 03 01:15:09 PM PST 24
Finished	Jan 03 01:34:45 PM PST 24
Peak memory	200384 kb
Host	smart-5c2c1673-809e-48cc-af87-878201751074
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860252095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters _wakeup.3860252095
Directory	/workspace/16.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/20.adc_ctrl_clock_gating.1050733186
Short name	T206
Test name
Test status
Simulation time	330263556528 ps
CPU time	185.13 seconds
Started	Jan 03 01:15:16 PM PST 24
Finished	Jan 03 01:19:27 PM PST 24
Peak memory	200888 kb
Host	smart-45369ce9-1f7a-4cbf-98a5-3b62b208fb9b
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050733186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat ing.1050733186
Directory	/workspace/20.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/5.adc_ctrl_clock_gating.211100939
Short name	T263
Test name
Test status
Simulation time	488254439713 ps
CPU time	561.52 seconds
Started	Jan 03 01:14:45 PM PST 24
Finished	Jan 03 01:25:00 PM PST 24
Peak memory	200920 kb
Host	smart-bc305e50-af2a-465d-885a-927642d0e750
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211100939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gatin g.211100939
Directory	/workspace/5.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/30.adc_ctrl_filters_both.2905036708
Short name	T150
Test name
Test status
Simulation time	497758771002 ps
CPU time	239.61 seconds
Started	Jan 03 01:17:14 PM PST 24
Finished	Jan 03 01:21:17 PM PST 24
Peak memory	200924 kb
Host	smart-2f61e350-987b-4ae1-bddb-51d1ddb429e5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2905036708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.2905036708
Directory	/workspace/30.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.1076373392
Short name	T121
Test name
Test status
Simulation time	329612896076 ps
CPU time	213.75 seconds
Started	Jan 03 01:17:31 PM PST 24
Finished	Jan 03 01:21:09 PM PST 24
Peak memory	200856 kb
Host	smart-30ec5ec0-8d80-4b98-acd6-0f3df7425528
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076373392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru pt_fixed.1076373392
Directory	/workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/13.adc_ctrl_clock_gating.1833905496
Short name	T284
Test name
Test status
Simulation time	494190809513 ps
CPU time	1178.8 seconds
Started	Jan 03 01:15:00 PM PST 24
Finished	Jan 03 01:35:43 PM PST 24
Peak memory	200976 kb
Host	smart-99fde301-b29e-458c-8edb-1b640c1d3703
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833905496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat ing.1833905496
Directory	/workspace/13.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/12.adc_ctrl_filters_interrupt.3353536675
Short name	T111
Test name
Test status
Simulation time	332304180406 ps
CPU time	79.49 seconds
Started	Jan 03 01:15:22 PM PST 24
Finished	Jan 03 01:17:49 PM PST 24
Peak memory	200892 kb
Host	smart-f4556a23-519d-4dec-93c8-9428ec92d499
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3353536675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.3353536675
Directory	/workspace/12.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/27.adc_ctrl_filters_interrupt.2803968845
Short name	T200
Test name
Test status
Simulation time	483477948327 ps
CPU time	1042.93 seconds
Started	Jan 03 01:17:25 PM PST 24
Finished	Jan 03 01:34:51 PM PST 24
Peak memory	200932 kb
Host	smart-65513fbc-e486-4e38-a381-615be5886691
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2803968845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.2803968845
Directory	/workspace/27.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/10.adc_ctrl_stress_all.586398914
Short name	T130
Test name
Test status
Simulation time	591039721544 ps
CPU time	1026.72 seconds
Started	Jan 03 01:15:07 PM PST 24
Finished	Jan 03 01:33:18 PM PST 24
Peak memory	217688 kb
Host	smart-db9f4c21-c05b-4b60-ad5a-3d23b1dde0d2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586398914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all. 586398914
Directory	/workspace/10.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.798932979
Short name	T203
Test name
Test status
Simulation time	131619830840 ps
CPU time	80.91 seconds
Started	Jan 03 01:17:14 PM PST 24
Finished	Jan 03 01:18:38 PM PST 24
Peak memory	209180 kb
Host	smart-d65ce279-1fe1-4ca6-a97c-83f54566dd09
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798932979 -assert nopo stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.798932979
Directory	/workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/33.adc_ctrl_clock_gating.3067792867
Short name	T242
Test name
Test status
Simulation time	485779255698 ps
CPU time	615.04 seconds
Started	Jan 03 01:17:42 PM PST 24
Finished	Jan 03 01:27:59 PM PST 24
Peak memory	200956 kb
Host	smart-01ec7f6f-934e-4d24-9048-1d5be47938af
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067792867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat ing.3067792867
Directory	/workspace/33.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/0.adc_ctrl_sec_cm.2233256243
Short name	T47
Test name
Test status
Simulation time	4836069140 ps
CPU time	2.5 seconds
Started	Jan 03 01:14:55 PM PST 24
Finished	Jan 03 01:15:58 PM PST 24
Peak memory	216080 kb
Host	smart-ed65bd38-4b40-406c-b1f7-3d2e36670787
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233256243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.2233256243
Directory	/workspace/0.adc_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.1247040659
Short name	T107
Test name
Test status
Simulation time	26903194329 ps
CPU time	83.44 seconds
Started	Jan 03 01:15:48 PM PST 24
Finished	Jan 03 01:18:05 PM PST 24
Peak memory	209448 kb
Host	smart-8d692fe5-3cf9-46fb-ac4b-4f1a25af7716
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247040659 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.1247040659
Directory	/workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/24.adc_ctrl_filters_interrupt.2638896060
Short name	T215
Test name
Test status
Simulation time	496461082601 ps
CPU time	837.26 seconds
Started	Jan 03 01:18:00 PM PST 24
Finished	Jan 03 01:32:10 PM PST 24
Peak memory	200900 kb
Host	smart-e4c54ce7-dc5a-494a-a17e-4fb4f19bfd82
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2638896060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.2638896060
Directory	/workspace/24.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/31.adc_ctrl_clock_gating.2865439619
Short name	T172
Test name
Test status
Simulation time	493055988552 ps
CPU time	289.08 seconds
Started	Jan 03 01:17:28 PM PST 24
Finished	Jan 03 01:22:21 PM PST 24
Peak memory	200912 kb
Host	smart-30adba76-01de-4205-9ca3-40a432a6805f
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865439619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat ing.2865439619
Directory	/workspace/31.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/24.adc_ctrl_filters_both.3779125978
Short name	T244
Test name
Test status
Simulation time	502744674167 ps
CPU time	557.33 seconds
Started	Jan 03 01:17:38 PM PST 24
Finished	Jan 03 01:26:59 PM PST 24
Peak memory	200912 kb
Host	smart-7d84ffcf-4000-4960-99f2-25e72da5c1a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3779125978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.3779125978
Directory	/workspace/24.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/41.adc_ctrl_clock_gating.634449663
Short name	T289
Test name
Test status
Simulation time	481947716180 ps
CPU time	650.34 seconds
Started	Jan 03 01:17:53 PM PST 24
Finished	Jan 03 01:29:02 PM PST 24
Peak memory	200904 kb
Host	smart-f59bdc3a-3c4a-4ac3-9b48-42fb89143249
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634449663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gati ng.634449663
Directory	/workspace/41.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/35.adc_ctrl_filters_both.3090552945
Short name	T278
Test name
Test status
Simulation time	506220974668 ps
CPU time	193.02 seconds
Started	Jan 03 01:17:35 PM PST 24
Finished	Jan 03 01:20:52 PM PST 24
Peak memory	200912 kb
Host	smart-699cd59a-25db-4677-9c28-9d3c926e7520
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3090552945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.3090552945
Directory	/workspace/35.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/38.adc_ctrl_filters_interrupt.4262583640
Short name	T272
Test name
Test status
Simulation time	328286292034 ps
CPU time	203.63 seconds
Started	Jan 03 01:17:27 PM PST 24
Finished	Jan 03 01:20:55 PM PST 24
Peak memory	200960 kb
Host	smart-6341301c-9a02-4b44-9ea3-65377ca2a365
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4262583640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.4262583640
Directory	/workspace/38.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/12.adc_ctrl_clock_gating.3766044989
Short name	T115
Test name
Test status
Simulation time	168323752797 ps
CPU time	147.46 seconds
Started	Jan 03 01:15:24 PM PST 24
Finished	Jan 03 01:18:56 PM PST 24
Peak memory	200984 kb
Host	smart-354a6fcb-a013-43e4-b3e0-2227a4138e05
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766044989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat ing.3766044989
Directory	/workspace/12.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/19.adc_ctrl_filters_wakeup.2789130343
Short name	T241
Test name
Test status
Simulation time	335272980674 ps
CPU time	749.55 seconds
Started	Jan 03 01:15:42 PM PST 24
Finished	Jan 03 01:29:09 PM PST 24
Peak memory	200908 kb
Host	smart-a0b9a90e-f5f1-47a2-bd3c-926c1f65bbf7
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789130343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters _wakeup.2789130343
Directory	/workspace/19.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.3615775742
Short name	T423
Test name
Test status
Simulation time	324729187544 ps
CPU time	204.6 seconds
Started	Jan 03 01:14:46 PM PST 24
Finished	Jan 03 01:19:05 PM PST 24
Peak memory	200820 kb
Host	smart-0a37dad2-7886-4afc-8d76-e12dbb53b238
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615775742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0. adc_ctrl_filters_wakeup_fixed.3615775742
Directory	/workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2110403494
Short name	T40
Test name
Test status
Simulation time	530044689 ps
CPU time	3.24 seconds
Started	Jan 03 12:58:46 PM PST 24
Finished	Jan 03 12:59:19 PM PST 24
Peak memory	200800 kb
Host	smart-61bf39d0-9399-4a5c-95d4-0d3a969c6400
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110403494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.2110403494
Directory	/workspace/19.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/default/16.adc_ctrl_clock_gating.3456516725
Short name	T232
Test name
Test status
Simulation time	493844908502 ps
CPU time	210.75 seconds
Started	Jan 03 01:15:09 PM PST 24
Finished	Jan 03 01:19:45 PM PST 24
Peak memory	200832 kb
Host	smart-9bed4e3b-bf07-41bf-b536-160ab78b5daf
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456516725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat ing.3456516725
Directory	/workspace/16.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/25.adc_ctrl_stress_all.1293471799
Short name	T315
Test name
Test status
Simulation time	811595954957 ps
CPU time	968.78 seconds
Started	Jan 03 01:17:14 PM PST 24
Finished	Jan 03 01:33:27 PM PST 24
Peak memory	200940 kb
Host	smart-75931c40-93a7-4f05-b6c8-f323f3bc55f4
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293471799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all .1293471799
Directory	/workspace/25.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/5.adc_ctrl_stress_all.1075666511
Short name	T184
Test name
Test status
Simulation time	303058882531 ps
CPU time	694.04 seconds
Started	Jan 03 01:14:49 PM PST 24
Finished	Jan 03 01:27:22 PM PST 24
Peak memory	211548 kb
Host	smart-112fc654-8f4a-44fe-aa86-e6d20fad790b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075666511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all. 1075666511
Directory	/workspace/5.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/45.adc_ctrl_stress_all.161230475
Short name	T298
Test name
Test status
Simulation time	337575266149 ps
CPU time	320.86 seconds
Started	Jan 03 01:18:40 PM PST 24
Finished	Jan 03 01:24:20 PM PST 24
Peak memory	200860 kb
Host	smart-679e5bd6-6085-4773-aa65-ca15ffae198c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161230475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all. 161230475
Directory	/workspace/45.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.2902722114
Short name	T296
Test name
Test status
Simulation time	409800165078 ps
CPU time	284.74 seconds
Started	Jan 03 01:18:42 PM PST 24
Finished	Jan 03 01:23:44 PM PST 24
Peak memory	217060 kb
Host	smart-44199510-0753-4ba3-8104-47f39b567cdd
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902722114 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.2902722114
Directory	/workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/2.adc_ctrl_filters_wakeup.4040833840
Short name	T279
Test name
Test status
Simulation time	164404174175 ps
CPU time	346.16 seconds
Started	Jan 03 01:15:07 PM PST 24
Finished	Jan 03 01:21:58 PM PST 24
Peak memory	200908 kb
Host	smart-6291e60f-4404-453c-bf5f-de393d172b1e
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040833840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_ wakeup.4040833840
Directory	/workspace/2.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/21.adc_ctrl_filters_both.4230056756
Short name	T239
Test name
Test status
Simulation time	328792998506 ps
CPU time	380.12 seconds
Started	Jan 03 01:15:23 PM PST 24
Finished	Jan 03 01:22:50 PM PST 24
Peak memory	200888 kb
Host	smart-8939d6cc-cbf7-450e-b89f-554e12fbe4fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4230056756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.4230056756
Directory	/workspace/21.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.716560502
Short name	T125
Test name
Test status
Simulation time	287462146346 ps
CPU time	223.94 seconds
Started	Jan 03 01:14:44 PM PST 24
Finished	Jan 03 01:19:21 PM PST 24
Peak memory	209556 kb
Host	smart-aa81535f-0803-4f5a-ae6e-de1d2587e4b6
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716560502 -assert nopo stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.716560502
Directory	/workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/7.adc_ctrl_filters_interrupt.938509332
Short name	T179
Test name
Test status
Simulation time	493670837683 ps
CPU time	134.17 seconds
Started	Jan 03 01:14:57 PM PST 24
Finished	Jan 03 01:18:14 PM PST 24
Peak memory	200988 kb
Host	smart-46eafbc9-bce8-4f53-b98d-e4fecd04af72
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=938509332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.938509332
Directory	/workspace/7.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.640623953
Short name	T72
Test name
Test status
Simulation time	625285777 ps
CPU time	0.91 seconds
Started	Jan 03 12:58:43 PM PST 24
Finished	Jan 03 12:59:13 PM PST 24
Peak memory	200540 kb
Host	smart-5f1cdc7f-e2ff-498b-95f9-e25bbbc8846b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640623953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.640623953
Directory	/workspace/0.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/default/31.adc_ctrl_filters_interrupt.1619384269
Short name	T104
Test name
Test status
Simulation time	159740571202 ps
CPU time	140.88 seconds
Started	Jan 03 01:17:16 PM PST 24
Finished	Jan 03 01:19:41 PM PST 24
Peak memory	200832 kb
Host	smart-76a671ac-5e6c-470b-87d5-257eaf76b972
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1619384269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.1619384269
Directory	/workspace/31.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/33.adc_ctrl_filters_both.4046617531
Short name	T243
Test name
Test status
Simulation time	496837798668 ps
CPU time	1122.82 seconds
Started	Jan 03 01:17:40 PM PST 24
Finished	Jan 03 01:36:26 PM PST 24
Peak memory	200976 kb
Host	smart-269c47f7-c511-4038-a37e-2c041123b4a4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4046617531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.4046617531
Directory	/workspace/33.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/48.adc_ctrl_filters_interrupt.2190464398
Short name	T291
Test name
Test status
Simulation time	163937568412 ps
CPU time	49.39 seconds
Started	Jan 03 01:18:41 PM PST 24
Finished	Jan 03 01:19:49 PM PST 24
Peak memory	200900 kb
Host	smart-6b762f22-7085-431d-a6c8-1690080a7839
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2190464398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.2190464398
Directory	/workspace/48.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.272452839
Short name	T353
Test name
Test status
Simulation time	368548339 ps
CPU time	0.84 seconds
Started	Jan 03 12:58:53 PM PST 24
Finished	Jan 03 12:59:27 PM PST 24
Peak memory	200256 kb
Host	smart-c22d02be-3e8a-4efd-8186-aed4d91d407a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272452839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.272452839
Directory	/workspace/12.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/default/34.adc_ctrl_filters_wakeup.1245582595
Short name	T262
Test name
Test status
Simulation time	520233567748 ps
CPU time	585.93 seconds
Started	Jan 03 01:18:09 PM PST 24
Finished	Jan 03 01:28:21 PM PST 24
Peak memory	200896 kb
Host	smart-e57ced93-a431-411c-8710-7de548a44baa
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245582595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters _wakeup.1245582595
Directory	/workspace/34.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/47.adc_ctrl_filters_interrupt.1374503083
Short name	T13
Test name
Test status
Simulation time	332689500299 ps
CPU time	755.91 seconds
Started	Jan 03 01:18:59 PM PST 24
Finished	Jan 03 01:31:43 PM PST 24
Peak memory	200960 kb
Host	smart-0187cbb9-a378-45f4-94f6-3abe6b501280
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1374503083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.1374503083
Directory	/workspace/47.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.2051301219
Short name	T274
Test name
Test status
Simulation time	81510401692 ps
CPU time	69.21 seconds
Started	Jan 03 01:15:07 PM PST 24
Finished	Jan 03 01:17:20 PM PST 24
Peak memory	209872 kb
Host	smart-76da3c28-062b-4edb-b515-96931fa99101
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051301219 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.2051301219
Directory	/workspace/9.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/11.adc_ctrl_fsm_reset.1284737970
Short name	T134
Test name
Test status
Simulation time	82892563115 ps
CPU time	251.19 seconds
Started	Jan 03 01:15:19 PM PST 24
Finished	Jan 03 01:20:36 PM PST 24
Peak memory	201368 kb
Host	smart-095d9a37-9a03-4e33-ac8b-c3470c78b9a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1284737970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.1284737970
Directory	/workspace/11.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/12.adc_ctrl_filters_wakeup.3927350000
Short name	T259
Test name
Test status
Simulation time	498770896738 ps
CPU time	176.92 seconds
Started	Jan 03 01:15:31 PM PST 24
Finished	Jan 03 01:19:30 PM PST 24
Peak memory	200896 kb
Host	smart-f0456ea5-1c4d-467c-b417-54aed15ab61b
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927350000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters _wakeup.3927350000
Directory	/workspace/12.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.1414363292
Short name	T309
Test name
Test status
Simulation time	40145667712 ps
CPU time	19.23 seconds
Started	Jan 03 01:15:47 PM PST 24
Finished	Jan 03 01:17:04 PM PST 24
Peak memory	209204 kb
Host	smart-421e2e0f-afe3-4f8e-b96b-e39be82fd893
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414363292 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.1414363292
Directory	/workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/48.adc_ctrl_filters_both.2720622222
Short name	T250
Test name
Test status
Simulation time	332160375073 ps
CPU time	760.24 seconds
Started	Jan 03 01:18:44 PM PST 24
Finished	Jan 03 01:31:41 PM PST 24
Peak memory	200864 kb
Host	smart-cdbbeb86-aed8-4567-b9d2-1414ed4f51a4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2720622222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.2720622222
Directory	/workspace/48.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/1.adc_ctrl_alert_test.971901926
Short name	T45
Test name
Test status
Simulation time	349922806 ps
CPU time	1.45 seconds
Started	Jan 03 01:15:01 PM PST 24
Finished	Jan 03 01:16:06 PM PST 24
Peak memory	200648 kb
Host	smart-83e75d29-e192-4e88-a0d0-31d388d1fed2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971901926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.971901926
Directory	/workspace/1.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3379047429
Short name	T343
Test name
Test status
Simulation time	4606472038 ps
CPU time	11.61 seconds
Started	Jan 03 12:58:49 PM PST 24
Finished	Jan 03 12:59:32 PM PST 24
Peak memory	200876 kb
Host	smart-e2cbf4b3-7889-4ecc-ad7d-545d4b41010b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379047429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in tg_err.3379047429
Directory	/workspace/0.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/11.adc_ctrl_clock_gating.2481613803
Short name	T329
Test name
Test status
Simulation time	327454253848 ps
CPU time	187.29 seconds
Started	Jan 03 01:15:15 PM PST 24
Finished	Jan 03 01:19:29 PM PST 24
Peak memory	200860 kb
Host	smart-1c7ec673-bc72-486a-b47d-76162216ebad
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481613803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat ing.2481613803
Directory	/workspace/11.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/13.adc_ctrl_filters_wakeup.4059448610
Short name	T261
Test name
Test status
Simulation time	494450556043 ps
CPU time	101.65 seconds
Started	Jan 03 01:15:07 PM PST 24
Finished	Jan 03 01:17:53 PM PST 24
Peak memory	200812 kb
Host	smart-eec9af43-7b27-498b-84af-4c7fc883b09a
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059448610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters _wakeup.4059448610
Directory	/workspace/13.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/15.adc_ctrl_filters_interrupt.2768200990
Short name	T229
Test name
Test status
Simulation time	485067442667 ps
CPU time	640.36 seconds
Started	Jan 03 01:15:24 PM PST 24
Finished	Jan 03 01:27:10 PM PST 24
Peak memory	200896 kb
Host	smart-d51b4312-a554-4636-96a7-cfea834ac589
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2768200990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.2768200990
Directory	/workspace/15.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/22.adc_ctrl_filters_both.1904046810
Short name	T275
Test name
Test status
Simulation time	338842809049 ps
CPU time	402.63 seconds
Started	Jan 03 01:15:48 PM PST 24
Finished	Jan 03 01:23:24 PM PST 24
Peak memory	200992 kb
Host	smart-1874219c-dd6f-4815-b6fc-23ffc245df7a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1904046810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.1904046810
Directory	/workspace/22.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/22.adc_ctrl_filters_wakeup.2751718078
Short name	T282
Test name
Test status
Simulation time	495580774088 ps
CPU time	1131.74 seconds
Started	Jan 03 01:15:41 PM PST 24
Finished	Jan 03 01:35:30 PM PST 24
Peak memory	200876 kb
Host	smart-3fe99da1-7738-48a6-a013-576752e3c7d7
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751718078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters _wakeup.2751718078
Directory	/workspace/22.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/23.adc_ctrl_filters_polled.885638802
Short name	T112
Test name
Test status
Simulation time	327270292429 ps
CPU time	79.86 seconds
Started	Jan 03 01:15:41 PM PST 24
Finished	Jan 03 01:17:58 PM PST 24
Peak memory	200804 kb
Host	smart-5c7d7007-f50e-4e19-9c90-3d1212b88258
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=885638802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.885638802
Directory	/workspace/23.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/37.adc_ctrl_filters_interrupt.2713819878
Short name	T97
Test name
Test status
Simulation time	498180788133 ps
CPU time	277.28 seconds
Started	Jan 03 01:17:49 PM PST 24
Finished	Jan 03 01:22:39 PM PST 24
Peak memory	200904 kb
Host	smart-618eb839-f1d5-4c01-85eb-1f27b0a93c30
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2713819878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.2713819878
Directory	/workspace/37.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/8.adc_ctrl_filters_interrupt.1959374747
Short name	T268
Test name
Test status
Simulation time	326665662153 ps
CPU time	210.12 seconds
Started	Jan 03 01:15:13 PM PST 24
Finished	Jan 03 01:19:49 PM PST 24
Peak memory	200836 kb
Host	smart-faff58c8-b702-4735-93d6-8e481b2137c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1959374747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.1959374747
Directory	/workspace/8.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/0.adc_ctrl_fsm_reset.2386810006
Short name	T349
Test name
Test status
Simulation time	94929726701 ps
CPU time	346.56 seconds
Started	Jan 03 01:14:55 PM PST 24
Finished	Jan 03 01:21:42 PM PST 24
Peak memory	201332 kb
Host	smart-332c21c5-8036-4591-a70c-8894a9f0e073
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2386810006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.2386810006
Directory	/workspace/0.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/1.adc_ctrl_filters_interrupt.985337673
Short name	T572
Test name
Test status
Simulation time	493200860775 ps
CPU time	1088.09 seconds
Started	Jan 03 01:14:55 PM PST 24
Finished	Jan 03 01:34:04 PM PST 24
Peak memory	200848 kb
Host	smart-f4629b86-3725-416a-bee0-73610fe08171
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=985337673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.985337673
Directory	/workspace/1.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/11.adc_ctrl_stress_all.2315118315
Short name	T94
Test name
Test status
Simulation time	371487702117 ps
CPU time	406.33 seconds
Started	Jan 03 01:15:21 PM PST 24
Finished	Jan 03 01:23:15 PM PST 24
Peak memory	200932 kb
Host	smart-28732cef-c6b2-4718-ab5a-b2f3a40b70d7
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315118315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all .2315118315
Directory	/workspace/11.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/12.adc_ctrl_stress_all.1909252272
Short name	T264
Test name
Test status
Simulation time	356971919223 ps
CPU time	126.52 seconds
Started	Jan 03 01:15:25 PM PST 24
Finished	Jan 03 01:18:37 PM PST 24
Peak memory	200880 kb
Host	smart-1aacf86b-25f2-4601-b944-af5d8f68f949
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909252272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all .1909252272
Directory	/workspace/12.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/13.adc_ctrl_filters_both.1883587020
Short name	T245
Test name
Test status
Simulation time	498857451801 ps
CPU time	324.61 seconds
Started	Jan 03 01:15:09 PM PST 24
Finished	Jan 03 01:21:39 PM PST 24
Peak memory	200900 kb
Host	smart-431ce71f-68e7-4ee7-8815-5379ca9ca93f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1883587020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.1883587020
Directory	/workspace/13.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/13.adc_ctrl_fsm_reset.2919239230
Short name	T582
Test name
Test status
Simulation time	134667799431 ps
CPU time	745.42 seconds
Started	Jan 03 01:15:09 PM PST 24
Finished	Jan 03 01:28:40 PM PST 24
Peak memory	201128 kb
Host	smart-feadd02d-ba78-494a-9263-b0994f73daf1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2919239230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.2919239230
Directory	/workspace/13.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/3.adc_ctrl_fsm_reset.2945805439
Short name	T199
Test name
Test status
Simulation time	132700054509 ps
CPU time	571.16 seconds
Started	Jan 03 01:14:43 PM PST 24
Finished	Jan 03 01:25:08 PM PST 24
Peak memory	201328 kb
Host	smart-880ab2f0-f004-4311-8657-ff58941d1263
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2945805439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.2945805439
Directory	/workspace/3.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.2512847950
Short name	T238
Test name
Test status
Simulation time	120903053153 ps
CPU time	76.06 seconds
Started	Jan 03 01:17:34 PM PST 24
Finished	Jan 03 01:18:55 PM PST 24
Peak memory	209196 kb
Host	smart-8ed09ed2-b3f1-4904-9cde-e2499cc9e968
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512847950 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.2512847950
Directory	/workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/38.adc_ctrl_filters_polled.2789030718
Short name	T306
Test name
Test status
Simulation time	332404196165 ps
CPU time	369.92 seconds
Started	Jan 03 01:17:31 PM PST 24
Finished	Jan 03 01:23:45 PM PST 24
Peak memory	200912 kb
Host	smart-30a630de-6419-449a-a12b-7dcde26d2a11
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2789030718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.2789030718
Directory	/workspace/38.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.887154812
Short name	T31
Test name
Test status
Simulation time	561438387 ps
CPU time	0.92 seconds
Started	Jan 03 12:58:48 PM PST 24
Finished	Jan 03 12:59:20 PM PST 24
Peak memory	200244 kb
Host	smart-e74641e8-12a0-4883-9c68-c73347edeffd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887154812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.887154812
Directory	/workspace/1.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/default/10.adc_ctrl_fsm_reset.2147776422
Short name	T195
Test name
Test status
Simulation time	84843897943 ps
CPU time	359.24 seconds
Started	Jan 03 01:14:55 PM PST 24
Finished	Jan 03 01:21:55 PM PST 24
Peak memory	201396 kb
Host	smart-eebf0b60-a0ac-4c16-9722-8829bc4ca072
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2147776422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.2147776422
Directory	/workspace/10.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/13.adc_ctrl_stress_all.1202824935
Short name	T190
Test name
Test status
Simulation time	311041262246 ps
CPU time	351.49 seconds
Started	Jan 03 01:15:06 PM PST 24
Finished	Jan 03 01:22:01 PM PST 24
Peak memory	217684 kb
Host	smart-fffbec76-d508-4909-96a3-92e15dde4f28
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202824935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all .1202824935
Directory	/workspace/13.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/15.adc_ctrl_filters_both.3159496951
Short name	T302
Test name
Test status
Simulation time	493088094153 ps
CPU time	1127.1 seconds
Started	Jan 03 01:15:18 PM PST 24
Finished	Jan 03 01:35:12 PM PST 24
Peak memory	200876 kb
Host	smart-0cb15db7-bb02-4fe4-818a-bc4d258fade8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3159496951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.3159496951
Directory	/workspace/15.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/16.adc_ctrl_fsm_reset.697636020
Short name	T196
Test name
Test status
Simulation time	68800118383 ps
CPU time	232.25 seconds
Started	Jan 03 01:15:29 PM PST 24
Finished	Jan 03 01:20:24 PM PST 24
Peak memory	201444 kb
Host	smart-e17efdef-a266-492a-b46b-ce57f57ddd7a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=697636020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.697636020
Directory	/workspace/16.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/22.adc_ctrl_stress_all.3611228658
Short name	T323
Test name
Test status
Simulation time	670524071433 ps
CPU time	395.45 seconds
Started	Jan 03 01:15:48 PM PST 24
Finished	Jan 03 01:23:17 PM PST 24
Peak memory	200916 kb
Host	smart-396af9ac-e1bb-40cd-bf9b-93f4a3b0d9f3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611228658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all .3611228658
Directory	/workspace/22.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/23.adc_ctrl_stress_all.983662987
Short name	T287
Test name
Test status
Simulation time	164682117262 ps
CPU time	152.43 seconds
Started	Jan 03 01:15:40 PM PST 24
Finished	Jan 03 01:19:10 PM PST 24
Peak memory	200932 kb
Host	smart-0bf94a44-b2fa-4428-9be2-6eb62e5cef92
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983662987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all. 983662987
Directory	/workspace/23.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/36.adc_ctrl_filters_interrupt.1976534412
Short name	T201
Test name
Test status
Simulation time	327094471565 ps
CPU time	704.78 seconds
Started	Jan 03 01:17:33 PM PST 24
Finished	Jan 03 01:29:22 PM PST 24
Peak memory	200936 kb
Host	smart-6bca3a41-afc8-4bee-a6d1-760bc83814fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1976534412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.1976534412
Directory	/workspace/36.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.106078679
Short name	T252
Test name
Test status
Simulation time	166755613181 ps
CPU time	330.71 seconds
Started	Jan 03 01:17:34 PM PST 24
Finished	Jan 03 01:23:13 PM PST 24
Peak memory	209504 kb
Host	smart-26d612b5-9f8e-4107-bb03-474456cf04c0
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106078679 -assert nopo stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.106078679
Directory	/workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/46.adc_ctrl_filters_wakeup.1937321339
Short name	T143
Test name
Test status
Simulation time	333573407890 ps
CPU time	87.26 seconds
Started	Jan 03 01:19:01 PM PST 24
Finished	Jan 03 01:20:36 PM PST 24
Peak memory	200872 kb
Host	smart-1003a446-7438-4692-adf2-27aa7a573a15
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937321339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters _wakeup.1937321339
Directory	/workspace/46.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2508031789
Short name	T400
Test name
Test status
Simulation time	729980409 ps
CPU time	1.77 seconds
Started	Jan 03 12:59:07 PM PST 24
Finished	Jan 03 12:59:56 PM PST 24
Peak memory	200704 kb
Host	smart-b46100d2-27b3-455e-8a6c-1b2ff333e84e
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508031789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia sing.2508031789
Directory	/workspace/0.adc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.1868845094
Short name	T853
Test name
Test status
Simulation time	1010584715 ps
CPU time	0.87 seconds
Started	Jan 03 12:58:43 PM PST 24
Finished	Jan 03 12:59:14 PM PST 24
Peak memory	200600 kb
Host	smart-6a6e71d4-147a-4eb7-a44a-9bc2f60a3c4e
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868845094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r eset.1868845094
Directory	/workspace/0.adc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.768346968
Short name	T395
Test name
Test status
Simulation time	724852764 ps
CPU time	1.07 seconds
Started	Jan 03 12:58:49 PM PST 24
Finished	Jan 03 12:59:22 PM PST 24
Peak memory	200668 kb
Host	smart-51c2225f-7a42-44b5-9e94-5201e12a470d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768346968 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.768346968
Directory	/workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1846642918
Short name	T362
Test name
Test status
Simulation time	519990333 ps
CPU time	0.9 seconds
Started	Jan 03 12:58:44 PM PST 24
Finished	Jan 03 12:59:15 PM PST 24
Peak memory	200300 kb
Host	smart-d4f2bed3-aef2-4bbe-8f5c-63c927b78e21
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846642918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.1846642918
Directory	/workspace/0.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.4195084157
Short name	T880
Test name
Test status
Simulation time	4218521497 ps
CPU time	13.29 seconds
Started	Jan 03 12:58:50 PM PST 24
Finished	Jan 03 12:59:35 PM PST 24
Peak memory	200824 kb
Host	smart-64ef7e4d-c84f-4f96-a404-b639845c0ad2
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195084157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c trl_same_csr_outstanding.4195084157
Directory	/workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1809141440
Short name	T63
Test name
Test status
Simulation time	423152117 ps
CPU time	2.21 seconds
Started	Jan 03 12:58:46 PM PST 24
Finished	Jan 03 12:59:19 PM PST 24
Peak memory	200808 kb
Host	smart-f088f022-0c85-4be5-b25a-7457f0250241
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809141440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.1809141440
Directory	/workspace/0.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.239336902
Short name	T74
Test name
Test status
Simulation time	560300906 ps
CPU time	1.66 seconds
Started	Jan 03 12:58:59 PM PST 24
Finished	Jan 03 12:59:40 PM PST 24
Peak memory	200684 kb
Host	smart-e506aa4d-a7be-4442-82ce-38cf9f9919ab
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239336902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alias ing.239336902
Directory	/workspace/1.adc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2561810401
Short name	T73
Test name
Test status
Simulation time	25962955529 ps
CPU time	57.11 seconds
Started	Jan 03 12:59:06 PM PST 24
Finished	Jan 03 01:00:49 PM PST 24
Peak memory	200820 kb
Host	smart-f150e283-cb5c-4e46-a8b4-7b745ac934c3
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561810401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_ bash.2561810401
Directory	/workspace/1.adc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.21714215
Short name	T855
Test name
Test status
Simulation time	1039344943 ps
CPU time	3.3 seconds
Started	Jan 03 12:59:03 PM PST 24
Finished	Jan 03 12:59:49 PM PST 24
Peak memory	200604 kb
Host	smart-d639abd0-21e1-46e5-9592-8008f113a1ec
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21714215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_res et.21714215
Directory	/workspace/1.adc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2876352223
Short name	T374
Test name
Test status
Simulation time	549162316 ps
CPU time	1.94 seconds
Started	Jan 03 12:59:02 PM PST 24
Finished	Jan 03 12:59:46 PM PST 24
Peak memory	200676 kb
Host	smart-6cbeaa6e-a218-48f1-b429-f010bf6ec504
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876352223 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.2876352223
Directory	/workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1739916424
Short name	T75
Test name
Test status
Simulation time	404238473 ps
CPU time	0.95 seconds
Started	Jan 03 12:58:58 PM PST 24
Finished	Jan 03 12:59:39 PM PST 24
Peak memory	200548 kb
Host	smart-fc6c69e4-68db-4f6c-9aa9-99f788e79939
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739916424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.1739916424
Directory	/workspace/1.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.726308715
Short name	T366
Test name
Test status
Simulation time	4837958927 ps
CPU time	13.51 seconds
Started	Jan 03 12:59:05 PM PST 24
Finished	Jan 03 01:00:03 PM PST 24
Peak memory	200892 kb
Host	smart-a4214190-d247-433c-afd0-8d988d84ef94
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726308715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ct rl_same_csr_outstanding.726308715
Directory	/workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.21193395
Short name	T879
Test name
Test status
Simulation time	498627668 ps
CPU time	2.44 seconds
Started	Jan 03 12:58:55 PM PST 24
Finished	Jan 03 12:59:34 PM PST 24
Peak memory	200876 kb
Host	smart-6bcde1be-9d1f-47c3-b79a-fb4bf17c1349
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21193395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.21193395
Directory	/workspace/1.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.527736842
Short name	T35
Test name
Test status
Simulation time	462559501 ps
CPU time	1.33 seconds
Started	Jan 03 12:58:51 PM PST 24
Finished	Jan 03 12:59:24 PM PST 24
Peak memory	200604 kb
Host	smart-c8ca7bcd-a8b3-45ab-b40a-0b2777feba83
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527736842 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.527736842
Directory	/workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3778516459
Short name	T901
Test name
Test status
Simulation time	421268249 ps
CPU time	0.78 seconds
Started	Jan 03 12:58:46 PM PST 24
Finished	Jan 03 12:59:18 PM PST 24
Peak memory	200548 kb
Host	smart-6c79a054-f3e2-4842-9204-8a31c4c610d5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778516459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.3778516459
Directory	/workspace/10.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1635818208
Short name	T894
Test name
Test status
Simulation time	342816352 ps
CPU time	0.84 seconds
Started	Jan 03 12:58:41 PM PST 24
Finished	Jan 03 12:59:12 PM PST 24
Peak memory	200520 kb
Host	smart-d17ef3a3-f44b-4f9a-8932-0cb70fe2e461
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635818208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.1635818208
Directory	/workspace/10.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3489159459
Short name	T869
Test name
Test status
Simulation time	5080351570 ps
CPU time	12.57 seconds
Started	Jan 03 12:58:52 PM PST 24
Finished	Jan 03 12:59:36 PM PST 24
Peak memory	200872 kb
Host	smart-d839686a-8996-47d1-9a77-5f8539d3f6a4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489159459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ ctrl_same_csr_outstanding.3489159459
Directory	/workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2970037352
Short name	T66
Test name
Test status
Simulation time	419446203 ps
CPU time	2.14 seconds
Started	Jan 03 12:58:49 PM PST 24
Finished	Jan 03 12:59:23 PM PST 24
Peak memory	200912 kb
Host	smart-8e4404f2-5b7e-44ac-89b9-b2d876a2a6f3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970037352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.2970037352
Directory	/workspace/10.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1607729310
Short name	T10
Test name
Test status
Simulation time	4435297423 ps
CPU time	4.01 seconds
Started	Jan 03 12:58:54 PM PST 24
Finished	Jan 03 12:59:33 PM PST 24
Peak memory	200768 kb
Host	smart-4a58eed5-02d3-4cd5-abd2-e3b7befd5395
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607729310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i ntg_err.1607729310
Directory	/workspace/10.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.4073073328
Short name	T9
Test name
Test status
Simulation time	514591680 ps
CPU time	1.54 seconds
Started	Jan 03 12:59:00 PM PST 24
Finished	Jan 03 12:59:43 PM PST 24
Peak memory	200656 kb
Host	smart-9039da3a-45f0-4989-9787-d157abc7b11a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073073328 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.4073073328
Directory	/workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.6900330
Short name	T89
Test name
Test status
Simulation time	433543374 ps
CPU time	1.02 seconds
Started	Jan 03 12:59:06 PM PST 24
Finished	Jan 03 12:59:51 PM PST 24
Peak memory	200612 kb
Host	smart-659d5004-f3cf-4b4f-9077-a4fb235c7bc6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6900330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.6900330
Directory	/workspace/11.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3008430520
Short name	T82
Test name
Test status
Simulation time	302612716 ps
CPU time	1.28 seconds
Started	Jan 03 12:58:47 PM PST 24
Finished	Jan 03 12:59:19 PM PST 24
Peak memory	200532 kb
Host	smart-ce0284c8-99ee-4747-b66c-6da83bf59715
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008430520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.3008430520
Directory	/workspace/11.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3399682575
Short name	T873
Test name
Test status
Simulation time	2598973746 ps
CPU time	10.03 seconds
Started	Jan 03 12:58:47 PM PST 24
Finished	Jan 03 12:59:27 PM PST 24
Peak memory	200640 kb
Host	smart-06d80628-076c-48f2-a59b-be43dfb4e1ad
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399682575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ ctrl_same_csr_outstanding.3399682575
Directory	/workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2193911417
Short name	T390
Test name
Test status
Simulation time	369217736 ps
CPU time	1.72 seconds
Started	Jan 03 12:58:55 PM PST 24
Finished	Jan 03 12:59:32 PM PST 24
Peak memory	200880 kb
Host	smart-cb93d618-48e0-4591-8b2d-3b9f965e1bf0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193911417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.2193911417
Directory	/workspace/11.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2447405406
Short name	T886
Test name
Test status
Simulation time	8508801554 ps
CPU time	16.19 seconds
Started	Jan 03 12:58:48 PM PST 24
Finished	Jan 03 12:59:35 PM PST 24
Peak memory	200832 kb
Host	smart-2afa15ec-9fca-4621-b6d9-c1b8a85e1e19
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447405406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i ntg_err.2447405406
Directory	/workspace/11.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.3507214377
Short name	T39
Test name
Test status
Simulation time	537794012 ps
CPU time	1.74 seconds
Started	Jan 03 12:58:46 PM PST 24
Finished	Jan 03 12:59:17 PM PST 24
Peak memory	200640 kb
Host	smart-edc87fa2-980d-4577-b42c-a24df14e3bb5
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507214377 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.3507214377
Directory	/workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.2576779446
Short name	T871
Test name
Test status
Simulation time	514160898 ps
CPU time	1.51 seconds
Started	Jan 03 12:58:50 PM PST 24
Finished	Jan 03 12:59:23 PM PST 24
Peak memory	200536 kb
Host	smart-b58a4ef9-ae62-4e6c-ae01-746b4c7fa78f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576779446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.2576779446
Directory	/workspace/12.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2615155037
Short name	T377
Test name
Test status
Simulation time	2204627834 ps
CPU time	2.39 seconds
Started	Jan 03 12:58:48 PM PST 24
Finished	Jan 03 12:59:21 PM PST 24
Peak memory	200684 kb
Host	smart-152a774e-afce-4a07-9b03-849faa1fee46
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615155037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ ctrl_same_csr_outstanding.2615155037
Directory	/workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.4100056183
Short name	T370
Test name
Test status
Simulation time	483276788 ps
CPU time	1.81 seconds
Started	Jan 03 12:58:55 PM PST 24
Finished	Jan 03 12:59:34 PM PST 24
Peak memory	200864 kb
Host	smart-60b21aac-9a2a-4b45-b9aa-c8ce08f82c9e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100056183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.4100056183
Directory	/workspace/12.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3675184435
Short name	T854
Test name
Test status
Simulation time	4570866960 ps
CPU time	4.3 seconds
Started	Jan 03 12:58:49 PM PST 24
Finished	Jan 03 12:59:25 PM PST 24
Peak memory	200816 kb
Host	smart-3bcc67d8-576e-40a5-a7c6-7450d1821d04
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675184435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i ntg_err.3675184435
Directory	/workspace/12.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.4068601051
Short name	T382
Test name
Test status
Simulation time	605774361 ps
CPU time	0.87 seconds
Started	Jan 03 12:58:48 PM PST 24
Finished	Jan 03 12:59:26 PM PST 24
Peak memory	200592 kb
Host	smart-b9daf046-d82c-437a-90fe-32c35805629a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068601051 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.4068601051
Directory	/workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.291403244
Short name	T398
Test name
Test status
Simulation time	363879484 ps
CPU time	0.92 seconds
Started	Jan 03 12:58:47 PM PST 24
Finished	Jan 03 12:59:18 PM PST 24
Peak memory	200548 kb
Host	smart-0ebddcc0-8d75-42e9-ad7c-bb1b5c0490e6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291403244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.291403244
Directory	/workspace/13.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1721774996
Short name	T81
Test name
Test status
Simulation time	334939154 ps
CPU time	1.19 seconds
Started	Jan 03 12:58:41 PM PST 24
Finished	Jan 03 12:59:12 PM PST 24
Peak memory	200268 kb
Host	smart-041e473c-820e-46f6-b6d8-febaddb27df9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721774996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.1721774996
Directory	/workspace/13.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.714559855
Short name	T372
Test name
Test status
Simulation time	4655412001 ps
CPU time	15.38 seconds
Started	Jan 03 12:58:49 PM PST 24
Finished	Jan 03 12:59:35 PM PST 24
Peak memory	200808 kb
Host	smart-61ff651c-cbb3-4f5f-a1d3-d2f37d5fab99
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714559855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_c trl_same_csr_outstanding.714559855
Directory	/workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3013788134
Short name	T385
Test name
Test status
Simulation time	627474156 ps
CPU time	2.96 seconds
Started	Jan 03 12:58:49 PM PST 24
Finished	Jan 03 12:59:24 PM PST 24
Peak memory	200872 kb
Host	smart-b3207d49-6124-4558-bef7-e96c7d818a6b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013788134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.3013788134
Directory	/workspace/13.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1113639627
Short name	T401
Test name
Test status
Simulation time	8894728449 ps
CPU time	7.53 seconds
Started	Jan 03 12:58:46 PM PST 24
Finished	Jan 03 12:59:23 PM PST 24
Peak memory	200860 kb
Host	smart-1ed63056-0f81-48c5-806a-22885242cc52
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113639627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i ntg_err.1113639627
Directory	/workspace/13.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.4255598741
Short name	T368
Test name
Test status
Simulation time	488097295 ps
CPU time	1.43 seconds
Started	Jan 03 12:58:49 PM PST 24
Finished	Jan 03 12:59:21 PM PST 24
Peak memory	200592 kb
Host	smart-a553d9b2-b4ca-4681-8c4a-e9e5edb38ce7
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255598741 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.4255598741
Directory	/workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2315292402
Short name	T71
Test name
Test status
Simulation time	523708796 ps
CPU time	0.85 seconds
Started	Jan 03 12:58:48 PM PST 24
Finished	Jan 03 12:59:20 PM PST 24
Peak memory	200612 kb
Host	smart-5116c54f-7d2a-4923-a585-a4c38292754f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315292402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.2315292402
Directory	/workspace/14.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.457661811
Short name	T897
Test name
Test status
Simulation time	341698124 ps
CPU time	1.37 seconds
Started	Jan 03 12:58:58 PM PST 24
Finished	Jan 03 12:59:40 PM PST 24
Peak memory	200232 kb
Host	smart-f520be7b-918c-48e2-b741-0cda94eb71fa
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457661811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.457661811
Directory	/workspace/14.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1888122710
Short name	T905
Test name
Test status
Simulation time	2892560358 ps
CPU time	4.62 seconds
Started	Jan 03 12:58:48 PM PST 24
Finished	Jan 03 12:59:24 PM PST 24
Peak memory	200676 kb
Host	smart-133ed939-b866-4d70-94de-180caa49f046
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888122710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ ctrl_same_csr_outstanding.1888122710
Directory	/workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.677122646
Short name	T870
Test name
Test status
Simulation time	651616246 ps
CPU time	3.34 seconds
Started	Jan 03 12:59:03 PM PST 24
Finished	Jan 03 12:59:50 PM PST 24
Peak memory	210120 kb
Host	smart-bb024114-7c5d-4293-abab-ee1c76a5ac19
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677122646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.677122646
Directory	/workspace/14.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3162975631
Short name	T885
Test name
Test status
Simulation time	3993081629 ps
CPU time	11.24 seconds
Started	Jan 03 12:58:43 PM PST 24
Finished	Jan 03 12:59:24 PM PST 24
Peak memory	200864 kb
Host	smart-1550f8a8-e284-4901-ad26-8883719c9e8f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162975631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i ntg_err.3162975631
Directory	/workspace/14.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1661360746
Short name	T892
Test name
Test status
Simulation time	607308403 ps
CPU time	1.3 seconds
Started	Jan 03 12:58:56 PM PST 24
Finished	Jan 03 12:59:35 PM PST 24
Peak memory	200644 kb
Host	smart-2dae1ada-7b8d-4829-8709-fa0fa507110c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661360746 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.1661360746
Directory	/workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.671946090
Short name	T7
Test name
Test status
Simulation time	573967246 ps
CPU time	2.03 seconds
Started	Jan 03 12:58:47 PM PST 24
Finished	Jan 03 12:59:20 PM PST 24
Peak memory	200548 kb
Host	smart-e191cd34-f5b9-45b4-8013-cb70d33795a9
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671946090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.671946090
Directory	/workspace/15.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1709555058
Short name	T78
Test name
Test status
Simulation time	556043364 ps
CPU time	0.89 seconds
Started	Jan 03 12:58:51 PM PST 24
Finished	Jan 03 12:59:24 PM PST 24
Peak memory	200300 kb
Host	smart-0cf1f1ed-531a-4e0d-9a59-9d5ffd2befad
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709555058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.1709555058
Directory	/workspace/15.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2308351110
Short name	T383
Test name
Test status
Simulation time	5166655065 ps
CPU time	10.64 seconds
Started	Jan 03 12:58:57 PM PST 24
Finished	Jan 03 12:59:46 PM PST 24
Peak memory	200816 kb
Host	smart-63a2b381-b9a7-40d4-8508-086caeaa24d5
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308351110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ ctrl_same_csr_outstanding.2308351110
Directory	/workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.274318738
Short name	T887
Test name
Test status
Simulation time	496172434 ps
CPU time	2.8 seconds
Started	Jan 03 12:59:01 PM PST 24
Finished	Jan 03 12:59:45 PM PST 24
Peak memory	200868 kb
Host	smart-357fa29e-b53f-4c03-b720-bbba09e77a3c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274318738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.274318738
Directory	/workspace/15.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3871282056
Short name	T62
Test name
Test status
Simulation time	8635491851 ps
CPU time	22.59 seconds
Started	Jan 03 12:58:57 PM PST 24
Finished	Jan 03 12:59:58 PM PST 24
Peak memory	200840 kb
Host	smart-4a84f124-1048-4fbe-b70d-82e5e2f125b4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871282056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i ntg_err.3871282056
Directory	/workspace/15.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2952349159
Short name	T378
Test name
Test status
Simulation time	616485298 ps
CPU time	1.49 seconds
Started	Jan 03 12:58:46 PM PST 24
Finished	Jan 03 12:59:17 PM PST 24
Peak memory	209032 kb
Host	smart-2ccb9c24-d186-4b1d-b190-31c15c615969
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952349159 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.2952349159
Directory	/workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.1904000247
Short name	T893
Test name
Test status
Simulation time	355594571 ps
CPU time	1.12 seconds
Started	Jan 03 12:58:49 PM PST 24
Finished	Jan 03 12:59:22 PM PST 24
Peak memory	200536 kb
Host	smart-ff0a6875-536f-44d4-a9f5-93fa62dc6d4c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904000247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.1904000247
Directory	/workspace/16.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.487124307
Short name	T27
Test name
Test status
Simulation time	512832140 ps
CPU time	1.88 seconds
Started	Jan 03 12:58:49 PM PST 24
Finished	Jan 03 12:59:23 PM PST 24
Peak memory	200440 kb
Host	smart-e2664135-1f5d-4f6b-9668-4540df6f8c06
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487124307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.487124307
Directory	/workspace/16.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1607364540
Short name	T375
Test name
Test status
Simulation time	4106233544 ps
CPU time	11.83 seconds
Started	Jan 03 12:58:45 PM PST 24
Finished	Jan 03 12:59:27 PM PST 24
Peak memory	200784 kb
Host	smart-d9b00bbe-522a-4e00-afb1-3725680669fa
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607364540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ ctrl_same_csr_outstanding.1607364540
Directory	/workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2271309540
Short name	T65
Test name
Test status
Simulation time	1473451054 ps
CPU time	2.07 seconds
Started	Jan 03 12:58:44 PM PST 24
Finished	Jan 03 12:59:16 PM PST 24
Peak memory	200888 kb
Host	smart-68fb0697-282c-42c1-8ac6-1d119c76b049
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271309540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.2271309540
Directory	/workspace/16.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.711937557
Short name	T895
Test name
Test status
Simulation time	4186678036 ps
CPU time	10.75 seconds
Started	Jan 03 12:58:43 PM PST 24
Finished	Jan 03 12:59:23 PM PST 24
Peak memory	200876 kb
Host	smart-fa56ec7e-daea-4969-8e85-a1309a689a90
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711937557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_in tg_err.711937557
Directory	/workspace/16.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.843020235
Short name	T371
Test name
Test status
Simulation time	476827492 ps
CPU time	1.68 seconds
Started	Jan 03 12:58:52 PM PST 24
Finished	Jan 03 12:59:26 PM PST 24
Peak memory	200656 kb
Host	smart-bdb3e9c8-d2c3-424c-880e-c2aa0ed634b0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843020235 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.843020235
Directory	/workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.460169660
Short name	T29
Test name
Test status
Simulation time	479522331 ps
CPU time	0.97 seconds
Started	Jan 03 12:58:48 PM PST 24
Finished	Jan 03 12:59:20 PM PST 24
Peak memory	200532 kb
Host	smart-1e72d132-d063-418d-9fbe-423e1783668a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460169660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.460169660
Directory	/workspace/17.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3328413005
Short name	T77
Test name
Test status
Simulation time	612737355 ps
CPU time	0.71 seconds
Started	Jan 03 12:58:47 PM PST 24
Finished	Jan 03 12:59:19 PM PST 24
Peak memory	200260 kb
Host	smart-0213da97-710d-4ba9-8366-c603ed762049
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328413005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.3328413005
Directory	/workspace/17.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1540948557
Short name	T182
Test name
Test status
Simulation time	4052398461 ps
CPU time	8.51 seconds
Started	Jan 03 12:58:50 PM PST 24
Finished	Jan 03 12:59:30 PM PST 24
Peak memory	200720 kb
Host	smart-fe96983d-7cae-4a83-9eec-6618855e6109
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540948557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ ctrl_same_csr_outstanding.1540948557
Directory	/workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1543059903
Short name	T392
Test name
Test status
Simulation time	494074043 ps
CPU time	2.94 seconds
Started	Jan 03 12:58:50 PM PST 24
Finished	Jan 03 12:59:25 PM PST 24
Peak memory	209048 kb
Host	smart-9e466021-36a2-416f-ab02-8a86765dc534
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543059903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.1543059903
Directory	/workspace/17.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1248913487
Short name	T896
Test name
Test status
Simulation time	4520067358 ps
CPU time	5.78 seconds
Started	Jan 03 12:58:52 PM PST 24
Finished	Jan 03 12:59:31 PM PST 24
Peak memory	200836 kb
Host	smart-c097ce52-29ea-4a5d-9f5b-a211f44ad662
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248913487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i ntg_err.1248913487
Directory	/workspace/17.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.77045386
Short name	T181
Test name
Test status
Simulation time	371207509 ps
CPU time	1.56 seconds
Started	Jan 03 12:59:00 PM PST 24
Finished	Jan 03 12:59:42 PM PST 24
Peak memory	200656 kb
Host	smart-74dec095-582b-4d81-be40-f45dea31ed6c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77045386 -assert nopostproc +UVM_TESTNAME=a dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.77045386
Directory	/workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2131406854
Short name	T888
Test name
Test status
Simulation time	495663463 ps
CPU time	1.81 seconds
Started	Jan 03 12:58:49 PM PST 24
Finished	Jan 03 12:59:23 PM PST 24
Peak memory	200572 kb
Host	smart-eec1aef5-3a8c-4864-939e-3959c1233b7c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131406854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.2131406854
Directory	/workspace/18.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.743096423
Short name	T352
Test name
Test status
Simulation time	501876653 ps
CPU time	0.93 seconds
Started	Jan 03 12:58:46 PM PST 24
Finished	Jan 03 12:59:17 PM PST 24
Peak memory	200300 kb
Host	smart-c0ea86e2-1189-4bfd-bf2a-ccd5e28e9df1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743096423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.743096423
Directory	/workspace/18.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2799937800
Short name	T889
Test name
Test status
Simulation time	2207661015 ps
CPU time	7.01 seconds
Started	Jan 03 12:58:46 PM PST 24
Finished	Jan 03 12:59:23 PM PST 24
Peak memory	200584 kb
Host	smart-5f7d1894-aa58-450c-a5c3-b4ad0e77742a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799937800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ ctrl_same_csr_outstanding.2799937800
Directory	/workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.594816934
Short name	T900
Test name
Test status
Simulation time	474103702 ps
CPU time	1.65 seconds
Started	Jan 03 12:58:46 PM PST 24
Finished	Jan 03 12:59:18 PM PST 24
Peak memory	200808 kb
Host	smart-b6dc44b9-c27b-48e3-960f-129e053c4d13
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594816934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.594816934
Directory	/workspace/18.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.560265319
Short name	T874
Test name
Test status
Simulation time	8311447729 ps
CPU time	21.41 seconds
Started	Jan 03 12:58:47 PM PST 24
Finished	Jan 03 12:59:39 PM PST 24
Peak memory	200836 kb
Host	smart-9d408127-c8b4-4529-aa07-eec76aa3a64f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560265319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_in tg_err.560265319
Directory	/workspace/18.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3350817247
Short name	T357
Test name
Test status
Simulation time	353550236 ps
CPU time	1.13 seconds
Started	Jan 03 12:59:04 PM PST 24
Finished	Jan 03 12:59:49 PM PST 24
Peak memory	200648 kb
Host	smart-3c44e25e-a8df-460f-8e87-98d591cde2e7
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350817247 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.3350817247
Directory	/workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3848724307
Short name	T882
Test name
Test status
Simulation time	315297689 ps
CPU time	1.39 seconds
Started	Jan 03 12:59:21 PM PST 24
Finished	Jan 03 01:00:16 PM PST 24
Peak memory	200564 kb
Host	smart-b2e11f2a-1169-45bc-9bc0-1485574acac1
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848724307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.3848724307
Directory	/workspace/19.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.3975018660
Short name	T899
Test name
Test status
Simulation time	406263558 ps
CPU time	1.1 seconds
Started	Jan 03 12:59:01 PM PST 24
Finished	Jan 03 12:59:44 PM PST 24
Peak memory	200248 kb
Host	smart-66214032-b051-4651-b69a-db6746d8fc21
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975018660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.3975018660
Directory	/workspace/19.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2280642067
Short name	T863
Test name
Test status
Simulation time	2669865614 ps
CPU time	10.33 seconds
Started	Jan 03 12:59:08 PM PST 24
Finished	Jan 03 01:00:08 PM PST 24
Peak memory	200672 kb
Host	smart-2462c839-15af-47bb-bfd7-2fd956051bb7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280642067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ ctrl_same_csr_outstanding.2280642067
Directory	/workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3542407984
Short name	T862
Test name
Test status
Simulation time	9680277718 ps
CPU time	4.6 seconds
Started	Jan 03 12:58:56 PM PST 24
Finished	Jan 03 12:59:38 PM PST 24
Peak memory	200876 kb
Host	smart-9ffb2fbb-e714-418d-a701-42e996173f85
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542407984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i ntg_err.3542407984
Directory	/workspace/19.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.3155295151
Short name	T4
Test name
Test status
Simulation time	972308191 ps
CPU time	1.78 seconds
Started	Jan 03 12:58:50 PM PST 24
Finished	Jan 03 12:59:23 PM PST 24
Peak memory	200656 kb
Host	smart-f09b4bc3-4bad-4736-944b-2806f2c17831
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155295151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia sing.3155295151
Directory	/workspace/2.adc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2982991282
Short name	T851
Test name
Test status
Simulation time	25635610999 ps
CPU time	38.75 seconds
Started	Jan 03 12:59:11 PM PST 24
Finished	Jan 03 01:00:42 PM PST 24
Peak memory	200712 kb
Host	smart-20b93d48-3927-4add-811c-3d51b7ab57e9
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982991282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_ bash.2982991282
Directory	/workspace/2.adc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3404577185
Short name	T70
Test name
Test status
Simulation time	960177954 ps
CPU time	2.82 seconds
Started	Jan 03 12:59:08 PM PST 24
Finished	Jan 03 01:00:01 PM PST 24
Peak memory	200588 kb
Host	smart-681be1b8-bbb9-462f-acc9-5ea53cd4a95d
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404577185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r eset.3404577185
Directory	/workspace/2.adc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3446277515
Short name	T387
Test name
Test status
Simulation time	517278428 ps
CPU time	1.37 seconds
Started	Jan 03 12:59:03 PM PST 24
Finished	Jan 03 12:59:46 PM PST 24
Peak memory	208864 kb
Host	smart-74eb4677-82a1-48bc-82ff-fe922b12823b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446277515 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.3446277515
Directory	/workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3187120545
Short name	T903
Test name
Test status
Simulation time	488372381 ps
CPU time	1.07 seconds
Started	Jan 03 12:59:00 PM PST 24
Finished	Jan 03 12:59:41 PM PST 24
Peak memory	200524 kb
Host	smart-db73c224-e1f7-4a46-8ab5-6847fa9b20eb
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187120545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.3187120545
Directory	/workspace/2.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2720038714
Short name	T80
Test name
Test status
Simulation time	386070885 ps
CPU time	0.79 seconds
Started	Jan 03 12:58:58 PM PST 24
Finished	Jan 03 12:59:38 PM PST 24
Peak memory	200516 kb
Host	smart-d38b2242-aab8-422c-99d8-7353eeac376a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720038714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.2720038714
Directory	/workspace/2.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2189023988
Short name	T367
Test name
Test status
Simulation time	4174439228 ps
CPU time	4.82 seconds
Started	Jan 03 12:58:51 PM PST 24
Finished	Jan 03 12:59:28 PM PST 24
Peak memory	200896 kb
Host	smart-e3d59505-379e-4d3d-afb7-46d5f1a4095b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189023988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c trl_same_csr_outstanding.2189023988
Directory	/workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2657769717
Short name	T883
Test name
Test status
Simulation time	511256423 ps
CPU time	2.95 seconds
Started	Jan 03 12:58:47 PM PST 24
Finished	Jan 03 12:59:21 PM PST 24
Peak memory	209056 kb
Host	smart-19cce3d3-2a10-4ab3-8a76-f261ff8f527f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657769717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.2657769717
Directory	/workspace/2.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3523199310
Short name	T389
Test name
Test status
Simulation time	4032162001 ps
CPU time	6.02 seconds
Started	Jan 03 12:59:06 PM PST 24
Finished	Jan 03 12:59:56 PM PST 24
Peak memory	200756 kb
Host	smart-d87da4da-8e2d-40d1-85c9-43294ff72b06
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523199310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in tg_err.3523199310
Directory	/workspace/2.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.3351386623
Short name	T902
Test name
Test status
Simulation time	317452996 ps
CPU time	0.79 seconds
Started	Jan 03 12:59:03 PM PST 24
Finished	Jan 03 12:59:47 PM PST 24
Peak memory	200396 kb
Host	smart-09a84607-a5ae-4385-8e08-286ba44eacee
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351386623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.3351386623
Directory	/workspace/20.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.2261651898
Short name	T380
Test name
Test status
Simulation time	522263017 ps
CPU time	0.92 seconds
Started	Jan 03 12:59:03 PM PST 24
Finished	Jan 03 12:59:46 PM PST 24
Peak memory	200192 kb
Host	smart-6011a84f-8cf2-48f3-bfc0-7efc3e74c734
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261651898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.2261651898
Directory	/workspace/21.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.447373495
Short name	T399
Test name
Test status
Simulation time	525954353 ps
CPU time	1.15 seconds
Started	Jan 03 12:59:07 PM PST 24
Finished	Jan 03 12:59:54 PM PST 24
Peak memory	200400 kb
Host	smart-b67ff325-79e4-4818-88e5-0972d553520a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447373495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.447373495
Directory	/workspace/22.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3632275927
Short name	T379
Test name
Test status
Simulation time	317950501 ps
CPU time	1.32 seconds
Started	Jan 03 12:59:14 PM PST 24
Finished	Jan 03 01:00:10 PM PST 24
Peak memory	200536 kb
Host	smart-a6d03d42-d3d9-48db-8e3a-f2aa704a47df
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632275927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.3632275927
Directory	/workspace/23.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.2870275864
Short name	T5
Test name
Test status
Simulation time	478369499 ps
CPU time	1.18 seconds
Started	Jan 03 12:59:03 PM PST 24
Finished	Jan 03 12:59:47 PM PST 24
Peak memory	200216 kb
Host	smart-7e8f2fdb-d1fa-46ae-bb11-6cb157ed5ece
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870275864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.2870275864
Directory	/workspace/24.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1511726289
Short name	T876
Test name
Test status
Simulation time	460716957 ps
CPU time	0.89 seconds
Started	Jan 03 12:59:12 PM PST 24
Finished	Jan 03 01:00:07 PM PST 24
Peak memory	200320 kb
Host	smart-6abc6182-0332-4157-93c7-c5669ba666ea
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511726289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.1511726289
Directory	/workspace/25.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.1146012092
Short name	T877
Test name
Test status
Simulation time	322368105 ps
CPU time	0.8 seconds
Started	Jan 03 12:59:13 PM PST 24
Finished	Jan 03 01:00:08 PM PST 24
Peak memory	200340 kb
Host	smart-acf56e60-204e-4820-bb60-ea88a2241078
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146012092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.1146012092
Directory	/workspace/26.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.496561496
Short name	T857
Test name
Test status
Simulation time	541303162 ps
CPU time	0.95 seconds
Started	Jan 03 12:59:11 PM PST 24
Finished	Jan 03 01:00:04 PM PST 24
Peak memory	200232 kb
Host	smart-acd68871-b004-4c87-ba1b-a9c11d79424d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496561496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.496561496
Directory	/workspace/27.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.278476793
Short name	T397
Test name
Test status
Simulation time	503336147 ps
CPU time	1.69 seconds
Started	Jan 03 12:59:07 PM PST 24
Finished	Jan 03 12:59:57 PM PST 24
Peak memory	200468 kb
Host	smart-cd19bbfb-d2e6-473b-a665-4698b29e5586
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278476793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.278476793
Directory	/workspace/28.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.2901672134
Short name	T69
Test name
Test status
Simulation time	455746949 ps
CPU time	1.2 seconds
Started	Jan 03 12:58:55 PM PST 24
Finished	Jan 03 12:59:33 PM PST 24
Peak memory	200268 kb
Host	smart-edb07359-d343-40d9-adc8-573746e3059c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901672134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.2901672134
Directory	/workspace/29.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.4114158056
Short name	T76
Test name
Test status
Simulation time	1211335159 ps
CPU time	2.84 seconds
Started	Jan 03 12:58:59 PM PST 24
Finished	Jan 03 12:59:42 PM PST 24
Peak memory	200768 kb
Host	smart-2acb32b2-5a9f-48fe-a4f9-0c77d5b03e48
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114158056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia sing.4114158056
Directory	/workspace/3.adc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2445772340
Short name	T87
Test name
Test status
Simulation time	22824253552 ps
CPU time	22.65 seconds
Started	Jan 03 12:59:06 PM PST 24
Finished	Jan 03 01:00:14 PM PST 24
Peak memory	200884 kb
Host	smart-b834dd1a-9d63-461c-8081-5141eabcebd3
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445772340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_ bash.2445772340
Directory	/workspace/3.adc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3001539860
Short name	T852
Test name
Test status
Simulation time	1188807911 ps
CPU time	1.44 seconds
Started	Jan 03 12:59:10 PM PST 24
Finished	Jan 03 01:00:03 PM PST 24
Peak memory	200456 kb
Host	smart-1b67fabe-8071-4145-bc64-5fdeba8ffeb5
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001539860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r eset.3001539860
Directory	/workspace/3.adc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2392316218
Short name	T868
Test name
Test status
Simulation time	605593288 ps
CPU time	1.18 seconds
Started	Jan 03 12:59:13 PM PST 24
Finished	Jan 03 01:00:08 PM PST 24
Peak memory	208964 kb
Host	smart-0f51b91a-fb16-4301-bfb8-1eac7cfc60d2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392316218 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.2392316218
Directory	/workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.4027149748
Short name	T36
Test name
Test status
Simulation time	417271414 ps
CPU time	1.21 seconds
Started	Jan 03 12:59:11 PM PST 24
Finished	Jan 03 01:00:05 PM PST 24
Peak memory	200452 kb
Host	smart-a2e24c85-668d-421f-a271-e332ac443e90
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027149748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.4027149748
Directory	/workspace/3.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2252397824
Short name	T864
Test name
Test status
Simulation time	503979370 ps
CPU time	1.79 seconds
Started	Jan 03 12:59:11 PM PST 24
Finished	Jan 03 01:00:07 PM PST 24
Peak memory	200140 kb
Host	smart-004e2387-de7b-4754-86a6-bd748cb55949
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252397824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.2252397824
Directory	/workspace/3.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3492693593
Short name	T6
Test name
Test status
Simulation time	4486986735 ps
CPU time	13.6 seconds
Started	Jan 03 12:59:09 PM PST 24
Finished	Jan 03 01:00:13 PM PST 24
Peak memory	200720 kb
Host	smart-d0a7260b-feb7-484e-b675-4c54c9da5401
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492693593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c trl_same_csr_outstanding.3492693593
Directory	/workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.4210496016
Short name	T41
Test name
Test status
Simulation time	490815552 ps
CPU time	3.61 seconds
Started	Jan 03 12:59:07 PM PST 24
Finished	Jan 03 12:59:58 PM PST 24
Peak memory	200660 kb
Host	smart-685d8015-44d1-4cab-b5cb-c62a8c8d4ea5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210496016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.4210496016
Directory	/workspace/3.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1248104963
Short name	T85
Test name
Test status
Simulation time	8025735318 ps
CPU time	21.76 seconds
Started	Jan 03 12:59:07 PM PST 24
Finished	Jan 03 01:00:15 PM PST 24
Peak memory	200772 kb
Host	smart-639e36f0-6382-4010-bfec-4f8fd991c856
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248104963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in tg_err.1248104963
Directory	/workspace/3.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.4012190140
Short name	T24
Test name
Test status
Simulation time	499061624 ps
CPU time	1.21 seconds
Started	Jan 03 12:59:10 PM PST 24
Finished	Jan 03 01:00:02 PM PST 24
Peak memory	200228 kb
Host	smart-d6f0dd66-feb5-479d-a8ec-2aa2d5504988
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012190140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.4012190140
Directory	/workspace/30.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.2141770536
Short name	T354
Test name
Test status
Simulation time	309320894 ps
CPU time	0.82 seconds
Started	Jan 03 12:59:01 PM PST 24
Finished	Jan 03 12:59:43 PM PST 24
Peak memory	200284 kb
Host	smart-977f28d8-b6d1-42c8-8db6-e16a1e698735
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141770536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.2141770536
Directory	/workspace/31.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.82619638
Short name	T388
Test name
Test status
Simulation time	429564548 ps
CPU time	1.56 seconds
Started	Jan 03 12:58:59 PM PST 24
Finished	Jan 03 12:59:41 PM PST 24
Peak memory	200304 kb
Host	smart-4ef3f1b9-1527-4fd7-9f48-d45f65d305a4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82619638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.82619638
Directory	/workspace/32.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.3826661868
Short name	T364
Test name
Test status
Simulation time	310185829 ps
CPU time	1.37 seconds
Started	Jan 03 12:59:00 PM PST 24
Finished	Jan 03 12:59:42 PM PST 24
Peak memory	200296 kb
Host	smart-d3e1730a-c03e-4779-b1d7-c787acf2bfe3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826661868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.3826661868
Directory	/workspace/33.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2698421549
Short name	T356
Test name
Test status
Simulation time	374252835 ps
CPU time	0.85 seconds
Started	Jan 03 12:59:02 PM PST 24
Finished	Jan 03 12:59:45 PM PST 24
Peak memory	200328 kb
Host	smart-adc4da80-b0fc-447c-8243-28d54989fb23
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698421549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.2698421549
Directory	/workspace/34.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1428238904
Short name	T891
Test name
Test status
Simulation time	503801868 ps
CPU time	0.79 seconds
Started	Jan 03 12:58:54 PM PST 24
Finished	Jan 03 12:59:31 PM PST 24
Peak memory	200280 kb
Host	smart-72cf6bcb-f714-436d-b1ae-0499d0bc81b7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428238904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.1428238904
Directory	/workspace/35.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.605009617
Short name	T359
Test name
Test status
Simulation time	453626772 ps
CPU time	0.92 seconds
Started	Jan 03 12:59:04 PM PST 24
Finished	Jan 03 12:59:49 PM PST 24
Peak memory	200320 kb
Host	smart-056e98f9-5382-40d7-ae09-c997f4523b8e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605009617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.605009617
Directory	/workspace/36.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.932992273
Short name	T384
Test name
Test status
Simulation time	471864887 ps
CPU time	0.91 seconds
Started	Jan 03 12:59:07 PM PST 24
Finished	Jan 03 12:59:56 PM PST 24
Peak memory	200284 kb
Host	smart-3258e575-4c99-4843-bdd8-82a262ef1ff7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932992273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.932992273
Directory	/workspace/37.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.720863512
Short name	T363
Test name
Test status
Simulation time	408381946 ps
CPU time	1.63 seconds
Started	Jan 03 12:59:05 PM PST 24
Finished	Jan 03 12:59:51 PM PST 24
Peak memory	200304 kb
Host	smart-822100e3-923d-4a35-bfc7-a7cc80d370de
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720863512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.720863512
Directory	/workspace/38.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.3968856532
Short name	T365
Test name
Test status
Simulation time	525988861 ps
CPU time	0.92 seconds
Started	Jan 03 12:59:18 PM PST 24
Finished	Jan 03 01:00:13 PM PST 24
Peak memory	200476 kb
Host	smart-7e930163-476f-4453-a952-0f9f51504420
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968856532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.3968856532
Directory	/workspace/39.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1989893217
Short name	T83
Test name
Test status
Simulation time	863493097 ps
CPU time	2.79 seconds
Started	Jan 03 12:58:43 PM PST 24
Finished	Jan 03 12:59:15 PM PST 24
Peak memory	200800 kb
Host	smart-bc860a86-ad6f-4e6a-b98c-cffa4313151f
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989893217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia sing.1989893217
Directory	/workspace/4.adc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.4040493663
Short name	T86
Test name
Test status
Simulation time	25550212990 ps
CPU time	16.16 seconds
Started	Jan 03 12:59:15 PM PST 24
Finished	Jan 03 01:00:26 PM PST 24
Peak memory	200776 kb
Host	smart-41e078c1-fe31-4956-a1e3-cb6a056514bd
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040493663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_ bash.4040493663
Directory	/workspace/4.adc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1741700816
Short name	T875
Test name
Test status
Simulation time	956844723 ps
CPU time	1.26 seconds
Started	Jan 03 12:58:47 PM PST 24
Finished	Jan 03 12:59:19 PM PST 24
Peak memory	200592 kb
Host	smart-6117e594-ae16-407d-a6ac-afbe81060379
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741700816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r eset.1741700816
Directory	/workspace/4.adc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2803428614
Short name	T860
Test name
Test status
Simulation time	517501367 ps
CPU time	0.96 seconds
Started	Jan 03 12:58:34 PM PST 24
Finished	Jan 03 12:59:08 PM PST 24
Peak memory	200660 kb
Host	smart-5e27f02f-a949-44e7-a9fb-1e17d0c3de20
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803428614 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.2803428614
Directory	/workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3055235173
Short name	T856
Test name
Test status
Simulation time	525597385 ps
CPU time	1.38 seconds
Started	Jan 03 12:58:54 PM PST 24
Finished	Jan 03 12:59:30 PM PST 24
Peak memory	200588 kb
Host	smart-e3a53857-6a63-4167-b2b3-3cdafaf15d4c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055235173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.3055235173
Directory	/workspace/4.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.672587786
Short name	T360
Test name
Test status
Simulation time	492190539 ps
CPU time	1.7 seconds
Started	Jan 03 12:59:15 PM PST 24
Finished	Jan 03 01:00:11 PM PST 24
Peak memory	200196 kb
Host	smart-73ee34b2-2bbd-4abc-938f-8d6afc4dbf8e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672587786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.672587786
Directory	/workspace/4.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.4068330159
Short name	T867
Test name
Test status
Simulation time	4830593248 ps
CPU time	10.67 seconds
Started	Jan 03 12:58:49 PM PST 24
Finished	Jan 03 12:59:31 PM PST 24
Peak memory	200836 kb
Host	smart-73d4252d-f2f3-4508-bb58-7bdc1cc6d451
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068330159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c trl_same_csr_outstanding.4068330159
Directory	/workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2226031668
Short name	T26
Test name
Test status
Simulation time	527218435 ps
CPU time	1.58 seconds
Started	Jan 03 12:59:15 PM PST 24
Finished	Jan 03 01:00:11 PM PST 24
Peak memory	200716 kb
Host	smart-4705c11e-f7ce-4d23-b68a-aa7fa9f1c872
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226031668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.2226031668
Directory	/workspace/4.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3124449868
Short name	T344
Test name
Test status
Simulation time	8344444486 ps
CPU time	12.02 seconds
Started	Jan 03 12:59:17 PM PST 24
Finished	Jan 03 01:00:23 PM PST 24
Peak memory	200836 kb
Host	smart-5b289c2f-484d-4a11-b1f1-d72b82a05a35
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124449868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in tg_err.3124449868
Directory	/workspace/4.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.2459042935
Short name	T355
Test name
Test status
Simulation time	582788294 ps
CPU time	0.89 seconds
Started	Jan 03 12:59:09 PM PST 24
Finished	Jan 03 01:00:00 PM PST 24
Peak memory	200300 kb
Host	smart-c3659c3b-e259-4f20-a646-05dfcd6eb4ae
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459042935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.2459042935
Directory	/workspace/40.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2460353882
Short name	T361
Test name
Test status
Simulation time	449269944 ps
CPU time	1.67 seconds
Started	Jan 03 12:59:04 PM PST 24
Finished	Jan 03 12:59:50 PM PST 24
Peak memory	200260 kb
Host	smart-f18931dd-9f1f-41ef-ba88-a6fb76337bcf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460353882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.2460353882
Directory	/workspace/41.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2646860530
Short name	T28
Test name
Test status
Simulation time	286070981 ps
CPU time	1.24 seconds
Started	Jan 03 12:59:06 PM PST 24
Finished	Jan 03 12:59:53 PM PST 24
Peak memory	200256 kb
Host	smart-927acfb8-1f09-4819-840e-5b25144eea7d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646860530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.2646860530
Directory	/workspace/42.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.1642632088
Short name	T393
Test name
Test status
Simulation time	508796668 ps
CPU time	1.78 seconds
Started	Jan 03 12:58:54 PM PST 24
Finished	Jan 03 12:59:31 PM PST 24
Peak memory	200272 kb
Host	smart-e14cf30b-75c8-419e-94c1-50a4aff7e067
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642632088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.1642632088
Directory	/workspace/43.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2826065798
Short name	T394
Test name
Test status
Simulation time	525425569 ps
CPU time	1.87 seconds
Started	Jan 03 12:59:05 PM PST 24
Finished	Jan 03 12:59:52 PM PST 24
Peak memory	200260 kb
Host	smart-d09eb937-83e4-423c-a66d-609926279110
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826065798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.2826065798
Directory	/workspace/44.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.2539150426
Short name	T84
Test name
Test status
Simulation time	331687963 ps
CPU time	0.83 seconds
Started	Jan 03 12:59:09 PM PST 24
Finished	Jan 03 01:00:01 PM PST 24
Peak memory	200336 kb
Host	smart-e93555d2-0432-4f14-b4c4-bbee70b09da5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539150426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.2539150426
Directory	/workspace/46.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.1077142996
Short name	T358
Test name
Test status
Simulation time	520000067 ps
CPU time	0.93 seconds
Started	Jan 03 12:59:18 PM PST 24
Finished	Jan 03 01:00:13 PM PST 24
Peak memory	200284 kb
Host	smart-811a080e-5437-49f4-9e53-e24d6c2d55b3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077142996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.1077142996
Directory	/workspace/47.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.1966871193
Short name	T858
Test name
Test status
Simulation time	351924197 ps
CPU time	0.85 seconds
Started	Jan 03 12:59:06 PM PST 24
Finished	Jan 03 12:59:52 PM PST 24
Peak memory	200280 kb
Host	smart-0401ea7a-ac44-47c5-a82e-8cce129636ca
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966871193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.1966871193
Directory	/workspace/48.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.1651896935
Short name	T890
Test name
Test status
Simulation time	446375642 ps
CPU time	1.62 seconds
Started	Jan 03 12:59:06 PM PST 24
Finished	Jan 03 12:59:54 PM PST 24
Peak memory	200516 kb
Host	smart-96e19eec-398d-415d-a156-e8bebd92d4b6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651896935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.1651896935
Directory	/workspace/49.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1383941101
Short name	T881
Test name
Test status
Simulation time	570670137 ps
CPU time	2.06 seconds
Started	Jan 03 12:58:51 PM PST 24
Finished	Jan 03 12:59:25 PM PST 24
Peak memory	200668 kb
Host	smart-0b8a10bd-a3b5-4de9-98d1-8b49118936d6
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383941101 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.1383941101
Directory	/workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.1489114229
Short name	T90
Test name
Test status
Simulation time	468621380 ps
CPU time	1.8 seconds
Started	Jan 03 12:58:47 PM PST 24
Finished	Jan 03 12:59:19 PM PST 24
Peak memory	200548 kb
Host	smart-2b24deca-4938-4c95-af38-b017635c98ea
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489114229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.1489114229
Directory	/workspace/5.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.4199483971
Short name	T878
Test name
Test status
Simulation time	352581778 ps
CPU time	1.46 seconds
Started	Jan 03 12:58:45 PM PST 24
Finished	Jan 03 12:59:17 PM PST 24
Peak memory	200264 kb
Host	smart-6ae1bc7d-eb10-4851-80af-efee2c02850d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199483971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.4199483971
Directory	/workspace/5.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.2074542622
Short name	T402
Test name
Test status
Simulation time	3080016081 ps
CPU time	1.25 seconds
Started	Jan 03 12:58:33 PM PST 24
Finished	Jan 03 12:59:07 PM PST 24
Peak memory	200616 kb
Host	smart-c277974b-7206-4e1c-9c1b-7668ef682d55
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074542622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c trl_same_csr_outstanding.2074542622
Directory	/workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.59592575
Short name	T68
Test name
Test status
Simulation time	824460303 ps
CPU time	2.62 seconds
Started	Jan 03 12:58:37 PM PST 24
Finished	Jan 03 12:59:11 PM PST 24
Peak memory	217128 kb
Host	smart-8d7d9e4a-d264-4d57-bcb8-aebeebdacb56
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59592575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.59592575
Directory	/workspace/5.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3555143819
Short name	T381
Test name
Test status
Simulation time	4349664264 ps
CPU time	10.83 seconds
Started	Jan 03 12:58:42 PM PST 24
Finished	Jan 03 12:59:23 PM PST 24
Peak memory	200836 kb
Host	smart-12b289f5-38c4-4633-9749-0a7300bf938d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555143819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in tg_err.3555143819
Directory	/workspace/5.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.4155257676
Short name	T79
Test name
Test status
Simulation time	555145303 ps
CPU time	2.1 seconds
Started	Jan 03 12:58:46 PM PST 24
Finished	Jan 03 12:59:18 PM PST 24
Peak memory	200680 kb
Host	smart-de616bf6-1d61-49bd-b18d-9622500863bb
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155257676 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.4155257676
Directory	/workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.1983370000
Short name	T865
Test name
Test status
Simulation time	332288942 ps
CPU time	1.33 seconds
Started	Jan 03 12:58:47 PM PST 24
Finished	Jan 03 12:59:19 PM PST 24
Peak memory	200580 kb
Host	smart-ac6b7ed6-17bb-43f4-88bb-684e5356da54
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983370000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.1983370000
Directory	/workspace/6.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3883197118
Short name	T904
Test name
Test status
Simulation time	479919281 ps
CPU time	0.87 seconds
Started	Jan 03 12:58:49 PM PST 24
Finished	Jan 03 12:59:22 PM PST 24
Peak memory	200524 kb
Host	smart-a3a45d6e-9986-4485-9740-42893e2bbc97
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883197118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.3883197118
Directory	/workspace/6.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2015895108
Short name	T396
Test name
Test status
Simulation time	2878985208 ps
CPU time	6.39 seconds
Started	Jan 03 12:58:49 PM PST 24
Finished	Jan 03 12:59:28 PM PST 24
Peak memory	200852 kb
Host	smart-29fd9659-1a6e-4a56-b794-7e7ebd2be778
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015895108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c trl_same_csr_outstanding.2015895108
Directory	/workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2118732375
Short name	T67
Test name
Test status
Simulation time	596730561 ps
CPU time	3.04 seconds
Started	Jan 03 12:58:46 PM PST 24
Finished	Jan 03 12:59:19 PM PST 24
Peak memory	200812 kb
Host	smart-374ff98e-78f6-49f9-83b8-c4247cc1d309
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118732375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.2118732375
Directory	/workspace/6.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3151307818
Short name	T391
Test name
Test status
Simulation time	4467669733 ps
CPU time	4.41 seconds
Started	Jan 03 12:58:47 PM PST 24
Finished	Jan 03 12:59:22 PM PST 24
Peak memory	200832 kb
Host	smart-ac6746f6-b836-45f3-a886-06f19e4d41d9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151307818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in tg_err.3151307818
Directory	/workspace/6.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3728292188
Short name	T898
Test name
Test status
Simulation time	553642617 ps
CPU time	1.21 seconds
Started	Jan 03 12:59:03 PM PST 24
Finished	Jan 03 12:59:49 PM PST 24
Peak memory	200552 kb
Host	smart-778f707b-db9c-4b68-9455-c45704b26664
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728292188 -assert nopostproc +UVM_TESTNAME =adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.3728292188
Directory	/workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.36272851
Short name	T33
Test name
Test status
Simulation time	426038233 ps
CPU time	1.72 seconds
Started	Jan 03 12:59:08 PM PST 24
Finished	Jan 03 01:00:00 PM PST 24
Peak memory	200608 kb
Host	smart-e56fb9c7-8d3b-48db-b765-5d951280c325
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36272851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.36272851
Directory	/workspace/7.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2084615914
Short name	T884
Test name
Test status
Simulation time	309958069 ps
CPU time	1.36 seconds
Started	Jan 03 12:59:09 PM PST 24
Finished	Jan 03 01:00:02 PM PST 24
Peak memory	200264 kb
Host	smart-86dde65e-697d-411b-a947-3eb0eaba5f43
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084615914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.2084615914
Directory	/workspace/7.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.903158533
Short name	T8
Test name
Test status
Simulation time	2565096365 ps
CPU time	5.1 seconds
Started	Jan 03 12:59:04 PM PST 24
Finished	Jan 03 12:59:54 PM PST 24
Peak memory	200680 kb
Host	smart-0f6f86d4-859b-4bea-a274-3e1489366a60
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903158533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ct rl_same_csr_outstanding.903158533
Directory	/workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2877352630
Short name	T369
Test name
Test status
Simulation time	484754445 ps
CPU time	2.45 seconds
Started	Jan 03 12:58:50 PM PST 24
Finished	Jan 03 12:59:24 PM PST 24
Peak memory	200840 kb
Host	smart-f2b07a86-9854-4441-8a44-84eff5aa844c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877352630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.2877352630
Directory	/workspace/7.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2139458960
Short name	T373
Test name
Test status
Simulation time	5544991919 ps
CPU time	2.15 seconds
Started	Jan 03 12:59:02 PM PST 24
Finished	Jan 03 12:59:46 PM PST 24
Peak memory	200772 kb
Host	smart-ccf5b937-77e5-4ab9-a7b6-19b8bb3ab347
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139458960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in tg_err.2139458960
Directory	/workspace/7.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.894403657
Short name	T2
Test name
Test status
Simulation time	650766267 ps
CPU time	1.23 seconds
Started	Jan 03 12:58:57 PM PST 24
Finished	Jan 03 12:59:37 PM PST 24
Peak memory	200572 kb
Host	smart-18ca1049-8d61-408f-a35a-c4e4f0a4a932
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894403657 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.894403657
Directory	/workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3281474129
Short name	T3
Test name
Test status
Simulation time	563684041 ps
CPU time	1 seconds
Started	Jan 03 12:59:21 PM PST 24
Finished	Jan 03 01:00:16 PM PST 24
Peak memory	200548 kb
Host	smart-1a25f2dd-5438-4e76-866e-4bdf444098d3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281474129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.3281474129
Directory	/workspace/8.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.2350501349
Short name	T386
Test name
Test status
Simulation time	599905722 ps
CPU time	0.7 seconds
Started	Jan 03 12:59:02 PM PST 24
Finished	Jan 03 12:59:44 PM PST 24
Peak memory	200488 kb
Host	smart-3407a67c-d754-4439-a3e5-dfd51a01beb8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350501349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.2350501349
Directory	/workspace/8.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.4270275579
Short name	T32
Test name
Test status
Simulation time	4834279970 ps
CPU time	16.05 seconds
Started	Jan 03 12:59:09 PM PST 24
Finished	Jan 03 01:00:16 PM PST 24
Peak memory	200864 kb
Host	smart-2d839c37-d1d8-4451-b92e-a7b8b9905fba
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270275579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c trl_same_csr_outstanding.4270275579
Directory	/workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3383837160
Short name	T859
Test name
Test status
Simulation time	352596866 ps
CPU time	2 seconds
Started	Jan 03 12:59:00 PM PST 24
Finished	Jan 03 12:59:43 PM PST 24
Peak memory	200828 kb
Host	smart-e3e15ed0-2003-4cdb-80da-8e9140ce89d5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383837160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.3383837160
Directory	/workspace/8.adc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1377340945
Short name	T861
Test name
Test status
Simulation time	4211425278 ps
CPU time	5.08 seconds
Started	Jan 03 12:58:47 PM PST 24
Finished	Jan 03 12:59:23 PM PST 24
Peak memory	200820 kb
Host	smart-4fb15e15-e627-4432-97d9-d7f731458f37
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377340945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in tg_err.1377340945
Directory	/workspace/8.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.358405425
Short name	T376
Test name
Test status
Simulation time	524836716 ps
CPU time	1.3 seconds
Started	Jan 03 12:59:02 PM PST 24
Finished	Jan 03 12:59:45 PM PST 24
Peak memory	208996 kb
Host	smart-fe96e140-b342-493e-b21f-1354ade3c725
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358405425 -assert nopostproc +UVM_TESTNAME= adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.358405425
Directory	/workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.4195432414
Short name	T88
Test name
Test status
Simulation time	464933826 ps
CPU time	0.98 seconds
Started	Jan 03 12:58:47 PM PST 24
Finished	Jan 03 12:59:18 PM PST 24
Peak memory	200612 kb
Host	smart-c9dc28cf-cc63-4d76-b992-df2485316749
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195432414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.4195432414
Directory	/workspace/9.adc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3898429527
Short name	T872
Test name
Test status
Simulation time	389989000 ps
CPU time	1.46 seconds
Started	Jan 03 12:59:07 PM PST 24
Finished	Jan 03 12:59:57 PM PST 24
Peak memory	200196 kb
Host	smart-8dcb9868-009e-47f7-86c3-345fd22e914d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898429527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.3898429527
Directory	/workspace/9.adc_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.3230369622
Short name	T866
Test name
Test status
Simulation time	4799105779 ps
CPU time	11.41 seconds
Started	Jan 03 12:58:47 PM PST 24
Finished	Jan 03 12:59:29 PM PST 24
Peak memory	200828 kb
Host	smart-3080ba4b-1361-46a4-866b-eadbc9c20322
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230369622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c trl_same_csr_outstanding.3230369622
Directory	/workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.775385034
Short name	T342
Test name
Test status
Simulation time	4238233301 ps
CPU time	3.61 seconds
Started	Jan 03 12:59:05 PM PST 24
Finished	Jan 03 12:59:53 PM PST 24
Peak memory	200864 kb
Host	smart-3d0dec3e-b0c7-4d57-ac84-e94045d4c4b5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775385034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_int g_err.775385034
Directory	/workspace/9.adc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/0.adc_ctrl_alert_test.3639088138
Short name	T535
Test name
Test status
Simulation time	425934396 ps
CPU time	1.61 seconds
Started	Jan 03 01:15:02 PM PST 24
Finished	Jan 03 01:16:08 PM PST 24
Peak memory	200608 kb
Host	smart-044bacef-f1b4-4e96-8761-d917d630c60a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639088138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.3639088138
Directory	/workspace/0.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/0.adc_ctrl_clock_gating.1939092116
Short name	T664
Test name
Test status
Simulation time	169195484452 ps
CPU time	376.01 seconds
Started	Jan 03 01:14:37 PM PST 24
Finished	Jan 03 01:21:39 PM PST 24
Peak memory	200896 kb
Host	smart-0e3be902-4f1c-4b14-ba2c-0491e58896e0
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939092116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati ng.1939092116
Directory	/workspace/0.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/0.adc_ctrl_filters_both.1504876672
Short name	T798
Test name
Test status
Simulation time	165577903627 ps
CPU time	403.6 seconds
Started	Jan 03 01:14:44 PM PST 24
Finished	Jan 03 01:22:21 PM PST 24
Peak memory	200888 kb
Host	smart-bf578e9f-d002-4ebb-9253-85be6a904a9d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1504876672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.1504876672
Directory	/workspace/0.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/0.adc_ctrl_filters_interrupt.4169075717
Short name	T207
Test name
Test status
Simulation time	162283967139 ps
CPU time	360.6 seconds
Started	Jan 03 01:14:43 PM PST 24
Finished	Jan 03 01:21:37 PM PST 24
Peak memory	200844 kb
Host	smart-95fc053d-5592-4787-8132-aed18e05883a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4169075717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.4169075717
Directory	/workspace/0.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.3555400457
Short name	T696
Test name
Test status
Simulation time	327857625864 ps
CPU time	399.13 seconds
Started	Jan 03 01:14:43 PM PST 24
Finished	Jan 03 01:22:16 PM PST 24
Peak memory	200772 kb
Host	smart-e1d12da3-65e0-44b3-97a3-1565bf93ed35
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555400457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup t_fixed.3555400457
Directory	/workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/0.adc_ctrl_filters_polled.738576544
Short name	T108
Test name
Test status
Simulation time	333970472377 ps
CPU time	717.86 seconds
Started	Jan 03 01:14:35 PM PST 24
Finished	Jan 03 01:27:15 PM PST 24
Peak memory	200940 kb
Host	smart-14055275-4785-4822-8e1d-1c14d747304a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=738576544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.738576544
Directory	/workspace/0.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.2132045447
Short name	T544
Test name
Test status
Simulation time	159298521670 ps
CPU time	57.33 seconds
Started	Jan 03 01:14:32 PM PST 24
Finished	Jan 03 01:16:10 PM PST 24
Peak memory	200812 kb
Host	smart-bc4089e8-1cfd-4e40-8656-f7e7aa72659a
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132045447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe d.2132045447
Directory	/workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/0.adc_ctrl_filters_wakeup.2868219429
Short name	T320
Test name
Test status
Simulation time	329982116767 ps
CPU time	194.46 seconds
Started	Jan 03 01:14:36 PM PST 24
Finished	Jan 03 01:18:35 PM PST 24
Peak memory	200940 kb
Host	smart-68161769-7ef2-4dc5-8d95-df5b5964ff8e
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868219429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_ wakeup.2868219429
Directory	/workspace/0.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/0.adc_ctrl_lowpower_counter.912579850
Short name	T38
Test name
Test status
Simulation time	47479846665 ps
CPU time	29.28 seconds
Started	Jan 03 01:14:46 PM PST 24
Finished	Jan 03 01:16:10 PM PST 24
Peak memory	200696 kb
Host	smart-b0cd8dd3-ff95-4b05-a294-006d2c0b519c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=912579850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.912579850
Directory	/workspace/0.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/0.adc_ctrl_poweron_counter.3285447270
Short name	T719
Test name
Test status
Simulation time	5241140611 ps
CPU time	1.58 seconds
Started	Jan 03 01:14:49 PM PST 24
Finished	Jan 03 01:15:49 PM PST 24
Peak memory	200760 kb
Host	smart-6a083b44-e50c-42c1-9e11-a4d4359a45cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3285447270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.3285447270
Directory	/workspace/0.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/0.adc_ctrl_smoke.1264545036
Short name	T609
Test name
Test status
Simulation time	6075482766 ps
CPU time	7.9 seconds
Started	Jan 03 01:14:33 PM PST 24
Finished	Jan 03 01:15:22 PM PST 24
Peak memory	200640 kb
Host	smart-be77a101-5f24-40e1-957b-bccf5a4a8c46
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1264545036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.1264545036
Directory	/workspace/0.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.1294880130
Short name	T271
Test name
Test status
Simulation time	367114548697 ps
CPU time	131.72 seconds
Started	Jan 03 01:14:44 PM PST 24
Finished	Jan 03 01:17:48 PM PST 24
Peak memory	209680 kb
Host	smart-abe52ba6-7aa9-4e4b-af78-7e48c12e9caa
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294880130 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.1294880130
Directory	/workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/1.adc_ctrl_clock_gating.1452696433
Short name	T160
Test name
Test status
Simulation time	164222672005 ps
CPU time	184.13 seconds
Started	Jan 03 01:14:50 PM PST 24
Finished	Jan 03 01:18:53 PM PST 24
Peak memory	200884 kb
Host	smart-5387c423-cd2d-4da7-aa10-0b9c0be3ba3d
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452696433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati ng.1452696433
Directory	/workspace/1.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/1.adc_ctrl_filters_both.3814599258
Short name	T335
Test name
Test status
Simulation time	499250531930 ps
CPU time	278.8 seconds
Started	Jan 03 01:14:52 PM PST 24
Finished	Jan 03 01:20:31 PM PST 24
Peak memory	200964 kb
Host	smart-74e35e3c-ce0e-4d78-a4fc-1f15f38a0a08
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3814599258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.3814599258
Directory	/workspace/1.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.2476070430
Short name	T119
Test name
Test status
Simulation time	493931126728 ps
CPU time	140.66 seconds
Started	Jan 03 01:14:50 PM PST 24
Finished	Jan 03 01:18:10 PM PST 24
Peak memory	200900 kb
Host	smart-af19ee45-6ed7-4564-b25a-1cec8e07917e
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476070430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup t_fixed.2476070430
Directory	/workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/1.adc_ctrl_filters_polled.2808753310
Short name	T643
Test name
Test status
Simulation time	164419188798 ps
CPU time	305.66 seconds
Started	Jan 03 01:15:07 PM PST 24
Finished	Jan 03 01:21:18 PM PST 24
Peak memory	200932 kb
Host	smart-01e41dd3-196e-4fd1-8101-c8790e14ef61
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2808753310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.2808753310
Directory	/workspace/1.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.1566808811
Short name	T429
Test name
Test status
Simulation time	497525276907 ps
CPU time	621.77 seconds
Started	Jan 03 01:14:56 PM PST 24
Finished	Jan 03 01:26:19 PM PST 24
Peak memory	200828 kb
Host	smart-a92dbc05-0c90-4e63-9805-23170be45028
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566808811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe d.1566808811
Directory	/workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/1.adc_ctrl_filters_wakeup.3522085507
Short name	T556
Test name
Test status
Simulation time	164700859114 ps
CPU time	192.94 seconds
Started	Jan 03 01:14:49 PM PST 24
Finished	Jan 03 01:19:01 PM PST 24
Peak memory	200904 kb
Host	smart-f4a5c4a0-0f05-4f15-b191-79eb6abdd9d4
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522085507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_ wakeup.3522085507
Directory	/workspace/1.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.3332873257
Short name	T537
Test name
Test status
Simulation time	326884394129 ps
CPU time	314.53 seconds
Started	Jan 03 01:14:56 PM PST 24
Finished	Jan 03 01:21:12 PM PST 24
Peak memory	200916 kb
Host	smart-f79eac88-a558-4053-8c1b-aa7ca077cbfa
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332873257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1. adc_ctrl_filters_wakeup_fixed.3332873257
Directory	/workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/1.adc_ctrl_fsm_reset.2215898924
Short name	T732
Test name
Test status
Simulation time	128331731819 ps
CPU time	635.75 seconds
Started	Jan 03 01:15:05 PM PST 24
Finished	Jan 03 01:26:45 PM PST 24
Peak memory	201396 kb
Host	smart-17b655e8-1d4c-429d-b07a-dbdef47b9912
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2215898924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.2215898924
Directory	/workspace/1.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/1.adc_ctrl_lowpower_counter.2479678611
Short name	T831
Test name
Test status
Simulation time	29640432430 ps
CPU time	36.15 seconds
Started	Jan 03 01:14:56 PM PST 24
Finished	Jan 03 01:16:34 PM PST 24
Peak memory	200684 kb
Host	smart-2581a7b9-faa8-4676-bdb2-faec6ec46369
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2479678611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.2479678611
Directory	/workspace/1.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/1.adc_ctrl_poweron_counter.3324974011
Short name	T466
Test name
Test status
Simulation time	3550607773 ps
CPU time	4.59 seconds
Started	Jan 03 01:15:01 PM PST 24
Finished	Jan 03 01:16:09 PM PST 24
Peak memory	200696 kb
Host	smart-0c4e2701-8444-40ad-be32-15339219cfd7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3324974011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.3324974011
Directory	/workspace/1.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/1.adc_ctrl_sec_cm.915141254
Short name	T50
Test name
Test status
Simulation time	4490402596 ps
CPU time	11.61 seconds
Started	Jan 03 01:14:55 PM PST 24
Finished	Jan 03 01:16:07 PM PST 24
Peak memory	215984 kb
Host	smart-dd468fd1-15a4-480a-a1b4-dc8ac9a87825
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915141254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.915141254
Directory	/workspace/1.adc_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/1.adc_ctrl_smoke.2385130541
Short name	T456
Test name
Test status
Simulation time	5817248816 ps
CPU time	2.59 seconds
Started	Jan 03 01:14:55 PM PST 24
Finished	Jan 03 01:15:58 PM PST 24
Peak memory	200696 kb
Host	smart-15203a86-53fa-4030-a0dc-15b43ffed0b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2385130541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.2385130541
Directory	/workspace/1.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/1.adc_ctrl_stress_all.1428975271
Short name	T110
Test name
Test status
Simulation time	167310661864 ps
CPU time	75.75 seconds
Started	Jan 03 01:15:07 PM PST 24
Finished	Jan 03 01:17:28 PM PST 24
Peak memory	200956 kb
Host	smart-d5c59e3b-c666-4f3d-8fa9-bd3bc33be7f9
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428975271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all. 1428975271
Directory	/workspace/1.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/10.adc_ctrl_alert_test.1423834691
Short name	T674
Test name
Test status
Simulation time	358026791 ps
CPU time	0.69 seconds
Started	Jan 03 01:15:05 PM PST 24
Finished	Jan 03 01:16:09 PM PST 24
Peak memory	200644 kb
Host	smart-60f0b051-286a-4d78-90dc-5e51348ccc48
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423834691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.1423834691
Directory	/workspace/10.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/10.adc_ctrl_clock_gating.1710980049
Short name	T772
Test name
Test status
Simulation time	318732000792 ps
CPU time	346 seconds
Started	Jan 03 01:15:09 PM PST 24
Finished	Jan 03 01:22:00 PM PST 24
Peak memory	200844 kb
Host	smart-d551141e-9e48-4639-848e-cfbdbe03f999
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710980049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat ing.1710980049
Directory	/workspace/10.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/10.adc_ctrl_filters_both.3080244434
Short name	T802
Test name
Test status
Simulation time	329514894421 ps
CPU time	407.71 seconds
Started	Jan 03 01:14:54 PM PST 24
Finished	Jan 03 01:22:43 PM PST 24
Peak memory	200984 kb
Host	smart-fd9a48e8-bbb1-4889-9c78-9d0c79afd124
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3080244434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.3080244434
Directory	/workspace/10.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/10.adc_ctrl_filters_interrupt.57339047
Short name	T301
Test name
Test status
Simulation time	167011188616 ps
CPU time	376.3 seconds
Started	Jan 03 01:15:07 PM PST 24
Finished	Jan 03 01:22:28 PM PST 24
Peak memory	200636 kb
Host	smart-b328ed0b-5b58-4e83-93bb-e640ff4d04b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=57339047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.57339047
Directory	/workspace/10.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.2238911186
Short name	T495
Test name
Test status
Simulation time	329583117259 ps
CPU time	775.97 seconds
Started	Jan 03 01:15:01 PM PST 24
Finished	Jan 03 01:29:02 PM PST 24
Peak memory	200856 kb
Host	smart-69caebd9-7e2f-4156-b029-757f2d565b99
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238911186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru pt_fixed.2238911186
Directory	/workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/10.adc_ctrl_filters_polled.3170409730
Short name	T546
Test name
Test status
Simulation time	168944756582 ps
CPU time	413.03 seconds
Started	Jan 03 01:14:58 PM PST 24
Finished	Jan 03 01:22:53 PM PST 24
Peak memory	200844 kb
Host	smart-d6871a04-081f-45ea-a964-5655f67be565
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3170409730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.3170409730
Directory	/workspace/10.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.220053778
Short name	T424
Test name
Test status
Simulation time	158374908106 ps
CPU time	120.59 seconds
Started	Jan 03 01:15:02 PM PST 24
Finished	Jan 03 01:18:06 PM PST 24
Peak memory	200856 kb
Host	smart-809300fd-9897-4d3d-bcce-cf4ab58c90f9
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=220053778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fixe d.220053778
Directory	/workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/10.adc_ctrl_filters_wakeup.3839382301
Short name	T770
Test name
Test status
Simulation time	164629391279 ps
CPU time	382.71 seconds
Started	Jan 03 01:15:08 PM PST 24
Finished	Jan 03 01:22:35 PM PST 24
Peak memory	200964 kb
Host	smart-a407f0d5-ad2e-48ee-be5c-baf4ea7fde8b
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839382301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters _wakeup.3839382301
Directory	/workspace/10.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.3848404041
Short name	T427
Test name
Test status
Simulation time	322000811336 ps
CPU time	195.14 seconds
Started	Jan 03 01:15:09 PM PST 24
Finished	Jan 03 01:19:29 PM PST 24
Peak memory	200836 kb
Host	smart-2a9dc293-86c0-4cb6-83de-b630d5fb7be8
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848404041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10 .adc_ctrl_filters_wakeup_fixed.3848404041
Directory	/workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/10.adc_ctrl_lowpower_counter.751813558
Short name	T529
Test name
Test status
Simulation time	35437902417 ps
CPU time	66.59 seconds
Started	Jan 03 01:15:04 PM PST 24
Finished	Jan 03 01:17:14 PM PST 24
Peak memory	200744 kb
Host	smart-5740825f-b020-4137-9247-0523f3cceeaa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=751813558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.751813558
Directory	/workspace/10.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/10.adc_ctrl_poweron_counter.96402574
Short name	T698
Test name
Test status
Simulation time	2959993236 ps
CPU time	3.83 seconds
Started	Jan 03 01:15:08 PM PST 24
Finished	Jan 03 01:16:17 PM PST 24
Peak memory	200732 kb
Host	smart-f5a7a7b6-3e1b-4cfe-99fc-bf51bc901d2a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=96402574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.96402574
Directory	/workspace/10.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/10.adc_ctrl_smoke.1178865582
Short name	T131
Test name
Test status
Simulation time	6060496149 ps
CPU time	3.7 seconds
Started	Jan 03 01:14:55 PM PST 24
Finished	Jan 03 01:15:59 PM PST 24
Peak memory	200760 kb
Host	smart-1680f492-f1c9-41f4-8a10-16176d5f4596
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1178865582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.1178865582
Directory	/workspace/10.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.2548760627
Short name	T91
Test name
Test status
Simulation time	75062027186 ps
CPU time	87.58 seconds
Started	Jan 03 01:15:11 PM PST 24
Finished	Jan 03 01:17:43 PM PST 24
Peak memory	210328 kb
Host	smart-0be27775-6f24-4357-b438-42c6f61c50a3
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548760627 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.2548760627
Directory	/workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/11.adc_ctrl_alert_test.2919515492
Short name	T42
Test name
Test status
Simulation time	420698076 ps
CPU time	0.84 seconds
Started	Jan 03 01:15:24 PM PST 24
Finished	Jan 03 01:16:31 PM PST 24
Peak memory	200480 kb
Host	smart-9523f639-7fbe-4ce3-8b63-aaacf4492f32
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919515492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.2919515492
Directory	/workspace/11.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/11.adc_ctrl_filters_both.2596026944
Short name	T237
Test name
Test status
Simulation time	166581180534 ps
CPU time	48.3 seconds
Started	Jan 03 01:15:25 PM PST 24
Finished	Jan 03 01:17:17 PM PST 24
Peak memory	200924 kb
Host	smart-61ea51c5-efaf-4b70-ab57-126c733f7fab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2596026944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.2596026944
Directory	/workspace/11.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/11.adc_ctrl_filters_interrupt.3872578036
Short name	T723
Test name
Test status
Simulation time	162621128113 ps
CPU time	72.51 seconds
Started	Jan 03 01:15:16 PM PST 24
Finished	Jan 03 01:17:35 PM PST 24
Peak memory	200860 kb
Host	smart-c606a475-5f03-49e5-9927-4d42436ed276
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3872578036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.3872578036
Directory	/workspace/11.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.2849432412
Short name	T221
Test name
Test status
Simulation time	168676553085 ps
CPU time	405.66 seconds
Started	Jan 03 01:15:07 PM PST 24
Finished	Jan 03 01:22:57 PM PST 24
Peak memory	200872 kb
Host	smart-9cace2c2-ddad-436d-a726-e4eefc2c9141
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849432412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru pt_fixed.2849432412
Directory	/workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/11.adc_ctrl_filters_polled.4211057282
Short name	T281
Test name
Test status
Simulation time	480875493674 ps
CPU time	1042.51 seconds
Started	Jan 03 01:15:04 PM PST 24
Finished	Jan 03 01:33:30 PM PST 24
Peak memory	200812 kb
Host	smart-aff74f80-508e-495e-8c09-f52658b9ab40
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4211057282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.4211057282
Directory	/workspace/11.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.2470698769
Short name	T787
Test name
Test status
Simulation time	497534444824 ps
CPU time	148.23 seconds
Started	Jan 03 01:15:07 PM PST 24
Finished	Jan 03 01:18:40 PM PST 24
Peak memory	200904 kb
Host	smart-34aa8b47-c6ad-4ca5-af74-9820791b0b17
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470698769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix ed.2470698769
Directory	/workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/11.adc_ctrl_filters_wakeup.189858144
Short name	T273
Test name
Test status
Simulation time	164434179127 ps
CPU time	36.9 seconds
Started	Jan 03 01:15:07 PM PST 24
Finished	Jan 03 01:16:48 PM PST 24
Peak memory	200984 kb
Host	smart-226ea82e-7a09-4d9c-9d4e-75c657c8a69e
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189858144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters _wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_ wakeup.189858144
Directory	/workspace/11.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.321754314
Short name	T20
Test name
Test status
Simulation time	485485354234 ps
CPU time	1059.08 seconds
Started	Jan 03 01:15:10 PM PST 24
Finished	Jan 03 01:33:55 PM PST 24
Peak memory	200840 kb
Host	smart-e4af0a33-9ddd-4de7-90eb-c610441fb401
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321754314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ =adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11. adc_ctrl_filters_wakeup_fixed.321754314
Directory	/workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/11.adc_ctrl_lowpower_counter.1550122495
Short name	T551
Test name
Test status
Simulation time	33991384304 ps
CPU time	86.8 seconds
Started	Jan 03 01:15:19 PM PST 24
Finished	Jan 03 01:17:54 PM PST 24
Peak memory	200720 kb
Host	smart-42a1a885-4e0f-4745-801a-3d2787bb680c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1550122495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.1550122495
Directory	/workspace/11.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/11.adc_ctrl_poweron_counter.3805772012
Short name	T580
Test name
Test status
Simulation time	5147509789 ps
CPU time	2.72 seconds
Started	Jan 03 01:15:17 PM PST 24
Finished	Jan 03 01:16:26 PM PST 24
Peak memory	200692 kb
Host	smart-984a91e7-dff3-4105-adbb-fa5cc390e1b2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3805772012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.3805772012
Directory	/workspace/11.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/11.adc_ctrl_smoke.1685549993
Short name	T491
Test name
Test status
Simulation time	5838273460 ps
CPU time	12.6 seconds
Started	Jan 03 01:15:08 PM PST 24
Finished	Jan 03 01:16:26 PM PST 24
Peak memory	200676 kb
Host	smart-aa3364d6-d428-4ab3-b6cf-df058ff998da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1685549993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.1685549993
Directory	/workspace/11.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.1846147285
Short name	T588
Test name
Test status
Simulation time	72809437869 ps
CPU time	240.99 seconds
Started	Jan 03 01:15:17 PM PST 24
Finished	Jan 03 01:20:24 PM PST 24
Peak memory	209752 kb
Host	smart-f8f3041d-7c09-4c03-9822-60e0c8b9c839
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846147285 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.1846147285
Directory	/workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/12.adc_ctrl_alert_test.3525485935
Short name	T528
Test name
Test status
Simulation time	518767647 ps
CPU time	0.68 seconds
Started	Jan 03 01:15:28 PM PST 24
Finished	Jan 03 01:16:31 PM PST 24
Peak memory	200692 kb
Host	smart-566cc8bf-e187-46b4-9c88-3f7a5df4510b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525485935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.3525485935
Directory	/workspace/12.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/12.adc_ctrl_filters_both.2568834053
Short name	T228
Test name
Test status
Simulation time	167299782968 ps
CPU time	429.3 seconds
Started	Jan 03 01:15:25 PM PST 24
Finished	Jan 03 01:23:40 PM PST 24
Peak memory	200952 kb
Host	smart-ff41fa0e-b3e7-4270-ab35-58143d23503d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2568834053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.2568834053
Directory	/workspace/12.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.894684462
Short name	T759
Test name
Test status
Simulation time	165063031130 ps
CPU time	345.22 seconds
Started	Jan 03 01:15:20 PM PST 24
Finished	Jan 03 01:22:11 PM PST 24
Peak memory	200960 kb
Host	smart-91f91174-885b-424f-8209-44ad8fb9536f
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=894684462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrup t_fixed.894684462
Directory	/workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/12.adc_ctrl_filters_polled.2381478640
Short name	T568
Test name
Test status
Simulation time	485735171079 ps
CPU time	543.62 seconds
Started	Jan 03 01:15:31 PM PST 24
Finished	Jan 03 01:25:37 PM PST 24
Peak memory	200908 kb
Host	smart-de6f096b-90b9-40e2-bbae-09f454fc6f58
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2381478640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.2381478640
Directory	/workspace/12.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.840306092
Short name	T628
Test name
Test status
Simulation time	163394877541 ps
CPU time	389.29 seconds
Started	Jan 03 01:15:16 PM PST 24
Finished	Jan 03 01:22:52 PM PST 24
Peak memory	200804 kb
Host	smart-48ffd95f-629d-4548-a951-186ce0e727f5
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=840306092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fixe d.840306092
Directory	/workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.2946523592
Short name	T632
Test name
Test status
Simulation time	161233926064 ps
CPU time	180.88 seconds
Started	Jan 03 01:15:23 PM PST 24
Finished	Jan 03 01:19:30 PM PST 24
Peak memory	200808 kb
Host	smart-5ec6d44d-6238-4e45-b344-3d0023ae361b
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946523592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12 .adc_ctrl_filters_wakeup_fixed.2946523592
Directory	/workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/12.adc_ctrl_fsm_reset.2269991256
Short name	T347
Test name
Test status
Simulation time	109235841989 ps
CPU time	330.42 seconds
Started	Jan 03 01:15:22 PM PST 24
Finished	Jan 03 01:21:59 PM PST 24
Peak memory	201396 kb
Host	smart-53491a4a-9a04-4c52-8d5c-99a6aeb7179a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2269991256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.2269991256
Directory	/workspace/12.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/12.adc_ctrl_lowpower_counter.272318703
Short name	T651
Test name
Test status
Simulation time	22794068064 ps
CPU time	26.07 seconds
Started	Jan 03 01:15:25 PM PST 24
Finished	Jan 03 01:16:57 PM PST 24
Peak memory	200712 kb
Host	smart-86286fac-3f9e-4dd0-860d-e5734bc6da16
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=272318703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.272318703
Directory	/workspace/12.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/12.adc_ctrl_poweron_counter.3253839210
Short name	T477
Test name
Test status
Simulation time	3185190029 ps
CPU time	6.66 seconds
Started	Jan 03 01:15:20 PM PST 24
Finished	Jan 03 01:16:34 PM PST 24
Peak memory	200704 kb
Host	smart-e1382579-1480-46cc-8016-e7dbdd947232
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3253839210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.3253839210
Directory	/workspace/12.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/12.adc_ctrl_smoke.1307958086
Short name	T562
Test name
Test status
Simulation time	5860077282 ps
CPU time	2.56 seconds
Started	Jan 03 01:15:19 PM PST 24
Finished	Jan 03 01:16:28 PM PST 24
Peak memory	200680 kb
Host	smart-6a1fbf04-d552-484d-a46c-0778c56fbec9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1307958086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.1307958086
Directory	/workspace/12.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.3028406725
Short name	T639
Test name
Test status
Simulation time	228846722653 ps
CPU time	346.4 seconds
Started	Jan 03 01:15:23 PM PST 24
Finished	Jan 03 01:22:16 PM PST 24
Peak memory	209700 kb
Host	smart-d3caa436-212b-488e-ad7b-2c314ed0f0eb
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028406725 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.3028406725
Directory	/workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/13.adc_ctrl_alert_test.3104240182
Short name	T434
Test name
Test status
Simulation time	467536684 ps
CPU time	1.6 seconds
Started	Jan 03 01:15:01 PM PST 24
Finished	Jan 03 01:16:07 PM PST 24
Peak memory	200620 kb
Host	smart-1c996040-826b-41bc-a6c1-2f41bcb47f5f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104240182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.3104240182
Directory	/workspace/13.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/13.adc_ctrl_filters_interrupt.66880768
Short name	T249
Test name
Test status
Simulation time	326346871543 ps
CPU time	316.82 seconds
Started	Jan 03 01:15:07 PM PST 24
Finished	Jan 03 01:21:28 PM PST 24
Peak memory	200752 kb
Host	smart-a0f8ebef-882d-404c-9052-dfc3ad326825
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=66880768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.66880768
Directory	/workspace/13.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.193209587
Short name	T473
Test name
Test status
Simulation time	167205683564 ps
CPU time	137.77 seconds
Started	Jan 03 01:14:59 PM PST 24
Finished	Jan 03 01:18:19 PM PST 24
Peak memory	200912 kb
Host	smart-ba4bc1e2-48ba-42f4-9981-0ec8ea6a2e7e
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=193209587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrup t_fixed.193209587
Directory	/workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/13.adc_ctrl_filters_polled.930347397
Short name	T164
Test name
Test status
Simulation time	499211298404 ps
CPU time	108.26 seconds
Started	Jan 03 01:15:03 PM PST 24
Finished	Jan 03 01:17:55 PM PST 24
Peak memory	200880 kb
Host	smart-133a2479-8f5b-4930-bc19-b30ab3ce71d3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=930347397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.930347397
Directory	/workspace/13.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.3624081246
Short name	T658
Test name
Test status
Simulation time	336662091198 ps
CPU time	711.06 seconds
Started	Jan 03 01:15:07 PM PST 24
Finished	Jan 03 01:28:03 PM PST 24
Peak memory	200948 kb
Host	smart-fdfd8b2a-ee6f-4c7c-9271-ccc0ebbe62a1
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624081246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix ed.3624081246
Directory	/workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.2960890900
Short name	T538
Test name
Test status
Simulation time	162801892564 ps
CPU time	36.06 seconds
Started	Jan 03 01:14:54 PM PST 24
Finished	Jan 03 01:16:32 PM PST 24
Peak memory	200800 kb
Host	smart-a225f10d-2a26-4019-9d95-c7e10c4807ad
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960890900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13 .adc_ctrl_filters_wakeup_fixed.2960890900
Directory	/workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/13.adc_ctrl_lowpower_counter.2247134228
Short name	T422
Test name
Test status
Simulation time	29791744625 ps
CPU time	18.21 seconds
Started	Jan 03 01:15:10 PM PST 24
Finished	Jan 03 01:16:33 PM PST 24
Peak memory	200712 kb
Host	smart-860c015c-59b7-4a01-8fc2-70fc1a560afd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2247134228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.2247134228
Directory	/workspace/13.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/13.adc_ctrl_poweron_counter.726481328
Short name	T765
Test name
Test status
Simulation time	3419538686 ps
CPU time	7.89 seconds
Started	Jan 03 01:15:02 PM PST 24
Finished	Jan 03 01:16:14 PM PST 24
Peak memory	200704 kb
Host	smart-ad3a7bf1-a450-41bc-8f04-7f0fe9f22c2d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=726481328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.726481328
Directory	/workspace/13.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/13.adc_ctrl_smoke.1608899378
Short name	T668
Test name
Test status
Simulation time	5943599317 ps
CPU time	15.24 seconds
Started	Jan 03 01:15:27 PM PST 24
Finished	Jan 03 01:16:46 PM PST 24
Peak memory	200696 kb
Host	smart-dcbc54c4-802c-490e-9339-4733eeea9049
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1608899378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.1608899378
Directory	/workspace/13.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.2644072079
Short name	T258
Test name
Test status
Simulation time	124161500541 ps
CPU time	176.31 seconds
Started	Jan 03 01:15:13 PM PST 24
Finished	Jan 03 01:19:15 PM PST 24
Peak memory	209584 kb
Host	smart-b787b9f6-fe93-40f0-a303-ce1228bc912b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644072079 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.2644072079
Directory	/workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/14.adc_ctrl_alert_test.3155775765
Short name	T457
Test name
Test status
Simulation time	470940315 ps
CPU time	0.9 seconds
Started	Jan 03 01:14:56 PM PST 24
Finished	Jan 03 01:15:59 PM PST 24
Peak memory	200712 kb
Host	smart-3484885a-d3ce-4666-8587-b7d770e5f5b5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155775765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.3155775765
Directory	/workspace/14.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/14.adc_ctrl_clock_gating.859429962
Short name	T769
Test name
Test status
Simulation time	328031449803 ps
CPU time	89.71 seconds
Started	Jan 03 01:15:07 PM PST 24
Finished	Jan 03 01:17:42 PM PST 24
Peak memory	200956 kb
Host	smart-74f8d2b2-930e-463d-94cd-3fb9c6a4f661
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859429962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gati ng.859429962
Directory	/workspace/14.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/14.adc_ctrl_filters_both.1315667175
Short name	T316
Test name
Test status
Simulation time	324905578293 ps
CPU time	796.72 seconds
Started	Jan 03 01:15:07 PM PST 24
Finished	Jan 03 01:29:29 PM PST 24
Peak memory	200944 kb
Host	smart-e1462038-2e5b-4761-86ec-1f6a38feaafc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1315667175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.1315667175
Directory	/workspace/14.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/14.adc_ctrl_filters_interrupt.2008232706
Short name	T213
Test name
Test status
Simulation time	165989120269 ps
CPU time	168.54 seconds
Started	Jan 03 01:15:03 PM PST 24
Finished	Jan 03 01:18:56 PM PST 24
Peak memory	200760 kb
Host	smart-cfce9558-1934-49bc-a139-65f82e40e112
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2008232706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.2008232706
Directory	/workspace/14.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.1848428185
Short name	T514
Test name
Test status
Simulation time	321740420890 ps
CPU time	132.25 seconds
Started	Jan 03 01:15:09 PM PST 24
Finished	Jan 03 01:18:26 PM PST 24
Peak memory	200760 kb
Host	smart-7da9ce16-2734-4ad6-8efb-7dc58cb25f83
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848428185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru pt_fixed.1848428185
Directory	/workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/14.adc_ctrl_filters_polled.1751101961
Short name	T627
Test name
Test status
Simulation time	485307233596 ps
CPU time	321.38 seconds
Started	Jan 03 01:15:06 PM PST 24
Finished	Jan 03 01:21:31 PM PST 24
Peak memory	200844 kb
Host	smart-5d40463f-760e-4ebd-83d7-5cd38cacdd43
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1751101961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.1751101961
Directory	/workspace/14.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.391891848
Short name	T636
Test name
Test status
Simulation time	325879083749 ps
CPU time	194.53 seconds
Started	Jan 03 01:15:05 PM PST 24
Finished	Jan 03 01:19:24 PM PST 24
Peak memory	200976 kb
Host	smart-e67da61f-f90e-4e6b-8e10-90918e0ce140
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=391891848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixe d.391891848
Directory	/workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/14.adc_ctrl_filters_wakeup.202432271
Short name	T234
Test name
Test status
Simulation time	329380150356 ps
CPU time	195.61 seconds
Started	Jan 03 01:15:04 PM PST 24
Finished	Jan 03 01:19:23 PM PST 24
Peak memory	200764 kb
Host	smart-7163ef20-6ed9-495e-8ba5-dd6814ea8228
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202432271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters _wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_ wakeup.202432271
Directory	/workspace/14.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.2909555100
Short name	T832
Test name
Test status
Simulation time	495250765801 ps
CPU time	227.84 seconds
Started	Jan 03 01:15:07 PM PST 24
Finished	Jan 03 01:19:59 PM PST 24
Peak memory	200832 kb
Host	smart-c23f7ecf-b488-49ee-a507-6dceea878a13
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909555100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14 .adc_ctrl_filters_wakeup_fixed.2909555100
Directory	/workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/14.adc_ctrl_fsm_reset.3664933498
Short name	T345
Test name
Test status
Simulation time	75929459327 ps
CPU time	479.04 seconds
Started	Jan 03 01:15:07 PM PST 24
Finished	Jan 03 01:24:11 PM PST 24
Peak memory	201396 kb
Host	smart-158890d1-2182-4709-a53c-da2bcdbc7342
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3664933498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.3664933498
Directory	/workspace/14.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/14.adc_ctrl_lowpower_counter.3608904512
Short name	T421
Test name
Test status
Simulation time	43490676503 ps
CPU time	86.2 seconds
Started	Jan 03 01:15:08 PM PST 24
Finished	Jan 03 01:17:40 PM PST 24
Peak memory	200712 kb
Host	smart-c42a9172-20cd-461d-bf34-c72cebae7db7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3608904512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.3608904512
Directory	/workspace/14.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/14.adc_ctrl_poweron_counter.1123736770
Short name	T612
Test name
Test status
Simulation time	4586165832 ps
CPU time	5.59 seconds
Started	Jan 03 01:14:58 PM PST 24
Finished	Jan 03 01:16:05 PM PST 24
Peak memory	200732 kb
Host	smart-2cb8dc68-e9e0-4c90-9dec-1d552f2200b8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1123736770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.1123736770
Directory	/workspace/14.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/14.adc_ctrl_smoke.965518302
Short name	T704
Test name
Test status
Simulation time	6128939395 ps
CPU time	15.33 seconds
Started	Jan 03 01:15:03 PM PST 24
Finished	Jan 03 01:16:22 PM PST 24
Peak memory	200612 kb
Host	smart-f7b64537-ee13-4fcb-92a9-929e386e9202
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=965518302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.965518302
Directory	/workspace/14.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.87107834
Short name	T312
Test name
Test status
Simulation time	178048689993 ps
CPU time	473.88 seconds
Started	Jan 03 01:15:08 PM PST 24
Finished	Jan 03 01:24:06 PM PST 24
Peak memory	209576 kb
Host	smart-0b13e162-b38e-4b1f-b541-dbc9e7030a28
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87107834 -assert nopos tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.87107834
Directory	/workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/15.adc_ctrl_alert_test.1695632278
Short name	T767
Test name
Test status
Simulation time	324837773 ps
CPU time	1.35 seconds
Started	Jan 03 01:15:18 PM PST 24
Finished	Jan 03 01:16:26 PM PST 24
Peak memory	200620 kb
Host	smart-fc016797-9ead-445b-8f15-30c60efb6b2e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695632278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.1695632278
Directory	/workspace/15.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/15.adc_ctrl_clock_gating.197645480
Short name	T304
Test name
Test status
Simulation time	327365749870 ps
CPU time	339.12 seconds
Started	Jan 03 01:15:20 PM PST 24
Finished	Jan 03 01:22:06 PM PST 24
Peak memory	200896 kb
Host	smart-e9dec109-23fb-4cff-8bac-0aa4cf972b01
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197645480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gati ng.197645480
Directory	/workspace/15.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.3161396162
Short name	T492
Test name
Test status
Simulation time	168127101050 ps
CPU time	300.83 seconds
Started	Jan 03 01:15:17 PM PST 24
Finished	Jan 03 01:21:24 PM PST 24
Peak memory	200884 kb
Host	smart-32454ba6-ac97-42d7-ba2a-ba804466b390
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161396162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru pt_fixed.3161396162
Directory	/workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/15.adc_ctrl_filters_polled.137248930
Short name	T147
Test name
Test status
Simulation time	321968033732 ps
CPU time	221.01 seconds
Started	Jan 03 01:15:07 PM PST 24
Finished	Jan 03 01:19:52 PM PST 24
Peak memory	200908 kb
Host	smart-2b3cb184-6441-4f0d-9dbf-18623c479a83
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=137248930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.137248930
Directory	/workspace/15.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.3010024575
Short name	T482
Test name
Test status
Simulation time	334967328302 ps
CPU time	843.87 seconds
Started	Jan 03 01:15:09 PM PST 24
Finished	Jan 03 01:30:18 PM PST 24
Peak memory	200844 kb
Host	smart-b3466084-9723-4c45-aafa-e00ffd597268
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010024575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix ed.3010024575
Directory	/workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/15.adc_ctrl_filters_wakeup.3991109382
Short name	T292
Test name
Test status
Simulation time	328081905467 ps
CPU time	90.92 seconds
Started	Jan 03 01:15:15 PM PST 24
Finished	Jan 03 01:17:52 PM PST 24
Peak memory	200880 kb
Host	smart-8950389f-65b5-44ab-a917-4faac441c52e
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991109382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters _wakeup.3991109382
Directory	/workspace/15.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.566131840
Short name	T600
Test name
Test status
Simulation time	326123494938 ps
CPU time	690.65 seconds
Started	Jan 03 01:15:18 PM PST 24
Finished	Jan 03 01:27:56 PM PST 24
Peak memory	200888 kb
Host	smart-ecb2f987-fa3a-4228-9788-9b49b6ca6f5e
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566131840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ =adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15. adc_ctrl_filters_wakeup_fixed.566131840
Directory	/workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/15.adc_ctrl_fsm_reset.1548162901
Short name	T801
Test name
Test status
Simulation time	120078360868 ps
CPU time	687.32 seconds
Started	Jan 03 01:15:17 PM PST 24
Finished	Jan 03 01:27:51 PM PST 24
Peak memory	201340 kb
Host	smart-ed370b25-f71e-4998-b9db-019513ae167f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1548162901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.1548162901
Directory	/workspace/15.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/15.adc_ctrl_lowpower_counter.1695615482
Short name	T829
Test name
Test status
Simulation time	38293171466 ps
CPU time	83.57 seconds
Started	Jan 03 01:15:22 PM PST 24
Finished	Jan 03 01:17:52 PM PST 24
Peak memory	200700 kb
Host	smart-efe8b842-612c-4d40-a44d-0fceefbbf333
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1695615482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.1695615482
Directory	/workspace/15.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/15.adc_ctrl_poweron_counter.1553529821
Short name	T778
Test name
Test status
Simulation time	4017459446 ps
CPU time	3.22 seconds
Started	Jan 03 01:15:19 PM PST 24
Finished	Jan 03 01:16:30 PM PST 24
Peak memory	200760 kb
Host	smart-d12cd3a6-9c27-4139-9f69-66c04ea4dabc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1553529821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.1553529821
Directory	/workspace/15.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/15.adc_ctrl_smoke.2076127890
Short name	T432
Test name
Test status
Simulation time	5957482104 ps
CPU time	1.98 seconds
Started	Jan 03 01:15:01 PM PST 24
Finished	Jan 03 01:16:07 PM PST 24
Peak memory	200692 kb
Host	smart-6ee1fbc6-7284-4d3e-8b68-7a90d3569526
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2076127890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.2076127890
Directory	/workspace/15.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/15.adc_ctrl_stress_all.1354913486
Short name	T497
Test name
Test status
Simulation time	52069443605 ps
CPU time	56.39 seconds
Started	Jan 03 01:15:20 PM PST 24
Finished	Jan 03 01:17:22 PM PST 24
Peak memory	200916 kb
Host	smart-f77bf4d1-25df-4b24-bee8-c5f83f0461b8
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354913486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all .1354913486
Directory	/workspace/15.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/16.adc_ctrl_alert_test.3875061638
Short name	T573
Test name
Test status
Simulation time	400713706 ps
CPU time	1.48 seconds
Started	Jan 03 01:15:09 PM PST 24
Finished	Jan 03 01:16:16 PM PST 24
Peak memory	200484 kb
Host	smart-48cc38b5-44a4-4e80-a180-2751aebb97ee
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875061638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.3875061638
Directory	/workspace/16.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/16.adc_ctrl_filters_both.551612250
Short name	T220
Test name
Test status
Simulation time	510777217074 ps
CPU time	1257.42 seconds
Started	Jan 03 01:15:02 PM PST 24
Finished	Jan 03 01:37:04 PM PST 24
Peak memory	200836 kb
Host	smart-758b93b4-c9ff-48cf-b4fc-afbc11ed2534
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=551612250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.551612250
Directory	/workspace/16.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/16.adc_ctrl_filters_interrupt.2345776196
Short name	T570
Test name
Test status
Simulation time	327296032777 ps
CPU time	807.26 seconds
Started	Jan 03 01:15:23 PM PST 24
Finished	Jan 03 01:29:57 PM PST 24
Peak memory	200868 kb
Host	smart-c6e5109f-c2c1-4ade-9f1c-24d4d73de7a7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2345776196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.2345776196
Directory	/workspace/16.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.258762561
Short name	T534
Test name
Test status
Simulation time	162860383215 ps
CPU time	347.73 seconds
Started	Jan 03 01:14:53 PM PST 24
Finished	Jan 03 01:21:42 PM PST 24
Peak memory	200920 kb
Host	smart-f9caff2a-be5a-4688-b374-af5e31178f1a
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=258762561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrup t_fixed.258762561
Directory	/workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/16.adc_ctrl_filters_polled.1240189533
Short name	T757
Test name
Test status
Simulation time	332896691449 ps
CPU time	811.9 seconds
Started	Jan 03 01:15:30 PM PST 24
Finished	Jan 03 01:30:04 PM PST 24
Peak memory	201004 kb
Host	smart-6a60af54-a0e7-453c-a090-2c12d2366bf3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1240189533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.1240189533
Directory	/workspace/16.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.2081929554
Short name	T533
Test name
Test status
Simulation time	322740870055 ps
CPU time	187.89 seconds
Started	Jan 03 01:15:21 PM PST 24
Finished	Jan 03 01:19:36 PM PST 24
Peak memory	200856 kb
Host	smart-baf5ff4d-8658-485e-81a0-e5a3a304ea83
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081929554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix ed.2081929554
Directory	/workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.4033601901
Short name	T441
Test name
Test status
Simulation time	328132237454 ps
CPU time	394.07 seconds
Started	Jan 03 01:15:19 PM PST 24
Finished	Jan 03 01:23:01 PM PST 24
Peak memory	200920 kb
Host	smart-a573fb9d-ffb7-4941-9ad4-cc77d38e0eeb
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033601901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16 .adc_ctrl_filters_wakeup_fixed.4033601901
Directory	/workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/16.adc_ctrl_lowpower_counter.3468580386
Short name	T694
Test name
Test status
Simulation time	27497778677 ps
CPU time	18.76 seconds
Started	Jan 03 01:15:03 PM PST 24
Finished	Jan 03 01:16:25 PM PST 24
Peak memory	200592 kb
Host	smart-aebb8e8a-9b68-458b-98b0-3cbd9565c493
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3468580386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.3468580386
Directory	/workspace/16.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/16.adc_ctrl_poweron_counter.3000347105
Short name	T561
Test name
Test status
Simulation time	4792800633 ps
CPU time	6.91 seconds
Started	Jan 03 01:15:01 PM PST 24
Finished	Jan 03 01:16:12 PM PST 24
Peak memory	200692 kb
Host	smart-c3b1bf02-d375-4491-ad72-5aace3b411e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3000347105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.3000347105
Directory	/workspace/16.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/16.adc_ctrl_smoke.2905535946
Short name	T139
Test name
Test status
Simulation time	5820211012 ps
CPU time	4.5 seconds
Started	Jan 03 01:15:18 PM PST 24
Finished	Jan 03 01:16:29 PM PST 24
Peak memory	200700 kb
Host	smart-6f4e0224-b168-4f5a-8635-8d76fa2da5d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2905535946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.2905535946
Directory	/workspace/16.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/16.adc_ctrl_stress_all.2312312919
Short name	T321
Test name
Test status
Simulation time	206480339336 ps
CPU time	468.9 seconds
Started	Jan 03 01:15:09 PM PST 24
Finished	Jan 03 01:24:03 PM PST 24
Peak memory	200444 kb
Host	smart-e7e5ea66-cf1f-41dc-935d-73efd8e40362
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312312919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all .2312312919
Directory	/workspace/16.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.1361996007
Short name	T106
Test name
Test status
Simulation time	85093332958 ps
CPU time	135.52 seconds
Started	Jan 03 01:15:08 PM PST 24
Finished	Jan 03 01:18:29 PM PST 24
Peak memory	209532 kb
Host	smart-75a9a041-62c0-4a98-b6cd-456718d62ebb
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361996007 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.1361996007
Directory	/workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/17.adc_ctrl_alert_test.2568049409
Short name	T449
Test name
Test status
Simulation time	322980324 ps
CPU time	0.95 seconds
Started	Jan 03 01:15:19 PM PST 24
Finished	Jan 03 01:16:28 PM PST 24
Peak memory	200652 kb
Host	smart-56d4c3aa-d1f9-46db-be71-5e1c45a47676
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568049409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.2568049409
Directory	/workspace/17.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/17.adc_ctrl_clock_gating.455152256
Short name	T145
Test name
Test status
Simulation time	499766521737 ps
CPU time	663.59 seconds
Started	Jan 03 01:15:20 PM PST 24
Finished	Jan 03 01:27:30 PM PST 24
Peak memory	200832 kb
Host	smart-5a271d05-e7f9-4d6c-ae16-8c21fcb52135
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455152256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gati ng.455152256
Directory	/workspace/17.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/17.adc_ctrl_filters_both.3322711763
Short name	T707
Test name
Test status
Simulation time	166160038808 ps
CPU time	105.31 seconds
Started	Jan 03 01:15:24 PM PST 24
Finished	Jan 03 01:18:14 PM PST 24
Peak memory	200900 kb
Host	smart-f876a8d8-e191-497e-af80-beb40d7ab7a5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3322711763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.3322711763
Directory	/workspace/17.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/17.adc_ctrl_filters_interrupt.623850281
Short name	T59
Test name
Test status
Simulation time	334978862159 ps
CPU time	762.18 seconds
Started	Jan 03 01:15:17 PM PST 24
Finished	Jan 03 01:29:06 PM PST 24
Peak memory	200876 kb
Host	smart-ebf9c9be-028a-4260-973f-4d5cd23c6972
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=623850281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.623850281
Directory	/workspace/17.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.3710330600
Short name	T808
Test name
Test status
Simulation time	329478660280 ps
CPU time	124.07 seconds
Started	Jan 03 01:15:20 PM PST 24
Finished	Jan 03 01:18:30 PM PST 24
Peak memory	200848 kb
Host	smart-61940526-6dd8-473d-97e6-92bdb3a8c5cf
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710330600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru pt_fixed.3710330600
Directory	/workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/17.adc_ctrl_filters_polled.2644751972
Short name	T822
Test name
Test status
Simulation time	328214611472 ps
CPU time	186.6 seconds
Started	Jan 03 01:15:16 PM PST 24
Finished	Jan 03 01:19:28 PM PST 24
Peak memory	200888 kb
Host	smart-1c304afa-2dd8-41de-8267-4ff38f55b55d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2644751972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.2644751972
Directory	/workspace/17.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.1305853144
Short name	T583
Test name
Test status
Simulation time	490059279985 ps
CPU time	276.5 seconds
Started	Jan 03 01:15:18 PM PST 24
Finished	Jan 03 01:21:01 PM PST 24
Peak memory	200896 kb
Host	smart-4fa9d33e-c35f-4b16-932d-f3baee479eb0
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305853144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix ed.1305853144
Directory	/workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/17.adc_ctrl_filters_wakeup.434834696
Short name	T635
Test name
Test status
Simulation time	490418369571 ps
CPU time	570.98 seconds
Started	Jan 03 01:15:16 PM PST 24
Finished	Jan 03 01:25:54 PM PST 24
Peak memory	200940 kb
Host	smart-02c10739-3603-4892-913a-ef5bda653f98
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434834696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters _wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_ wakeup.434834696
Directory	/workspace/17.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.2663028078
Short name	T442
Test name
Test status
Simulation time	489330543676 ps
CPU time	1091.55 seconds
Started	Jan 03 01:15:20 PM PST 24
Finished	Jan 03 01:34:37 PM PST 24
Peak memory	200848 kb
Host	smart-ec45bce2-2794-4ea2-85ff-4a63896db2ae
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663028078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17 .adc_ctrl_filters_wakeup_fixed.2663028078
Directory	/workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/17.adc_ctrl_fsm_reset.654603995
Short name	T185
Test name
Test status
Simulation time	101868398656 ps
CPU time	397.32 seconds
Started	Jan 03 01:15:19 PM PST 24
Finished	Jan 03 01:23:04 PM PST 24
Peak memory	201320 kb
Host	smart-6185a653-749d-4dca-83b7-4c7ad559f18d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=654603995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.654603995
Directory	/workspace/17.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/17.adc_ctrl_lowpower_counter.1858417818
Short name	T771
Test name
Test status
Simulation time	28026989926 ps
CPU time	17.19 seconds
Started	Jan 03 01:15:22 PM PST 24
Finished	Jan 03 01:16:46 PM PST 24
Peak memory	200716 kb
Host	smart-7a0e0aae-cbb6-4ab7-98f0-9ca1649d89ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1858417818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.1858417818
Directory	/workspace/17.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/17.adc_ctrl_poweron_counter.951672670
Short name	T644
Test name
Test status
Simulation time	4211569005 ps
CPU time	1.55 seconds
Started	Jan 03 01:15:24 PM PST 24
Finished	Jan 03 01:16:31 PM PST 24
Peak memory	200724 kb
Host	smart-7cb8d417-f9b0-4eec-a532-1fa0acb39a97
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=951672670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.951672670
Directory	/workspace/17.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/17.adc_ctrl_smoke.2413201109
Short name	T447
Test name
Test status
Simulation time	6144854338 ps
CPU time	2.49 seconds
Started	Jan 03 01:15:09 PM PST 24
Finished	Jan 03 01:16:17 PM PST 24
Peak memory	200684 kb
Host	smart-ada3f688-1f11-470a-8946-76b99165b286
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2413201109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.2413201109
Directory	/workspace/17.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/17.adc_ctrl_stress_all.2287617933
Short name	T746
Test name
Test status
Simulation time	350561325840 ps
CPU time	439.7 seconds
Started	Jan 03 01:15:18 PM PST 24
Finished	Jan 03 01:23:44 PM PST 24
Peak memory	200856 kb
Host	smart-85a5a99b-fe6f-468f-91fc-58be63b6852c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287617933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all .2287617933
Directory	/workspace/17.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.291316475
Short name	T645
Test name
Test status
Simulation time	131950390908 ps
CPU time	58.05 seconds
Started	Jan 03 01:15:18 PM PST 24
Finished	Jan 03 01:17:22 PM PST 24
Peak memory	200956 kb
Host	smart-baa7e311-985b-4af1-8707-e637d094790f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291316475 -assert nopo stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.291316475
Directory	/workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/18.adc_ctrl_alert_test.35028470
Short name	T747
Test name
Test status
Simulation time	376362676 ps
CPU time	0.7 seconds
Started	Jan 03 01:15:39 PM PST 24
Finished	Jan 03 01:16:38 PM PST 24
Peak memory	200684 kb
Host	smart-b898f72f-07eb-4b99-9096-6667a31ed93a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35028470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.35028470
Directory	/workspace/18.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/18.adc_ctrl_filters_both.1451081068
Short name	T170
Test name
Test status
Simulation time	163838235430 ps
CPU time	339.82 seconds
Started	Jan 03 01:15:27 PM PST 24
Finished	Jan 03 01:22:10 PM PST 24
Peak memory	200936 kb
Host	smart-e28dc14a-7a7e-48d0-88cd-87eef660f90c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1451081068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.1451081068
Directory	/workspace/18.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/18.adc_ctrl_filters_interrupt.2996506632
Short name	T175
Test name
Test status
Simulation time	324828289264 ps
CPU time	793.86 seconds
Started	Jan 03 01:15:19 PM PST 24
Finished	Jan 03 01:29:41 PM PST 24
Peak memory	200948 kb
Host	smart-cca79ae6-6195-4a5e-80d7-e74a714410ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2996506632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.2996506632
Directory	/workspace/18.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.485371699
Short name	T412
Test name
Test status
Simulation time	326862278808 ps
CPU time	720.58 seconds
Started	Jan 03 01:15:23 PM PST 24
Finished	Jan 03 01:28:30 PM PST 24
Peak memory	200912 kb
Host	smart-2cb9c29d-907b-4d61-9b97-605541ee56e6
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=485371699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrup t_fixed.485371699
Directory	/workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/18.adc_ctrl_filters_polled.3198362419
Short name	T322
Test name
Test status
Simulation time	324244713742 ps
CPU time	770.52 seconds
Started	Jan 03 01:15:22 PM PST 24
Finished	Jan 03 01:29:18 PM PST 24
Peak memory	200868 kb
Host	smart-85f90dc1-9d8d-4922-9f5f-62a47339c3ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3198362419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.3198362419
Directory	/workspace/18.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.506861790
Short name	T406
Test name
Test status
Simulation time	166791838616 ps
CPU time	196.28 seconds
Started	Jan 03 01:15:22 PM PST 24
Finished	Jan 03 01:19:44 PM PST 24
Peak memory	200992 kb
Host	smart-31d98ccb-cd54-44b4-9381-f999bdbfbefa
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=506861790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fixe d.506861790
Directory	/workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/18.adc_ctrl_filters_wakeup.1653395588
Short name	T319
Test name
Test status
Simulation time	165944154540 ps
CPU time	368.31 seconds
Started	Jan 03 01:15:19 PM PST 24
Finished	Jan 03 01:22:35 PM PST 24
Peak memory	200948 kb
Host	smart-94c6963a-0cca-4070-8914-d95ef3e969f3
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653395588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters _wakeup.1653395588
Directory	/workspace/18.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.2430737190
Short name	T625
Test name
Test status
Simulation time	325223289286 ps
CPU time	746.69 seconds
Started	Jan 03 01:15:23 PM PST 24
Finished	Jan 03 01:28:56 PM PST 24
Peak memory	200908 kb
Host	smart-7f65b024-67f8-4df8-adce-07c90a6bdd35
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430737190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18 .adc_ctrl_filters_wakeup_fixed.2430737190
Directory	/workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/18.adc_ctrl_fsm_reset.4285184042
Short name	T346
Test name
Test status
Simulation time	71596926233 ps
CPU time	360.07 seconds
Started	Jan 03 01:15:27 PM PST 24
Finished	Jan 03 01:22:30 PM PST 24
Peak memory	201396 kb
Host	smart-1935730f-a600-4a6b-98d0-cb7e7d632b64
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4285184042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.4285184042
Directory	/workspace/18.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/18.adc_ctrl_lowpower_counter.373463097
Short name	T18
Test name
Test status
Simulation time	27380942695 ps
CPU time	65.06 seconds
Started	Jan 03 01:15:28 PM PST 24
Finished	Jan 03 01:17:36 PM PST 24
Peak memory	200764 kb
Host	smart-9a82b0dd-4703-4bb8-b801-ccac6b2268ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=373463097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.373463097
Directory	/workspace/18.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/18.adc_ctrl_poweron_counter.2881160892
Short name	T505
Test name
Test status
Simulation time	3773819026 ps
CPU time	4.74 seconds
Started	Jan 03 01:15:39 PM PST 24
Finished	Jan 03 01:16:42 PM PST 24
Peak memory	200720 kb
Host	smart-a4f6e4bd-4075-48f0-9e77-0b2b72d6ed6e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2881160892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.2881160892
Directory	/workspace/18.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/18.adc_ctrl_smoke.3724874122
Short name	T58
Test name
Test status
Simulation time	5582613011 ps
CPU time	12 seconds
Started	Jan 03 01:15:21 PM PST 24
Finished	Jan 03 01:16:38 PM PST 24
Peak memory	200708 kb
Host	smart-640e4d56-e838-4522-914b-5bfb992d8deb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3724874122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.3724874122
Directory	/workspace/18.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/18.adc_ctrl_stress_all.2785181017
Short name	T192
Test name
Test status
Simulation time	460862605824 ps
CPU time	571.4 seconds
Started	Jan 03 01:15:39 PM PST 24
Finished	Jan 03 01:26:09 PM PST 24
Peak memory	201284 kb
Host	smart-0e22d2dd-2aa0-4cd4-a87a-7118060048d8
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785181017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all .2785181017
Directory	/workspace/18.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.3151061776
Short name	T814
Test name
Test status
Simulation time	259355737680 ps
CPU time	345.66 seconds
Started	Jan 03 01:15:29 PM PST 24
Finished	Jan 03 01:22:17 PM PST 24
Peak memory	217208 kb
Host	smart-83e87297-3053-4896-9df2-cdd161f81754
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151061776 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.3151061776
Directory	/workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/19.adc_ctrl_alert_test.2014892378
Short name	T608
Test name
Test status
Simulation time	427505036 ps
CPU time	1.09 seconds
Started	Jan 03 01:15:47 PM PST 24
Finished	Jan 03 01:16:42 PM PST 24
Peak memory	200584 kb
Host	smart-2f6260b2-0bd1-499c-bb1a-573fd175cd3a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014892378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.2014892378
Directory	/workspace/19.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/19.adc_ctrl_filters_interrupt.3940155860
Short name	T253
Test name
Test status
Simulation time	491976257042 ps
CPU time	333.48 seconds
Started	Jan 03 01:15:32 PM PST 24
Finished	Jan 03 01:22:07 PM PST 24
Peak memory	200804 kb
Host	smart-dca7a714-2c9a-4a99-9103-8a5210f1fb80
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3940155860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.3940155860
Directory	/workspace/19.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.2761557798
Short name	T436
Test name
Test status
Simulation time	504961988955 ps
CPU time	1209.32 seconds
Started	Jan 03 01:15:44 PM PST 24
Finished	Jan 03 01:36:50 PM PST 24
Peak memory	200904 kb
Host	smart-0dcad357-fa93-4c98-b39b-d4c1aa177ae0
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761557798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru pt_fixed.2761557798
Directory	/workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/19.adc_ctrl_filters_polled.3935745228
Short name	T165
Test name
Test status
Simulation time	332660675016 ps
CPU time	197.02 seconds
Started	Jan 03 01:15:28 PM PST 24
Finished	Jan 03 01:19:48 PM PST 24
Peak memory	200796 kb
Host	smart-90927c25-4b65-43b0-9079-cf8871b369e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3935745228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.3935745228
Directory	/workspace/19.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.1376206531
Short name	T677
Test name
Test status
Simulation time	330141561534 ps
CPU time	691.16 seconds
Started	Jan 03 01:15:29 PM PST 24
Finished	Jan 03 01:28:03 PM PST 24
Peak memory	200720 kb
Host	smart-37c3ee50-47c6-4eb9-be56-7af8df950b2d
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376206531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix ed.1376206531
Directory	/workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.1336753979
Short name	T835
Test name
Test status
Simulation time	488677548407 ps
CPU time	593.69 seconds
Started	Jan 03 01:15:31 PM PST 24
Finished	Jan 03 01:26:27 PM PST 24
Peak memory	200732 kb
Host	smart-1f9bc14f-247c-4be2-9a8c-82a8c928da05
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336753979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19 .adc_ctrl_filters_wakeup_fixed.1336753979
Directory	/workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/19.adc_ctrl_fsm_reset.1008485956
Short name	T348
Test name
Test status
Simulation time	117697154811 ps
CPU time	423.91 seconds
Started	Jan 03 01:15:46 PM PST 24
Finished	Jan 03 01:23:45 PM PST 24
Peak memory	201288 kb
Host	smart-bc9721ad-bbd9-48a8-b384-d03015fa5d76
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1008485956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.1008485956
Directory	/workspace/19.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/19.adc_ctrl_lowpower_counter.478174773
Short name	T512
Test name
Test status
Simulation time	26797907729 ps
CPU time	58.75 seconds
Started	Jan 03 01:15:26 PM PST 24
Finished	Jan 03 01:17:29 PM PST 24
Peak memory	200828 kb
Host	smart-b46c4cab-f0e6-4aa7-b6db-84482e723a6a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=478174773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.478174773
Directory	/workspace/19.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/19.adc_ctrl_poweron_counter.2766796156
Short name	T599
Test name
Test status
Simulation time	4201534414 ps
CPU time	9.88 seconds
Started	Jan 03 01:15:46 PM PST 24
Finished	Jan 03 01:16:51 PM PST 24
Peak memory	200752 kb
Host	smart-d17d9340-292c-448e-9ccd-0e6f331f0cff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2766796156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.2766796156
Directory	/workspace/19.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/19.adc_ctrl_smoke.3719162012
Short name	T488
Test name
Test status
Simulation time	5719303033 ps
CPU time	4.25 seconds
Started	Jan 03 01:15:39 PM PST 24
Finished	Jan 03 01:16:42 PM PST 24
Peak memory	200720 kb
Host	smart-d058ef44-e69b-494b-a40d-2fff8a2c010d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3719162012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.3719162012
Directory	/workspace/19.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/19.adc_ctrl_stress_all.3702007141
Short name	T218
Test name
Test status
Simulation time	355608312683 ps
CPU time	183.7 seconds
Started	Jan 03 01:15:50 PM PST 24
Finished	Jan 03 01:19:47 PM PST 24
Peak memory	200860 kb
Host	smart-b10c6a66-5b26-4203-a860-13fe1797df6d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702007141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all .3702007141
Directory	/workspace/19.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/2.adc_ctrl_alert_test.2915365478
Short name	T742
Test name
Test status
Simulation time	421618456 ps
CPU time	0.87 seconds
Started	Jan 03 01:14:32 PM PST 24
Finished	Jan 03 01:15:12 PM PST 24
Peak memory	200624 kb
Host	smart-2e908dae-3219-4fdd-908f-3c8272100fd7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915365478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.2915365478
Directory	/workspace/2.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/2.adc_ctrl_clock_gating.2340406234
Short name	T231
Test name
Test status
Simulation time	332117600907 ps
CPU time	107.17 seconds
Started	Jan 03 01:15:10 PM PST 24
Finished	Jan 03 01:18:03 PM PST 24
Peak memory	200992 kb
Host	smart-fa99c9aa-3819-483e-96d1-515f554d6e30
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340406234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati ng.2340406234
Directory	/workspace/2.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/2.adc_ctrl_filters_both.3500206172
Short name	T222
Test name
Test status
Simulation time	157607724631 ps
CPU time	231.18 seconds
Started	Jan 03 01:14:32 PM PST 24
Finished	Jan 03 01:19:04 PM PST 24
Peak memory	200840 kb
Host	smart-1ec598fd-a446-41b9-bdef-b2a8a870378f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3500206172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.3500206172
Directory	/workspace/2.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/2.adc_ctrl_filters_interrupt.2822573465
Short name	T334
Test name
Test status
Simulation time	335179267953 ps
CPU time	199.87 seconds
Started	Jan 03 01:15:01 PM PST 24
Finished	Jan 03 01:19:25 PM PST 24
Peak memory	200844 kb
Host	smart-7e4941f1-a017-43cc-aca2-73f0fdcd964c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2822573465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.2822573465
Directory	/workspace/2.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.398414431
Short name	T652
Test name
Test status
Simulation time	325492694685 ps
CPU time	395.88 seconds
Started	Jan 03 01:14:32 PM PST 24
Finished	Jan 03 01:21:47 PM PST 24
Peak memory	200892 kb
Host	smart-90ce1754-50e1-4163-9c96-547eca15b870
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=398414431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt _fixed.398414431
Directory	/workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/2.adc_ctrl_filters_polled.958571741
Short name	T113
Test name
Test status
Simulation time	489771536633 ps
CPU time	1051.71 seconds
Started	Jan 03 01:15:04 PM PST 24
Finished	Jan 03 01:33:40 PM PST 24
Peak memory	200820 kb
Host	smart-4f50319e-c576-460c-81cf-8a33e3407814
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=958571741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.958571741
Directory	/workspace/2.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.2188075178
Short name	T413
Test name
Test status
Simulation time	167831621762 ps
CPU time	369.98 seconds
Started	Jan 03 01:15:07 PM PST 24
Finished	Jan 03 01:22:21 PM PST 24
Peak memory	200796 kb
Host	smart-1733a3b7-fe9b-416e-a24a-ab09b86d78c9
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188075178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe d.2188075178
Directory	/workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.265703457
Short name	T623
Test name
Test status
Simulation time	322456937939 ps
CPU time	747.8 seconds
Started	Jan 03 01:15:00 PM PST 24
Finished	Jan 03 01:28:32 PM PST 24
Peak memory	200836 kb
Host	smart-320fc7b3-e76e-4ba2-a7ad-fe96a685e1a7
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265703457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ =adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.a dc_ctrl_filters_wakeup_fixed.265703457
Directory	/workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/2.adc_ctrl_fsm_reset.652701235
Short name	T552
Test name
Test status
Simulation time	69899816952 ps
CPU time	259.27 seconds
Started	Jan 03 01:14:44 PM PST 24
Finished	Jan 03 01:19:56 PM PST 24
Peak memory	201352 kb
Host	smart-68db99bd-3b71-48cd-b5e3-08a5c8a3b28d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=652701235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.652701235
Directory	/workspace/2.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/2.adc_ctrl_lowpower_counter.762778259
Short name	T403
Test name
Test status
Simulation time	37828033487 ps
CPU time	84.49 seconds
Started	Jan 03 01:14:43 PM PST 24
Finished	Jan 03 01:17:01 PM PST 24
Peak memory	200756 kb
Host	smart-3c9c3491-2723-439d-b33d-7fe1b8c2065b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=762778259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.762778259
Directory	/workspace/2.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/2.adc_ctrl_poweron_counter.1534433011
Short name	T659
Test name
Test status
Simulation time	4083910435 ps
CPU time	2.9 seconds
Started	Jan 03 01:14:43 PM PST 24
Finished	Jan 03 01:15:39 PM PST 24
Peak memory	200752 kb
Host	smart-fb426367-97cc-4006-b693-b9b401702b72
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1534433011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.1534433011
Directory	/workspace/2.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/2.adc_ctrl_sec_cm.3808707004
Short name	T49
Test name
Test status
Simulation time	8088920913 ps
CPU time	20.01 seconds
Started	Jan 03 01:14:33 PM PST 24
Finished	Jan 03 01:15:34 PM PST 24
Peak memory	216100 kb
Host	smart-4eb2c756-129d-4c4a-80af-680a4a3646d9
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808707004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.3808707004
Directory	/workspace/2.adc_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/2.adc_ctrl_smoke.3232564158
Short name	T797
Test name
Test status
Simulation time	5748518355 ps
CPU time	3.63 seconds
Started	Jan 03 01:15:08 PM PST 24
Finished	Jan 03 01:16:17 PM PST 24
Peak memory	200692 kb
Host	smart-dbb0754f-3d59-4cf1-aa0d-e09fd4f657ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3232564158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.3232564158
Directory	/workspace/2.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/2.adc_ctrl_stress_all.2791581608
Short name	T21
Test name
Test status
Simulation time	366728525096 ps
CPU time	906.14 seconds
Started	Jan 03 01:14:35 PM PST 24
Finished	Jan 03 01:30:24 PM PST 24
Peak memory	200824 kb
Host	smart-9de3708e-52bd-42e8-b918-cb4c6480cbec
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791581608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all. 2791581608
Directory	/workspace/2.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.2644644344
Short name	T171
Test name
Test status
Simulation time	205028674924 ps
CPU time	134.52 seconds
Started	Jan 03 01:14:36 PM PST 24
Finished	Jan 03 01:17:36 PM PST 24
Peak memory	209096 kb
Host	smart-11d66a27-450c-4d89-9090-bec86976556d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644644344 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.2644644344
Directory	/workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/20.adc_ctrl_alert_test.1538708613
Short name	T472
Test name
Test status
Simulation time	510225124 ps
CPU time	1.26 seconds
Started	Jan 03 01:15:21 PM PST 24
Finished	Jan 03 01:16:30 PM PST 24
Peak memory	200676 kb
Host	smart-1c6ed7c4-c42a-4ff0-8862-effe6dea6004
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538708613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.1538708613
Directory	/workspace/20.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/20.adc_ctrl_filters_both.121225789
Short name	T223
Test name
Test status
Simulation time	329686290350 ps
CPU time	221.5 seconds
Started	Jan 03 01:15:15 PM PST 24
Finished	Jan 03 01:20:03 PM PST 24
Peak memory	200912 kb
Host	smart-a0f7fcd4-3560-4bd5-9de3-48e5fb6fd500
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=121225789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.121225789
Directory	/workspace/20.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/20.adc_ctrl_filters_interrupt.4027358954
Short name	T640
Test name
Test status
Simulation time	487846340103 ps
CPU time	1132.66 seconds
Started	Jan 03 01:15:47 PM PST 24
Finished	Jan 03 01:35:34 PM PST 24
Peak memory	200920 kb
Host	smart-28428328-281d-44df-aaad-a6e8e8e3c6a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4027358954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.4027358954
Directory	/workspace/20.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.4007804252
Short name	T728
Test name
Test status
Simulation time	327069669154 ps
CPU time	383.41 seconds
Started	Jan 03 01:15:48 PM PST 24
Finished	Jan 03 01:23:06 PM PST 24
Peak memory	200792 kb
Host	smart-3760836d-9421-4775-bf3d-8ebf110363c9
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007804252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru pt_fixed.4007804252
Directory	/workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/20.adc_ctrl_filters_polled.2606559386
Short name	T686
Test name
Test status
Simulation time	166747002602 ps
CPU time	200.38 seconds
Started	Jan 03 01:15:47 PM PST 24
Finished	Jan 03 01:20:01 PM PST 24
Peak memory	200864 kb
Host	smart-ae93b04a-e2c8-4533-a6f1-d27c5372bc0a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2606559386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.2606559386
Directory	/workspace/20.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.997776988
Short name	T159
Test name
Test status
Simulation time	498156970518 ps
CPU time	284.65 seconds
Started	Jan 03 01:15:46 PM PST 24
Finished	Jan 03 01:21:26 PM PST 24
Peak memory	200904 kb
Host	smart-dd3561bd-8ff5-4902-ae1e-75a22dc8bc31
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=997776988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fixe d.997776988
Directory	/workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/20.adc_ctrl_filters_wakeup.2818734666
Short name	T167
Test name
Test status
Simulation time	323079251613 ps
CPU time	203.89 seconds
Started	Jan 03 01:15:49 PM PST 24
Finished	Jan 03 01:20:06 PM PST 24
Peak memory	200940 kb
Host	smart-e3ad1171-9aab-461e-a2e6-da0017051dd4
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818734666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters _wakeup.2818734666
Directory	/workspace/20.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.829175925
Short name	T523
Test name
Test status
Simulation time	162044508655 ps
CPU time	30.85 seconds
Started	Jan 03 01:15:23 PM PST 24
Finished	Jan 03 01:17:03 PM PST 24
Peak memory	200916 kb
Host	smart-6c9be906-4cbe-4478-bf51-d39c74ded0cf
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829175925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ =adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20. adc_ctrl_filters_wakeup_fixed.829175925
Directory	/workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/20.adc_ctrl_fsm_reset.1861031369
Short name	T713
Test name
Test status
Simulation time	101260504897 ps
CPU time	473.75 seconds
Started	Jan 03 01:15:21 PM PST 24
Finished	Jan 03 01:24:22 PM PST 24
Peak memory	201372 kb
Host	smart-40f2fe60-237a-4030-8a84-bed568a589df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1861031369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.1861031369
Directory	/workspace/20.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/20.adc_ctrl_lowpower_counter.2077075489
Short name	T598
Test name
Test status
Simulation time	32741071989 ps
CPU time	10.49 seconds
Started	Jan 03 01:15:19 PM PST 24
Finished	Jan 03 01:16:37 PM PST 24
Peak memory	200756 kb
Host	smart-15acb125-56d6-4ee5-8e22-4feeb6e9f6d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2077075489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.2077075489
Directory	/workspace/20.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/20.adc_ctrl_poweron_counter.489531541
Short name	T433
Test name
Test status
Simulation time	5806630082 ps
CPU time	14.53 seconds
Started	Jan 03 01:15:17 PM PST 24
Finished	Jan 03 01:16:37 PM PST 24
Peak memory	200728 kb
Host	smart-5453540e-bc1c-489b-905f-aa4415ba3787
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=489531541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.489531541
Directory	/workspace/20.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/20.adc_ctrl_smoke.2766625724
Short name	T408
Test name
Test status
Simulation time	5972818631 ps
CPU time	4.32 seconds
Started	Jan 03 01:15:52 PM PST 24
Finished	Jan 03 01:16:47 PM PST 24
Peak memory	200704 kb
Host	smart-79224862-deb3-4055-b97c-5e60ffc711f6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2766625724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.2766625724
Directory	/workspace/20.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/20.adc_ctrl_stress_all.708965579
Short name	T714
Test name
Test status
Simulation time	265783350747 ps
CPU time	431.81 seconds
Started	Jan 03 01:15:18 PM PST 24
Finished	Jan 03 01:23:35 PM PST 24
Peak memory	200892 kb
Host	smart-485a75ba-d781-4b36-9989-cf352033a88b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708965579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all. 708965579
Directory	/workspace/20.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.1925223875
Short name	T783
Test name
Test status
Simulation time	81794824106 ps
CPU time	82.14 seconds
Started	Jan 03 01:15:23 PM PST 24
Finished	Jan 03 01:17:52 PM PST 24
Peak memory	209536 kb
Host	smart-222a7566-104c-45b5-a57a-01d900faf615
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925223875 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.1925223875
Directory	/workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/21.adc_ctrl_alert_test.4067119421
Short name	T620
Test name
Test status
Simulation time	337286405 ps
CPU time	0.97 seconds
Started	Jan 03 01:15:43 PM PST 24
Finished	Jan 03 01:16:41 PM PST 24
Peak memory	200664 kb
Host	smart-9ef7586a-aedf-4824-9b83-acb4693b07e4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067119421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.4067119421
Directory	/workspace/21.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/21.adc_ctrl_clock_gating.1618691113
Short name	T141
Test name
Test status
Simulation time	344509811770 ps
CPU time	59.33 seconds
Started	Jan 03 01:15:24 PM PST 24
Finished	Jan 03 01:17:28 PM PST 24
Peak memory	200864 kb
Host	smart-62e1a3a1-df10-438c-9c71-b5c1700924a3
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618691113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat ing.1618691113
Directory	/workspace/21.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/21.adc_ctrl_filters_interrupt.4137471413
Short name	T173
Test name
Test status
Simulation time	326408638083 ps
CPU time	185.07 seconds
Started	Jan 03 01:15:23 PM PST 24
Finished	Jan 03 01:19:35 PM PST 24
Peak memory	200948 kb
Host	smart-15915300-a8ff-49fa-8ae8-bfd1dfc12d63
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4137471413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.4137471413
Directory	/workspace/21.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.2889581810
Short name	T438
Test name
Test status
Simulation time	164962404085 ps
CPU time	192.61 seconds
Started	Jan 03 01:15:20 PM PST 24
Finished	Jan 03 01:19:38 PM PST 24
Peak memory	200784 kb
Host	smart-00bfbb6e-e90c-4226-9740-f6eebf5129fc
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889581810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru pt_fixed.2889581810
Directory	/workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/21.adc_ctrl_filters_polled.2425257280
Short name	T168
Test name
Test status
Simulation time	495390729504 ps
CPU time	85.22 seconds
Started	Jan 03 01:15:21 PM PST 24
Finished	Jan 03 01:17:51 PM PST 24
Peak memory	200972 kb
Host	smart-c60f04b8-0e54-423a-b096-241455884b83
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2425257280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.2425257280
Directory	/workspace/21.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.2012820052
Short name	T792
Test name
Test status
Simulation time	165942933954 ps
CPU time	108.13 seconds
Started	Jan 03 01:15:23 PM PST 24
Finished	Jan 03 01:18:18 PM PST 24
Peak memory	200868 kb
Host	smart-62142d4c-eed3-4bb3-ac9d-288ce8c5e646
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012820052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix ed.2012820052
Directory	/workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/21.adc_ctrl_filters_wakeup.95001080
Short name	T177
Test name
Test status
Simulation time	177632786868 ps
CPU time	113.69 seconds
Started	Jan 03 01:15:22 PM PST 24
Finished	Jan 03 01:18:23 PM PST 24
Peak memory	200928 kb
Host	smart-6d21b9bc-dc63-4df6-9c7d-cde0694a1024
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95001080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_ wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_w akeup.95001080
Directory	/workspace/21.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.3074835397
Short name	T416
Test name
Test status
Simulation time	160819906066 ps
CPU time	133.98 seconds
Started	Jan 03 01:15:23 PM PST 24
Finished	Jan 03 01:18:44 PM PST 24
Peak memory	200880 kb
Host	smart-aa21ff61-c1f6-497b-a28b-436d06a9ba3e
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074835397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21 .adc_ctrl_filters_wakeup_fixed.3074835397
Directory	/workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/21.adc_ctrl_fsm_reset.2410949769
Short name	T718
Test name
Test status
Simulation time	100672581372 ps
CPU time	612.55 seconds
Started	Jan 03 01:15:23 PM PST 24
Finished	Jan 03 01:26:42 PM PST 24
Peak memory	201320 kb
Host	smart-a02c1d81-4bb1-4310-9728-e33aaf6fc57d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2410949769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.2410949769
Directory	/workspace/21.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/21.adc_ctrl_lowpower_counter.4066857069
Short name	T489
Test name
Test status
Simulation time	42183622839 ps
CPU time	22.9 seconds
Started	Jan 03 01:15:20 PM PST 24
Finished	Jan 03 01:16:49 PM PST 24
Peak memory	200704 kb
Host	smart-38eb9df3-f3d9-4ca6-b6b5-305f5c6a908d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4066857069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.4066857069
Directory	/workspace/21.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/21.adc_ctrl_poweron_counter.2978161984
Short name	T800
Test name
Test status
Simulation time	3364524095 ps
CPU time	2.72 seconds
Started	Jan 03 01:15:24 PM PST 24
Finished	Jan 03 01:16:32 PM PST 24
Peak memory	200716 kb
Host	smart-34d81728-b4d4-450b-be6a-7893b45ae0d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2978161984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.2978161984
Directory	/workspace/21.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/21.adc_ctrl_smoke.1054805406
Short name	T437
Test name
Test status
Simulation time	6184177513 ps
CPU time	16.77 seconds
Started	Jan 03 01:15:28 PM PST 24
Finished	Jan 03 01:16:48 PM PST 24
Peak memory	200732 kb
Host	smart-ab51ea40-072e-45e2-b0fb-6e74a3b07235
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1054805406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.1054805406
Directory	/workspace/21.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/21.adc_ctrl_stress_all.542166930
Short name	T176
Test name
Test status
Simulation time	334954187432 ps
CPU time	800.36 seconds
Started	Jan 03 01:15:46 PM PST 24
Finished	Jan 03 01:30:01 PM PST 24
Peak memory	200964 kb
Host	smart-9a481216-2824-4ff0-9935-9619712a32ae
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542166930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all. 542166930
Directory	/workspace/21.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.4242730922
Short name	T764
Test name
Test status
Simulation time	278453436062 ps
CPU time	60.69 seconds
Started	Jan 03 01:15:48 PM PST 24
Finished	Jan 03 01:17:43 PM PST 24
Peak memory	209572 kb
Host	smart-34e58866-4310-46b0-9a57-e61feead211f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242730922 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.4242730922
Directory	/workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/22.adc_ctrl_alert_test.2133172163
Short name	T469
Test name
Test status
Simulation time	540488850 ps
CPU time	1.22 seconds
Started	Jan 03 01:15:50 PM PST 24
Finished	Jan 03 01:16:44 PM PST 24
Peak memory	200664 kb
Host	smart-a9285906-3bfc-418b-b779-9c368572cb9e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133172163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.2133172163
Directory	/workspace/22.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/22.adc_ctrl_clock_gating.1933419571
Short name	T211
Test name
Test status
Simulation time	162313005385 ps
CPU time	258.64 seconds
Started	Jan 03 01:15:51 PM PST 24
Finished	Jan 03 01:21:02 PM PST 24
Peak memory	200904 kb
Host	smart-b9f12baa-feac-4999-b0c4-fd44e8542d37
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933419571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat ing.1933419571
Directory	/workspace/22.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/22.adc_ctrl_filters_interrupt.733552373
Short name	T310
Test name
Test status
Simulation time	322351940387 ps
CPU time	811.57 seconds
Started	Jan 03 01:15:48 PM PST 24
Finished	Jan 03 01:30:14 PM PST 24
Peak memory	201020 kb
Host	smart-4079b51b-1e35-4d73-a15a-0690af50304d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=733552373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.733552373
Directory	/workspace/22.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.3369014426
Short name	T136
Test name
Test status
Simulation time	485681315555 ps
CPU time	1186.69 seconds
Started	Jan 03 01:15:47 PM PST 24
Finished	Jan 03 01:36:28 PM PST 24
Peak memory	200808 kb
Host	smart-7bb2b521-2e17-496b-8964-3a62c92c2680
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369014426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru pt_fixed.3369014426
Directory	/workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/22.adc_ctrl_filters_polled.2467009210
Short name	T500
Test name
Test status
Simulation time	159224855964 ps
CPU time	61.15 seconds
Started	Jan 03 01:15:50 PM PST 24
Finished	Jan 03 01:17:45 PM PST 24
Peak memory	200860 kb
Host	smart-061371e8-09e8-4b05-8faf-f657b1776d48
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2467009210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.2467009210
Directory	/workspace/22.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.2311618575
Short name	T690
Test name
Test status
Simulation time	165835265002 ps
CPU time	102.5 seconds
Started	Jan 03 01:15:52 PM PST 24
Finished	Jan 03 01:18:25 PM PST 24
Peak memory	200960 kb
Host	smart-a3f1f63d-01b1-44f2-86d8-8493a3de53f7
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311618575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix ed.2311618575
Directory	/workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.4100763952
Short name	T578
Test name
Test status
Simulation time	497225201182 ps
CPU time	298.25 seconds
Started	Jan 03 01:15:48 PM PST 24
Finished	Jan 03 01:21:40 PM PST 24
Peak memory	200860 kb
Host	smart-cd3d7d03-d7dc-4459-993b-77f9d8bf28b5
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100763952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22 .adc_ctrl_filters_wakeup_fixed.4100763952
Directory	/workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/22.adc_ctrl_fsm_reset.2686824538
Short name	T193
Test name
Test status
Simulation time	78833126941 ps
CPU time	280.2 seconds
Started	Jan 03 01:15:40 PM PST 24
Finished	Jan 03 01:21:18 PM PST 24
Peak memory	201328 kb
Host	smart-1b7e572f-7a0f-48d1-9cd7-e14041b2e34f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2686824538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.2686824538
Directory	/workspace/22.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/22.adc_ctrl_lowpower_counter.3541145557
Short name	T540
Test name
Test status
Simulation time	33466371471 ps
CPU time	8.92 seconds
Started	Jan 03 01:15:48 PM PST 24
Finished	Jan 03 01:16:51 PM PST 24
Peak memory	200668 kb
Host	smart-2c61e6a7-5e11-4788-a09e-30ec06e55a9d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3541145557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.3541145557
Directory	/workspace/22.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/22.adc_ctrl_poweron_counter.1700950866
Short name	T776
Test name
Test status
Simulation time	5084720380 ps
CPU time	3.39 seconds
Started	Jan 03 01:15:50 PM PST 24
Finished	Jan 03 01:16:47 PM PST 24
Peak memory	200724 kb
Host	smart-f6fbe425-12e7-4c5e-88dc-585607d153ec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1700950866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.1700950866
Directory	/workspace/22.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/22.adc_ctrl_smoke.3631481796
Short name	T695
Test name
Test status
Simulation time	5788612876 ps
CPU time	7.79 seconds
Started	Jan 03 01:15:46 PM PST 24
Finished	Jan 03 01:16:48 PM PST 24
Peak memory	200720 kb
Host	smart-cc254860-3e65-4613-8171-be9f6ca25063
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3631481796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.3631481796
Directory	/workspace/22.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.686324181
Short name	T226
Test name
Test status
Simulation time	51726682251 ps
CPU time	127.86 seconds
Started	Jan 03 01:15:45 PM PST 24
Finished	Jan 03 01:18:49 PM PST 24
Peak memory	201088 kb
Host	smart-735a227d-f7b6-4521-a338-a85b6427bcd4
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686324181 -assert nopo stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.686324181
Directory	/workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/23.adc_ctrl_alert_test.1573216540
Short name	T827
Test name
Test status
Simulation time	395513379 ps
CPU time	0.85 seconds
Started	Jan 03 01:17:21 PM PST 24
Finished	Jan 03 01:17:25 PM PST 24
Peak memory	200676 kb
Host	smart-fecb84eb-60b5-4999-bdee-49cfdf04f4a3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573216540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.1573216540
Directory	/workspace/23.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/23.adc_ctrl_clock_gating.194951233
Short name	T288
Test name
Test status
Simulation time	334813917833 ps
CPU time	228.39 seconds
Started	Jan 03 01:15:47 PM PST 24
Finished	Jan 03 01:20:33 PM PST 24
Peak memory	200856 kb
Host	smart-3dd497f1-a3f5-4d21-aef5-b0c4d3c52eb9
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194951233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gati ng.194951233
Directory	/workspace/23.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/23.adc_ctrl_filters_both.1649696386
Short name	T592
Test name
Test status
Simulation time	330753727315 ps
CPU time	153.75 seconds
Started	Jan 03 01:15:49 PM PST 24
Finished	Jan 03 01:19:16 PM PST 24
Peak memory	200956 kb
Host	smart-3f3916d3-a687-430c-b1ef-ca35a08ef67e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1649696386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.1649696386
Directory	/workspace/23.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/23.adc_ctrl_filters_interrupt.3995571434
Short name	T337
Test name
Test status
Simulation time	501725898121 ps
CPU time	1160.07 seconds
Started	Jan 03 01:15:49 PM PST 24
Finished	Jan 03 01:36:02 PM PST 24
Peak memory	200936 kb
Host	smart-fefd77b0-59e9-4dce-8c73-2880b6a01cda
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3995571434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.3995571434
Directory	/workspace/23.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.1172812361
Short name	T654
Test name
Test status
Simulation time	489341796219 ps
CPU time	163.59 seconds
Started	Jan 03 01:15:44 PM PST 24
Finished	Jan 03 01:19:24 PM PST 24
Peak memory	200832 kb
Host	smart-a68a2828-0431-41ab-9c79-eb5bee79eec9
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172812361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru pt_fixed.1172812361
Directory	/workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.1879152724
Short name	T610
Test name
Test status
Simulation time	329845679939 ps
CPU time	191.09 seconds
Started	Jan 03 01:15:51 PM PST 24
Finished	Jan 03 01:19:54 PM PST 24
Peak memory	200868 kb
Host	smart-2ede02f3-8289-4ef2-af3d-3c26576ced23
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879152724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix ed.1879152724
Directory	/workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/23.adc_ctrl_filters_wakeup.714277825
Short name	T266
Test name
Test status
Simulation time	165260388357 ps
CPU time	367.43 seconds
Started	Jan 03 01:15:39 PM PST 24
Finished	Jan 03 01:22:45 PM PST 24
Peak memory	200916 kb
Host	smart-17283738-fe65-4df8-8f1c-938c70c1d4c3
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714277825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters _wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_ wakeup.714277825
Directory	/workspace/23.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.3164916598
Short name	T795
Test name
Test status
Simulation time	332377218974 ps
CPU time	193.46 seconds
Started	Jan 03 01:15:47 PM PST 24
Finished	Jan 03 01:19:55 PM PST 24
Peak memory	200832 kb
Host	smart-b95bfe41-22f6-422c-bd28-cc3d24545e1b
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164916598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23 .adc_ctrl_filters_wakeup_fixed.3164916598
Directory	/workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/23.adc_ctrl_fsm_reset.146397128
Short name	T740
Test name
Test status
Simulation time	118303749412 ps
CPU time	466.59 seconds
Started	Jan 03 01:15:50 PM PST 24
Finished	Jan 03 01:24:31 PM PST 24
Peak memory	201420 kb
Host	smart-b95de611-439c-4471-822c-e0e4256bf5de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=146397128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.146397128
Directory	/workspace/23.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/23.adc_ctrl_lowpower_counter.744004369
Short name	T715
Test name
Test status
Simulation time	42228851753 ps
CPU time	91.51 seconds
Started	Jan 03 01:15:48 PM PST 24
Finished	Jan 03 01:18:14 PM PST 24
Peak memory	200692 kb
Host	smart-5e1abc41-155f-41b9-8de5-cdeb92c909a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=744004369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.744004369
Directory	/workspace/23.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/23.adc_ctrl_poweron_counter.1641551210
Short name	T418
Test name
Test status
Simulation time	3916368733 ps
CPU time	2.95 seconds
Started	Jan 03 01:15:46 PM PST 24
Finished	Jan 03 01:16:44 PM PST 24
Peak memory	200736 kb
Host	smart-a7de3225-33cf-4a05-9709-493b7ad52bb7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1641551210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.1641551210
Directory	/workspace/23.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/23.adc_ctrl_smoke.69342188
Short name	T846
Test name
Test status
Simulation time	5576554366 ps
CPU time	8.07 seconds
Started	Jan 03 01:15:45 PM PST 24
Finished	Jan 03 01:16:49 PM PST 24
Peak memory	200664 kb
Host	smart-7e8d4212-4069-4279-94b4-80ed55327aa0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=69342188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.69342188
Directory	/workspace/23.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/24.adc_ctrl_alert_test.3059057340
Short name	T812
Test name
Test status
Simulation time	407012003 ps
CPU time	0.88 seconds
Started	Jan 03 01:16:31 PM PST 24
Finished	Jan 03 01:16:56 PM PST 24
Peak memory	200672 kb
Host	smart-8506f078-31ac-442d-8e12-f3f6091983fb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059057340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.3059057340
Directory	/workspace/24.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/24.adc_ctrl_clock_gating.1195465081
Short name	T687
Test name
Test status
Simulation time	168164122488 ps
CPU time	99.92 seconds
Started	Jan 03 01:17:33 PM PST 24
Finished	Jan 03 01:19:17 PM PST 24
Peak memory	200832 kb
Host	smart-5067c206-98a2-441c-aa48-6d67ea2315e1
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195465081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat ing.1195465081
Directory	/workspace/24.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.3262792672
Short name	T458
Test name
Test status
Simulation time	494469012057 ps
CPU time	595.25 seconds
Started	Jan 03 01:17:30 PM PST 24
Finished	Jan 03 01:27:30 PM PST 24
Peak memory	200952 kb
Host	smart-3768ba69-216f-426b-9fb9-764402b82674
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262792672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru pt_fixed.3262792672
Directory	/workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/24.adc_ctrl_filters_polled.293406305
Short name	T149
Test name
Test status
Simulation time	490675818034 ps
CPU time	1120.8 seconds
Started	Jan 03 01:17:16 PM PST 24
Finished	Jan 03 01:36:00 PM PST 24
Peak memory	200884 kb
Host	smart-3f081774-44c7-445e-ae02-1c64591d2aa8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=293406305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.293406305
Directory	/workspace/24.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.1470925425
Short name	T670
Test name
Test status
Simulation time	491090476246 ps
CPU time	282.32 seconds
Started	Jan 03 01:17:30 PM PST 24
Finished	Jan 03 01:22:17 PM PST 24
Peak memory	200808 kb
Host	smart-cc09c9f2-8f8c-48ef-ac2e-2d712722a61e
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470925425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix ed.1470925425
Directory	/workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/24.adc_ctrl_filters_wakeup.1118367723
Short name	T122
Test name
Test status
Simulation time	178902466519 ps
CPU time	398.57 seconds
Started	Jan 03 01:16:03 PM PST 24
Finished	Jan 03 01:23:25 PM PST 24
Peak memory	200792 kb
Host	smart-93dd6198-cc82-4468-9c3e-31e678bf487c
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118367723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters _wakeup.1118367723
Directory	/workspace/24.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.360843741
Short name	T781
Test name
Test status
Simulation time	161238412294 ps
CPU time	338.54 seconds
Started	Jan 03 01:16:20 PM PST 24
Finished	Jan 03 01:22:30 PM PST 24
Peak memory	200952 kb
Host	smart-0313ddd0-d20d-41c5-bd6f-c4716168c5a5
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360843741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ =adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24. adc_ctrl_filters_wakeup_fixed.360843741
Directory	/workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/24.adc_ctrl_fsm_reset.1619784805
Short name	T755
Test name
Test status
Simulation time	114928551550 ps
CPU time	596.04 seconds
Started	Jan 03 01:16:24 PM PST 24
Finished	Jan 03 01:26:49 PM PST 24
Peak memory	201276 kb
Host	smart-7cbcbfe1-898e-4498-a27e-5674356676b7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1619784805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.1619784805
Directory	/workspace/24.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/24.adc_ctrl_lowpower_counter.43080581
Short name	T494
Test name
Test status
Simulation time	29143905990 ps
CPU time	34.2 seconds
Started	Jan 03 01:16:20 PM PST 24
Finished	Jan 03 01:17:26 PM PST 24
Peak memory	200708 kb
Host	smart-9069e455-70ee-478b-813c-1cf96ec112df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=43080581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.43080581
Directory	/workspace/24.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/24.adc_ctrl_poweron_counter.2607936403
Short name	T817
Test name
Test status
Simulation time	3681507441 ps
CPU time	2.95 seconds
Started	Jan 03 01:17:41 PM PST 24
Finished	Jan 03 01:17:47 PM PST 24
Peak memory	200752 kb
Host	smart-3b1dbc32-20a9-4ccc-8c26-d445d937db4e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2607936403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.2607936403
Directory	/workspace/24.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/24.adc_ctrl_smoke.1538487759
Short name	T443
Test name
Test status
Simulation time	6039639353 ps
CPU time	3.01 seconds
Started	Jan 03 01:16:50 PM PST 24
Finished	Jan 03 01:17:06 PM PST 24
Peak memory	200656 kb
Host	smart-e4239a17-488b-486e-9d46-16f9e4f7a587
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1538487759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.1538487759
Directory	/workspace/24.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/24.adc_ctrl_stress_all.544053351
Short name	T648
Test name
Test status
Simulation time	207302097215 ps
CPU time	121.18 seconds
Started	Jan 03 01:16:07 PM PST 24
Finished	Jan 03 01:18:49 PM PST 24
Peak memory	200924 kb
Host	smart-47632839-7807-4cb2-97a0-923e52436b6f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544053351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all. 544053351
Directory	/workspace/24.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.720028243
Short name	T135
Test name
Test status
Simulation time	30357705147 ps
CPU time	19.25 seconds
Started	Jan 03 01:16:23 PM PST 24
Finished	Jan 03 01:17:12 PM PST 24
Peak memory	200960 kb
Host	smart-29ddd19f-6624-4077-bc34-d6e24005abca
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720028243 -assert nopo stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.720028243
Directory	/workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/25.adc_ctrl_alert_test.960671324
Short name	T594
Test name
Test status
Simulation time	451110410 ps
CPU time	1.16 seconds
Started	Jan 03 01:17:28 PM PST 24
Finished	Jan 03 01:17:33 PM PST 24
Peak memory	200640 kb
Host	smart-b085b803-2305-4d77-aada-e3991fd959cc
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960671324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.960671324
Directory	/workspace/25.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/25.adc_ctrl_filters_both.3811968098
Short name	T339
Test name
Test status
Simulation time	503493193190 ps
CPU time	642.12 seconds
Started	Jan 03 01:17:05 PM PST 24
Finished	Jan 03 01:27:51 PM PST 24
Peak memory	200804 kb
Host	smart-2c7cce29-fbeb-4965-bf67-968571e39ab3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3811968098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.3811968098
Directory	/workspace/25.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/25.adc_ctrl_filters_interrupt.505690580
Short name	T155
Test name
Test status
Simulation time	322793596461 ps
CPU time	189.33 seconds
Started	Jan 03 01:16:32 PM PST 24
Finished	Jan 03 01:20:05 PM PST 24
Peak memory	201012 kb
Host	smart-50447cac-3967-4559-94e4-d4d2e03d0c2c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=505690580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.505690580
Directory	/workspace/25.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.1769222507
Short name	T566
Test name
Test status
Simulation time	162428542053 ps
CPU time	192.87 seconds
Started	Jan 03 01:16:47 PM PST 24
Finished	Jan 03 01:20:14 PM PST 24
Peak memory	200844 kb
Host	smart-b10926af-f983-4d3a-a713-40e7affefcde
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769222507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru pt_fixed.1769222507
Directory	/workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/25.adc_ctrl_filters_polled.4006360684
Short name	T689
Test name
Test status
Simulation time	169104231965 ps
CPU time	267.24 seconds
Started	Jan 03 01:16:32 PM PST 24
Finished	Jan 03 01:21:23 PM PST 24
Peak memory	200892 kb
Host	smart-4f0b833f-eb19-4af8-b523-325b5bfb12ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4006360684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.4006360684
Directory	/workspace/25.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.1757950820
Short name	T785
Test name
Test status
Simulation time	162230915444 ps
CPU time	364.89 seconds
Started	Jan 03 01:16:47 PM PST 24
Finished	Jan 03 01:23:06 PM PST 24
Peak memory	200872 kb
Host	smart-19c6b2e9-058b-457f-8ec0-e362f26ec5f6
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757950820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix ed.1757950820
Directory	/workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/25.adc_ctrl_filters_wakeup.713318314
Short name	T711
Test name
Test status
Simulation time	499039249255 ps
CPU time	316.39 seconds
Started	Jan 03 01:16:48 PM PST 24
Finished	Jan 03 01:22:18 PM PST 24
Peak memory	200936 kb
Host	smart-5ba3d6a7-6971-41f3-9b5c-0483b4d18bcd
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713318314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters _wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_ wakeup.713318314
Directory	/workspace/25.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.2077987270
Short name	T549
Test name
Test status
Simulation time	488183073856 ps
CPU time	224.38 seconds
Started	Jan 03 01:17:04 PM PST 24
Finished	Jan 03 01:20:52 PM PST 24
Peak memory	200884 kb
Host	smart-c8fca0c6-7a6c-47ae-837d-d3d46053db03
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077987270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25 .adc_ctrl_filters_wakeup_fixed.2077987270
Directory	/workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/25.adc_ctrl_fsm_reset.2970831356
Short name	T601
Test name
Test status
Simulation time	86937262916 ps
CPU time	499.68 seconds
Started	Jan 03 01:17:25 PM PST 24
Finished	Jan 03 01:25:48 PM PST 24
Peak memory	201248 kb
Host	smart-bfe08e0c-2758-4df0-b6fd-005a7849d7c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2970831356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.2970831356
Directory	/workspace/25.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/25.adc_ctrl_lowpower_counter.814108467
Short name	T574
Test name
Test status
Simulation time	43132418756 ps
CPU time	41.11 seconds
Started	Jan 03 01:16:25 PM PST 24
Finished	Jan 03 01:17:34 PM PST 24
Peak memory	200696 kb
Host	smart-a9204c50-85d0-447d-b4b4-c7a1d231b7bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=814108467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.814108467
Directory	/workspace/25.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/25.adc_ctrl_poweron_counter.715273909
Short name	T735
Test name
Test status
Simulation time	4657444360 ps
CPU time	12.03 seconds
Started	Jan 03 01:17:00 PM PST 24
Finished	Jan 03 01:17:20 PM PST 24
Peak memory	200752 kb
Host	smart-7e65078b-bb09-442c-ba66-71c897f1f4a8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=715273909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.715273909
Directory	/workspace/25.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/25.adc_ctrl_smoke.2071526768
Short name	T52
Test name
Test status
Simulation time	6163486971 ps
CPU time	1.58 seconds
Started	Jan 03 01:16:21 PM PST 24
Finished	Jan 03 01:16:54 PM PST 24
Peak memory	200732 kb
Host	smart-9628d390-9864-4dc9-b1d3-a661177505c4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2071526768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.2071526768
Directory	/workspace/25.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/26.adc_ctrl_alert_test.800685263
Short name	T684
Test name
Test status
Simulation time	412035221 ps
CPU time	1.63 seconds
Started	Jan 03 01:17:43 PM PST 24
Finished	Jan 03 01:17:49 PM PST 24
Peak memory	200672 kb
Host	smart-ed551a60-6074-4e78-9a76-3f7eba002db9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800685263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.800685263
Directory	/workspace/26.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/26.adc_ctrl_clock_gating.2756150963
Short name	T646
Test name
Test status
Simulation time	163936483879 ps
CPU time	107.3 seconds
Started	Jan 03 01:17:40 PM PST 24
Finished	Jan 03 01:19:31 PM PST 24
Peak memory	200844 kb
Host	smart-2280cc5e-6b89-4de9-918f-9f86f7b3f2e2
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756150963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat ing.2756150963
Directory	/workspace/26.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/26.adc_ctrl_filters_both.3916413548
Short name	T55
Test name
Test status
Simulation time	162688481903 ps
CPU time	363.43 seconds
Started	Jan 03 01:17:35 PM PST 24
Finished	Jan 03 01:23:43 PM PST 24
Peak memory	200948 kb
Host	smart-bf9699e2-df71-4206-b2ef-bcd5a2a28d04
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3916413548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.3916413548
Directory	/workspace/26.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/26.adc_ctrl_filters_interrupt.4182372632
Short name	T152
Test name
Test status
Simulation time	321559296854 ps
CPU time	175.74 seconds
Started	Jan 03 01:17:33 PM PST 24
Finished	Jan 03 01:20:33 PM PST 24
Peak memory	200900 kb
Host	smart-7be5ec32-52ea-42a8-ab27-c71e42d1e00a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4182372632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.4182372632
Directory	/workspace/26.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.3381946729
Short name	T597
Test name
Test status
Simulation time	334551122470 ps
CPU time	804.84 seconds
Started	Jan 03 01:17:46 PM PST 24
Finished	Jan 03 01:31:16 PM PST 24
Peak memory	200828 kb
Host	smart-1ac67536-225c-4e71-a271-3f884c24fd04
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381946729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru pt_fixed.3381946729
Directory	/workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/26.adc_ctrl_filters_polled.730105405
Short name	T462
Test name
Test status
Simulation time	166588617696 ps
CPU time	382.47 seconds
Started	Jan 03 01:17:35 PM PST 24
Finished	Jan 03 01:24:01 PM PST 24
Peak memory	200884 kb
Host	smart-a55cab6f-2b51-4e7c-9526-efe59250b758
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=730105405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.730105405
Directory	/workspace/26.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.837396933
Short name	T117
Test name
Test status
Simulation time	490997551694 ps
CPU time	267.39 seconds
Started	Jan 03 01:17:32 PM PST 24
Finished	Jan 03 01:22:03 PM PST 24
Peak memory	200864 kb
Host	smart-a9ad71b4-f570-470f-8a6d-1225c67507b8
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=837396933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fixe d.837396933
Directory	/workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/26.adc_ctrl_filters_wakeup.190042999
Short name	T123
Test name
Test status
Simulation time	161819626907 ps
CPU time	404.73 seconds
Started	Jan 03 01:17:52 PM PST 24
Finished	Jan 03 01:24:56 PM PST 24
Peak memory	200988 kb
Host	smart-6410aef4-464a-47c3-9b55-d71240700506
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190042999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters _wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_ wakeup.190042999
Directory	/workspace/26.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.781567153
Short name	T843
Test name
Test status
Simulation time	336120939741 ps
CPU time	190.5 seconds
Started	Jan 03 01:17:41 PM PST 24
Finished	Jan 03 01:20:54 PM PST 24
Peak memory	200860 kb
Host	smart-8180a3dd-1f33-48f0-bd9f-a9b113741203
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781567153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ =adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26. adc_ctrl_filters_wakeup_fixed.781567153
Directory	/workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/26.adc_ctrl_fsm_reset.4148790613
Short name	T565
Test name
Test status
Simulation time	66977082528 ps
CPU time	230.23 seconds
Started	Jan 03 01:17:58 PM PST 24
Finished	Jan 03 01:22:02 PM PST 24
Peak memory	201416 kb
Host	smart-cd9d3e05-ea1e-47e1-b492-673fdd7379a1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4148790613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.4148790613
Directory	/workspace/26.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/26.adc_ctrl_lowpower_counter.659908779
Short name	T683
Test name
Test status
Simulation time	31465792896 ps
CPU time	71.94 seconds
Started	Jan 03 01:17:40 PM PST 24
Finished	Jan 03 01:18:55 PM PST 24
Peak memory	200720 kb
Host	smart-01662ffc-2387-43f2-a0f3-e430ec60fc49
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=659908779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.659908779
Directory	/workspace/26.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/26.adc_ctrl_poweron_counter.1290429393
Short name	T804
Test name
Test status
Simulation time	5561159813 ps
CPU time	9.22 seconds
Started	Jan 03 01:17:45 PM PST 24
Finished	Jan 03 01:18:00 PM PST 24
Peak memory	200716 kb
Host	smart-2a99c344-88bb-4bea-8e08-60ceed6ffb8b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1290429393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.1290429393
Directory	/workspace/26.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/26.adc_ctrl_smoke.1530993865
Short name	T685
Test name
Test status
Simulation time	5778344243 ps
CPU time	6.37 seconds
Started	Jan 03 01:17:34 PM PST 24
Finished	Jan 03 01:17:45 PM PST 24
Peak memory	200688 kb
Host	smart-738a795f-e6e8-4144-a141-b5a2522c02c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1530993865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.1530993865
Directory	/workspace/26.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.2730041815
Short name	T784
Test name
Test status
Simulation time	97161761265 ps
CPU time	210.74 seconds
Started	Jan 03 01:17:42 PM PST 24
Finished	Jan 03 01:21:15 PM PST 24
Peak memory	217112 kb
Host	smart-5a81205b-9f82-4ed3-ac04-cd2f982e3861
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730041815 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.2730041815
Directory	/workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/27.adc_ctrl_alert_test.2040106328
Short name	T484
Test name
Test status
Simulation time	300682497 ps
CPU time	0.79 seconds
Started	Jan 03 01:16:44 PM PST 24
Finished	Jan 03 01:17:01 PM PST 24
Peak memory	200660 kb
Host	smart-bc5355d7-1099-4a64-9ff0-93533a4f6a61
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040106328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.2040106328
Directory	/workspace/27.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/27.adc_ctrl_clock_gating.3864929647
Short name	T828
Test name
Test status
Simulation time	333874664622 ps
CPU time	756.88 seconds
Started	Jan 03 01:17:24 PM PST 24
Finished	Jan 03 01:30:04 PM PST 24
Peak memory	200976 kb
Host	smart-da1cea20-f671-498c-9770-4f011241317c
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864929647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat ing.3864929647
Directory	/workspace/27.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/27.adc_ctrl_filters_both.1938441299
Short name	T845
Test name
Test status
Simulation time	506536323919 ps
CPU time	1145 seconds
Started	Jan 03 01:16:46 PM PST 24
Finished	Jan 03 01:36:06 PM PST 24
Peak memory	200956 kb
Host	smart-6a517d02-c1fd-4c45-a377-b6277f41b098
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1938441299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.1938441299
Directory	/workspace/27.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.3390053178
Short name	T729
Test name
Test status
Simulation time	490292828593 ps
CPU time	1058.4 seconds
Started	Jan 03 01:17:25 PM PST 24
Finished	Jan 03 01:35:06 PM PST 24
Peak memory	200820 kb
Host	smart-55904eed-3b74-4a89-ad49-3e9d290e6a5f
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390053178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru pt_fixed.3390053178
Directory	/workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/27.adc_ctrl_filters_polled.494114183
Short name	T813
Test name
Test status
Simulation time	325913093500 ps
CPU time	419.07 seconds
Started	Jan 03 01:17:42 PM PST 24
Finished	Jan 03 01:24:43 PM PST 24
Peak memory	200816 kb
Host	smart-f1e0ed6c-ee77-470e-86eb-018c4017821c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=494114183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.494114183
Directory	/workspace/27.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.3848734655
Short name	T840
Test name
Test status
Simulation time	318164436230 ps
CPU time	199.19 seconds
Started	Jan 03 01:17:44 PM PST 24
Finished	Jan 03 01:21:07 PM PST 24
Peak memory	200860 kb
Host	smart-00ac6f2e-5b2a-4b1c-8f44-76c6fb48abcf
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848734655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix ed.3848734655
Directory	/workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/27.adc_ctrl_filters_wakeup.3151178127
Short name	T202
Test name
Test status
Simulation time	169411169729 ps
CPU time	194.74 seconds
Started	Jan 03 01:16:43 PM PST 24
Finished	Jan 03 01:20:14 PM PST 24
Peak memory	200908 kb
Host	smart-52855e8d-1ae5-4d4c-b7d9-a6699a2d4e93
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151178127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters _wakeup.3151178127
Directory	/workspace/27.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.405545102
Short name	T766
Test name
Test status
Simulation time	163065234222 ps
CPU time	199.39 seconds
Started	Jan 03 01:16:47 PM PST 24
Finished	Jan 03 01:20:20 PM PST 24
Peak memory	200828 kb
Host	smart-4e3e24b8-adf6-4b17-b992-5dba2bc3fa8f
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405545102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ =adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27. adc_ctrl_filters_wakeup_fixed.405545102
Directory	/workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/27.adc_ctrl_fsm_reset.1540897494
Short name	T637
Test name
Test status
Simulation time	106332772605 ps
CPU time	437.28 seconds
Started	Jan 03 01:16:46 PM PST 24
Finished	Jan 03 01:24:18 PM PST 24
Peak memory	201328 kb
Host	smart-d3c8a8e1-8817-46c1-8cd6-4b730afbb94b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1540897494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.1540897494
Directory	/workspace/27.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/27.adc_ctrl_lowpower_counter.1118868772
Short name	T775
Test name
Test status
Simulation time	23062678930 ps
CPU time	24.65 seconds
Started	Jan 03 01:17:23 PM PST 24
Finished	Jan 03 01:17:50 PM PST 24
Peak memory	200700 kb
Host	smart-5601de2a-4f6f-4c29-bc0e-15339c18d8d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1118868772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.1118868772
Directory	/workspace/27.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/27.adc_ctrl_poweron_counter.962097256
Short name	T724
Test name
Test status
Simulation time	5256086489 ps
CPU time	12.36 seconds
Started	Jan 03 01:17:23 PM PST 24
Finished	Jan 03 01:17:39 PM PST 24
Peak memory	200768 kb
Host	smart-8130a868-ffc7-4fed-a5b5-088fd7589d64
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=962097256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.962097256
Directory	/workspace/27.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/27.adc_ctrl_smoke.2139414711
Short name	T536
Test name
Test status
Simulation time	6120047291 ps
CPU time	13.92 seconds
Started	Jan 03 01:17:41 PM PST 24
Finished	Jan 03 01:17:58 PM PST 24
Peak memory	200620 kb
Host	smart-3e371e38-27b9-4ee8-9e5f-ba72abd31361
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2139414711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.2139414711
Directory	/workspace/27.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/27.adc_ctrl_stress_all.110425400
Short name	T811
Test name
Test status
Simulation time	357128068305 ps
CPU time	592.67 seconds
Started	Jan 03 01:16:45 PM PST 24
Finished	Jan 03 01:26:53 PM PST 24
Peak memory	210944 kb
Host	smart-0fa77dc2-297f-43e5-81ff-8f16c3dd17b4
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110425400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all. 110425400
Directory	/workspace/27.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.3223067684
Short name	T789
Test name
Test status
Simulation time	128708066075 ps
CPU time	74.26 seconds
Started	Jan 03 01:17:23 PM PST 24
Finished	Jan 03 01:18:40 PM PST 24
Peak memory	209728 kb
Host	smart-2c77f4c0-eaa2-438b-8b34-92d015ebe627
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223067684 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.3223067684
Directory	/workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/28.adc_ctrl_alert_test.1177068246
Short name	T616
Test name
Test status
Simulation time	478911453 ps
CPU time	0.81 seconds
Started	Jan 03 01:17:35 PM PST 24
Finished	Jan 03 01:17:40 PM PST 24
Peak memory	200648 kb
Host	smart-e8efd89b-3d9b-4b2f-b915-6a190b698e57
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177068246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.1177068246
Directory	/workspace/28.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/28.adc_ctrl_clock_gating.3050354015
Short name	T842
Test name
Test status
Simulation time	167371710947 ps
CPU time	190.98 seconds
Started	Jan 03 01:17:30 PM PST 24
Finished	Jan 03 01:20:44 PM PST 24
Peak memory	200960 kb
Host	smart-f8fbcedf-dfb4-4391-8259-c4259421c984
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050354015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat ing.3050354015
Directory	/workspace/28.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/28.adc_ctrl_filters_both.1825221778
Short name	T542
Test name
Test status
Simulation time	169939985982 ps
CPU time	100.76 seconds
Started	Jan 03 01:17:29 PM PST 24
Finished	Jan 03 01:19:12 PM PST 24
Peak memory	200996 kb
Host	smart-6cf797b7-9600-4a99-9182-270083308a55
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1825221778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.1825221778
Directory	/workspace/28.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/28.adc_ctrl_filters_interrupt.1301011537
Short name	T524
Test name
Test status
Simulation time	165698804675 ps
CPU time	127.8 seconds
Started	Jan 03 01:17:18 PM PST 24
Finished	Jan 03 01:19:29 PM PST 24
Peak memory	200900 kb
Host	smart-6337388d-90bb-4c44-8cf7-260a112c5631
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1301011537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.1301011537
Directory	/workspace/28.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.252422416
Short name	T516
Test name
Test status
Simulation time	321982585634 ps
CPU time	358.55 seconds
Started	Jan 03 01:17:26 PM PST 24
Finished	Jan 03 01:23:27 PM PST 24
Peak memory	200832 kb
Host	smart-ea7cbb7e-1242-464c-9ac6-18d923c38515
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=252422416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrup t_fixed.252422416
Directory	/workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/28.adc_ctrl_filters_polled.2764587677
Short name	T738
Test name
Test status
Simulation time	329794236133 ps
CPU time	735.9 seconds
Started	Jan 03 01:17:15 PM PST 24
Finished	Jan 03 01:29:35 PM PST 24
Peak memory	200896 kb
Host	smart-b2338fd6-8ccc-4439-a9fe-cc283484222c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2764587677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.2764587677
Directory	/workspace/28.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.694772311
Short name	T576
Test name
Test status
Simulation time	332544743590 ps
CPU time	766.37 seconds
Started	Jan 03 01:17:32 PM PST 24
Finished	Jan 03 01:30:23 PM PST 24
Peak memory	200832 kb
Host	smart-6d87eb20-994c-46f0-bfe1-b51ff7ff73b1
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=694772311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fixe d.694772311
Directory	/workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/28.adc_ctrl_filters_wakeup.3958755116
Short name	T295
Test name
Test status
Simulation time	165633809378 ps
CPU time	357.73 seconds
Started	Jan 03 01:17:40 PM PST 24
Finished	Jan 03 01:23:46 PM PST 24
Peak memory	200884 kb
Host	smart-64318be7-b4cc-4dce-8727-e462238c04d0
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958755116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters _wakeup.3958755116
Directory	/workspace/28.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.1670527244
Short name	T504
Test name
Test status
Simulation time	491413672337 ps
CPU time	1107.97 seconds
Started	Jan 03 01:17:28 PM PST 24
Finished	Jan 03 01:35:59 PM PST 24
Peak memory	200868 kb
Host	smart-ad0160dd-13ca-4771-a599-fde3ec79360e
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670527244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28 .adc_ctrl_filters_wakeup_fixed.1670527244
Directory	/workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/28.adc_ctrl_fsm_reset.2091205416
Short name	T678
Test name
Test status
Simulation time	132307546680 ps
CPU time	527.36 seconds
Started	Jan 03 01:17:32 PM PST 24
Finished	Jan 03 01:26:24 PM PST 24
Peak memory	201316 kb
Host	smart-7594e543-2d4f-4b72-bf1c-eb9c860013e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2091205416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.2091205416
Directory	/workspace/28.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/28.adc_ctrl_lowpower_counter.3144273177
Short name	T701
Test name
Test status
Simulation time	39593615042 ps
CPU time	93.74 seconds
Started	Jan 03 01:17:33 PM PST 24
Finished	Jan 03 01:19:11 PM PST 24
Peak memory	200760 kb
Host	smart-117482e6-773c-41ed-b37f-84ef6a7367f0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3144273177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.3144273177
Directory	/workspace/28.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/28.adc_ctrl_poweron_counter.744293297
Short name	T417
Test name
Test status
Simulation time	3789514092 ps
CPU time	1.56 seconds
Started	Jan 03 01:17:35 PM PST 24
Finished	Jan 03 01:17:45 PM PST 24
Peak memory	200680 kb
Host	smart-03f50cc5-0cc8-4283-8308-d0ddf0fe2946
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=744293297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.744293297
Directory	/workspace/28.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/28.adc_ctrl_smoke.1379593813
Short name	T591
Test name
Test status
Simulation time	5792907462 ps
CPU time	6.32 seconds
Started	Jan 03 01:17:26 PM PST 24
Finished	Jan 03 01:17:35 PM PST 24
Peak memory	200644 kb
Host	smart-e2def2f6-e2ae-42e9-a1e3-14642343b4bd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1379593813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.1379593813
Directory	/workspace/28.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/28.adc_ctrl_stress_all.1047700209
Short name	T254
Test name
Test status
Simulation time	169036309601 ps
CPU time	52.93 seconds
Started	Jan 03 01:17:32 PM PST 24
Finished	Jan 03 01:18:29 PM PST 24
Peak memory	200816 kb
Host	smart-f63f3649-a54a-428f-be46-d30489067a22
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047700209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all .1047700209
Directory	/workspace/28.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.686596750
Short name	T305
Test name
Test status
Simulation time	213961569409 ps
CPU time	156.79 seconds
Started	Jan 03 01:17:30 PM PST 24
Finished	Jan 03 01:20:11 PM PST 24
Peak memory	209164 kb
Host	smart-91347624-46cd-4c1b-b7d2-335fc51af018
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686596750 -assert nopo stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.686596750
Directory	/workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/29.adc_ctrl_alert_test.156545505
Short name	T475
Test name
Test status
Simulation time	504671866 ps
CPU time	1.74 seconds
Started	Jan 03 01:17:12 PM PST 24
Finished	Jan 03 01:17:15 PM PST 24
Peak memory	200632 kb
Host	smart-eadff963-70dc-4c6b-8761-cd08ae8cc3d9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156545505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.156545505
Directory	/workspace/29.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/29.adc_ctrl_filters_both.3263785080
Short name	T752
Test name
Test status
Simulation time	167549604607 ps
CPU time	100.2 seconds
Started	Jan 03 01:17:30 PM PST 24
Finished	Jan 03 01:19:14 PM PST 24
Peak memory	200960 kb
Host	smart-a16c01d2-abbe-4d28-b1c3-c5c10daa78ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3263785080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.3263785080
Directory	/workspace/29.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/29.adc_ctrl_filters_interrupt.2377641219
Short name	T479
Test name
Test status
Simulation time	166486365964 ps
CPU time	359.22 seconds
Started	Jan 03 01:17:36 PM PST 24
Finished	Jan 03 01:23:40 PM PST 24
Peak memory	200980 kb
Host	smart-9a07b86f-e584-4cfc-aaf5-2f17cdb07114
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2377641219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.2377641219
Directory	/workspace/29.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.1315489272
Short name	T498
Test name
Test status
Simulation time	492830512035 ps
CPU time	601.16 seconds
Started	Jan 03 01:17:38 PM PST 24
Finished	Jan 03 01:27:43 PM PST 24
Peak memory	200888 kb
Host	smart-adda59f9-1d75-48c2-97bc-cf7a5009e622
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315489272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru pt_fixed.1315489272
Directory	/workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/29.adc_ctrl_filters_polled.3827841535
Short name	T510
Test name
Test status
Simulation time	164809764516 ps
CPU time	96.69 seconds
Started	Jan 03 01:17:36 PM PST 24
Finished	Jan 03 01:19:17 PM PST 24
Peak memory	200860 kb
Host	smart-694050a3-388a-4077-bcc5-24ecf98caebf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3827841535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.3827841535
Directory	/workspace/29.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.251688034
Short name	T480
Test name
Test status
Simulation time	485894415012 ps
CPU time	317.19 seconds
Started	Jan 03 01:17:36 PM PST 24
Finished	Jan 03 01:22:58 PM PST 24
Peak memory	200956 kb
Host	smart-d01b4e1b-05a6-4013-8f38-5947da1f6e50
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=251688034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fixe d.251688034
Directory	/workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/29.adc_ctrl_filters_wakeup.2693612855
Short name	T815
Test name
Test status
Simulation time	368285174519 ps
CPU time	672.15 seconds
Started	Jan 03 01:17:39 PM PST 24
Finished	Jan 03 01:28:54 PM PST 24
Peak memory	200912 kb
Host	smart-a856c002-154c-4233-bd12-42ef0822cd62
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693612855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters _wakeup.2693612855
Directory	/workspace/29.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.1595891701
Short name	T463
Test name
Test status
Simulation time	322607560630 ps
CPU time	276.79 seconds
Started	Jan 03 01:17:14 PM PST 24
Finished	Jan 03 01:21:54 PM PST 24
Peak memory	200840 kb
Host	smart-f49d7f2b-37eb-4dd6-8d7a-bc90566d8ab0
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595891701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29 .adc_ctrl_filters_wakeup_fixed.1595891701
Directory	/workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/29.adc_ctrl_fsm_reset.3234995394
Short name	T519
Test name
Test status
Simulation time	86815603286 ps
CPU time	350.07 seconds
Started	Jan 03 01:17:14 PM PST 24
Finished	Jan 03 01:23:07 PM PST 24
Peak memory	201332 kb
Host	smart-072d67dd-ba12-4f51-b285-4a97b5ab5a03
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3234995394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.3234995394
Directory	/workspace/29.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/29.adc_ctrl_lowpower_counter.819383903
Short name	T614
Test name
Test status
Simulation time	34099438773 ps
CPU time	15.68 seconds
Started	Jan 03 01:17:27 PM PST 24
Finished	Jan 03 01:17:46 PM PST 24
Peak memory	200736 kb
Host	smart-7d6f74f2-4d39-4b04-96c1-04cf6679df72
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=819383903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.819383903
Directory	/workspace/29.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/29.adc_ctrl_poweron_counter.932687669
Short name	T555
Test name
Test status
Simulation time	3324913351 ps
CPU time	2.48 seconds
Started	Jan 03 01:17:13 PM PST 24
Finished	Jan 03 01:17:18 PM PST 24
Peak memory	200672 kb
Host	smart-580b02cb-0bd1-4574-8fd0-cffc1f2c266a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=932687669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.932687669
Directory	/workspace/29.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/29.adc_ctrl_smoke.3291909310
Short name	T428
Test name
Test status
Simulation time	5893284915 ps
CPU time	13.21 seconds
Started	Jan 03 01:17:36 PM PST 24
Finished	Jan 03 01:17:53 PM PST 24
Peak memory	200712 kb
Host	smart-573526d6-f285-4d5e-8740-3de53de5fe5b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3291909310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.3291909310
Directory	/workspace/29.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/29.adc_ctrl_stress_all.2507181684
Short name	T188
Test name
Test status
Simulation time	357115073385 ps
CPU time	604.85 seconds
Started	Jan 03 01:17:24 PM PST 24
Finished	Jan 03 01:27:32 PM PST 24
Peak memory	209512 kb
Host	smart-cd2b804b-be4f-4e87-931b-bb71b05c0cfe
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507181684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all .2507181684
Directory	/workspace/29.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.1289031608
Short name	T734
Test name
Test status
Simulation time	71814532015 ps
CPU time	197.52 seconds
Started	Jan 03 01:17:31 PM PST 24
Finished	Jan 03 01:20:53 PM PST 24
Peak memory	209668 kb
Host	smart-f3e20623-4022-434d-ae14-176f1200b778
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289031608 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.1289031608
Directory	/workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/3.adc_ctrl_alert_test.1004689225
Short name	T669
Test name
Test status
Simulation time	464866439 ps
CPU time	0.67 seconds
Started	Jan 03 01:14:45 PM PST 24
Finished	Jan 03 01:15:39 PM PST 24
Peak memory	200564 kb
Host	smart-ce2d6c04-26f5-463c-b088-77cd5c184c2d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004689225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.1004689225
Directory	/workspace/3.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/3.adc_ctrl_clock_gating.251533785
Short name	T700
Test name
Test status
Simulation time	491485991801 ps
CPU time	684.63 seconds
Started	Jan 03 01:14:37 PM PST 24
Finished	Jan 03 01:26:47 PM PST 24
Peak memory	200852 kb
Host	smart-ed96585b-6fd0-43f4-ae47-f277bf7c6961
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251533785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gatin g.251533785
Directory	/workspace/3.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/3.adc_ctrl_filters_both.4274986640
Short name	T256
Test name
Test status
Simulation time	324950379713 ps
CPU time	714.23 seconds
Started	Jan 03 01:14:38 PM PST 24
Finished	Jan 03 01:27:20 PM PST 24
Peak memory	200864 kb
Host	smart-9969b46b-13ae-4e06-bb89-280c56043e50
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4274986640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.4274986640
Directory	/workspace/3.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/3.adc_ctrl_filters_interrupt.2588507623
Short name	T54
Test name
Test status
Simulation time	164276596505 ps
CPU time	102.89 seconds
Started	Jan 03 01:14:36 PM PST 24
Finished	Jan 03 01:17:04 PM PST 24
Peak memory	200876 kb
Host	smart-28304a88-01f1-4773-8419-bf3b4ef54844
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2588507623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.2588507623
Directory	/workspace/3.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.2098793128
Short name	T649
Test name
Test status
Simulation time	318475259520 ps
CPU time	625.16 seconds
Started	Jan 03 01:14:43 PM PST 24
Finished	Jan 03 01:26:02 PM PST 24
Peak memory	200832 kb
Host	smart-fefce6bc-af17-4fbc-85df-14c36b442203
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098793128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup t_fixed.2098793128
Directory	/workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/3.adc_ctrl_filters_polled.3199656924
Short name	T157
Test name
Test status
Simulation time	492860486516 ps
CPU time	93 seconds
Started	Jan 03 01:14:43 PM PST 24
Finished	Jan 03 01:17:09 PM PST 24
Peak memory	200908 kb
Host	smart-fff50177-8292-43b9-9b3b-5020290c3e0a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3199656924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.3199656924
Directory	/workspace/3.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.1223132263
Short name	T631
Test name
Test status
Simulation time	328894983215 ps
CPU time	785.47 seconds
Started	Jan 03 01:14:38 PM PST 24
Finished	Jan 03 01:28:31 PM PST 24
Peak memory	200828 kb
Host	smart-78977a6f-b8f7-4d03-9563-0dcad2d19cba
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223132263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe d.1223132263
Directory	/workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/3.adc_ctrl_filters_wakeup.4126106042
Short name	T277
Test name
Test status
Simulation time	332916934095 ps
CPU time	783.71 seconds
Started	Jan 03 01:14:43 PM PST 24
Finished	Jan 03 01:28:40 PM PST 24
Peak memory	200912 kb
Host	smart-cdce35b1-3bbb-4c84-bb90-184b95768448
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126106042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_ wakeup.4126106042
Directory	/workspace/3.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.932949837
Short name	T650
Test name
Test status
Simulation time	168571537348 ps
CPU time	96.92 seconds
Started	Jan 03 01:14:47 PM PST 24
Finished	Jan 03 01:17:19 PM PST 24
Peak memory	200848 kb
Host	smart-d041d8c4-6dcf-48d5-86a3-153434a5f6c1
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932949837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ =adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.a dc_ctrl_filters_wakeup_fixed.932949837
Directory	/workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/3.adc_ctrl_lowpower_counter.2335644564
Short name	T586
Test name
Test status
Simulation time	35060657249 ps
CPU time	79.94 seconds
Started	Jan 03 01:14:42 PM PST 24
Finished	Jan 03 01:16:54 PM PST 24
Peak memory	200740 kb
Host	smart-32704a85-7e82-4ac4-9a52-a08b6a43fa84
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2335644564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.2335644564
Directory	/workspace/3.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/3.adc_ctrl_poweron_counter.939889951
Short name	T51
Test name
Test status
Simulation time	3758285712 ps
CPU time	1.22 seconds
Started	Jan 03 01:14:42 PM PST 24
Finished	Jan 03 01:15:36 PM PST 24
Peak memory	200744 kb
Host	smart-99008dfb-6598-458c-b00b-0b8fcda0d201
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=939889951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.939889951
Directory	/workspace/3.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/3.adc_ctrl_sec_cm.1148027641
Short name	T48
Test name
Test status
Simulation time	4194409055 ps
CPU time	3.29 seconds
Started	Jan 03 01:14:37 PM PST 24
Finished	Jan 03 01:15:26 PM PST 24
Peak memory	216064 kb
Host	smart-26d3b273-6078-4dbc-bca9-9f9cad6ca5bd
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148027641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.1148027641
Directory	/workspace/3.adc_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/3.adc_ctrl_smoke.1266878870
Short name	T431
Test name
Test status
Simulation time	6053698244 ps
CPU time	13.65 seconds
Started	Jan 03 01:14:33 PM PST 24
Finished	Jan 03 01:15:26 PM PST 24
Peak memory	200680 kb
Host	smart-23bd6daa-798f-44c5-a73e-6aca8efb8f93
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1266878870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.1266878870
Directory	/workspace/3.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/3.adc_ctrl_stress_all.1179190658
Short name	T95
Test name
Test status
Simulation time	327033699120 ps
CPU time	354.88 seconds
Started	Jan 03 01:14:36 PM PST 24
Finished	Jan 03 01:21:16 PM PST 24
Peak memory	200916 kb
Host	smart-f96ca23d-3437-45fa-87b2-fee2a9b93871
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179190658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all. 1179190658
Directory	/workspace/3.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/30.adc_ctrl_alert_test.344110037
Short name	T673
Test name
Test status
Simulation time	445110785 ps
CPU time	1.52 seconds
Started	Jan 03 01:17:26 PM PST 24
Finished	Jan 03 01:17:31 PM PST 24
Peak memory	200560 kb
Host	smart-6e298063-bb9c-4690-af0e-8d6662f5ef5f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344110037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.344110037
Directory	/workspace/30.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/30.adc_ctrl_clock_gating.3014745125
Short name	T293
Test name
Test status
Simulation time	491364038936 ps
CPU time	219.46 seconds
Started	Jan 03 01:17:14 PM PST 24
Finished	Jan 03 01:20:57 PM PST 24
Peak memory	200856 kb
Host	smart-27c7a95c-296c-40dd-a6f3-81e93e3ecc74
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014745125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat ing.3014745125
Directory	/workspace/30.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/30.adc_ctrl_filters_interrupt.471105941
Short name	T103
Test name
Test status
Simulation time	164366350625 ps
CPU time	196.4 seconds
Started	Jan 03 01:17:13 PM PST 24
Finished	Jan 03 01:20:32 PM PST 24
Peak memory	200964 kb
Host	smart-8180d29c-9eb0-4169-ae88-71d505e4a62f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=471105941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.471105941
Directory	/workspace/30.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.3509123866
Short name	T841
Test name
Test status
Simulation time	488448563515 ps
CPU time	289.41 seconds
Started	Jan 03 01:17:12 PM PST 24
Finished	Jan 03 01:22:04 PM PST 24
Peak memory	201000 kb
Host	smart-b5a9ff2a-8bb8-4d0e-9eff-e5d468f8a70b
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509123866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru pt_fixed.3509123866
Directory	/workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/30.adc_ctrl_filters_polled.2698382321
Short name	T146
Test name
Test status
Simulation time	488470566523 ps
CPU time	993.55 seconds
Started	Jan 03 01:17:27 PM PST 24
Finished	Jan 03 01:34:04 PM PST 24
Peak memory	200964 kb
Host	smart-43d79fc5-508c-4c59-b1d9-0d63d515f3a8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2698382321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.2698382321
Directory	/workspace/30.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.3731529405
Short name	T518
Test name
Test status
Simulation time	166506736348 ps
CPU time	190.14 seconds
Started	Jan 03 01:17:30 PM PST 24
Finished	Jan 03 01:20:44 PM PST 24
Peak memory	200868 kb
Host	smart-c162909b-4ade-4212-a8a5-0a41a568c7d5
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731529405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix ed.3731529405
Directory	/workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/30.adc_ctrl_filters_wakeup.3467101414
Short name	T144
Test name
Test status
Simulation time	161882959911 ps
CPU time	89.54 seconds
Started	Jan 03 01:17:14 PM PST 24
Finished	Jan 03 01:18:47 PM PST 24
Peak memory	200896 kb
Host	smart-2893b177-c219-4a51-81d6-401fe2bdbbfe
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467101414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters _wakeup.3467101414
Directory	/workspace/30.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.1955397873
Short name	T464
Test name
Test status
Simulation time	482726460640 ps
CPU time	305.61 seconds
Started	Jan 03 01:17:32 PM PST 24
Finished	Jan 03 01:22:42 PM PST 24
Peak memory	200892 kb
Host	smart-6d605608-71b5-45e4-a180-d5d7c3a3a111
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955397873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30 .adc_ctrl_filters_wakeup_fixed.1955397873
Directory	/workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/30.adc_ctrl_fsm_reset.2421711183
Short name	T737
Test name
Test status
Simulation time	67216815593 ps
CPU time	256.69 seconds
Started	Jan 03 01:17:23 PM PST 24
Finished	Jan 03 01:21:42 PM PST 24
Peak memory	201424 kb
Host	smart-1f5677a8-615d-4542-a0f8-499c7714cfce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2421711183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.2421711183
Directory	/workspace/30.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/30.adc_ctrl_lowpower_counter.2954606406
Short name	T844
Test name
Test status
Simulation time	35431819723 ps
CPU time	84.05 seconds
Started	Jan 03 01:17:14 PM PST 24
Finished	Jan 03 01:18:41 PM PST 24
Peak memory	200700 kb
Host	smart-9e090b8e-a2c6-4318-9cc9-907f5457254f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2954606406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.2954606406
Directory	/workspace/30.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/30.adc_ctrl_poweron_counter.3227166385
Short name	T712
Test name
Test status
Simulation time	4267838543 ps
CPU time	3.15 seconds
Started	Jan 03 01:17:26 PM PST 24
Finished	Jan 03 01:17:32 PM PST 24
Peak memory	200700 kb
Host	smart-cf8c2831-736d-4d7b-92ef-ab91e9e58239
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3227166385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.3227166385
Directory	/workspace/30.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/30.adc_ctrl_smoke.784674083
Short name	T796
Test name
Test status
Simulation time	5950756645 ps
CPU time	4.58 seconds
Started	Jan 03 01:17:15 PM PST 24
Finished	Jan 03 01:17:23 PM PST 24
Peak memory	200684 kb
Host	smart-da5ceed1-8630-4f4b-8819-6a3bcb7b28f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=784674083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.784674083
Directory	/workspace/30.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/30.adc_ctrl_stress_all.1386522552
Short name	T285
Test name
Test status
Simulation time	332592411164 ps
CPU time	202.79 seconds
Started	Jan 03 01:17:12 PM PST 24
Finished	Jan 03 01:20:38 PM PST 24
Peak memory	200748 kb
Host	smart-69fe21ad-ea39-48c7-81d0-597c3c06328c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386522552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all .1386522552
Directory	/workspace/30.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.2292333587
Short name	T809
Test name
Test status
Simulation time	39334894771 ps
CPU time	24.91 seconds
Started	Jan 03 01:17:29 PM PST 24
Finished	Jan 03 01:17:57 PM PST 24
Peak memory	209168 kb
Host	smart-5314304b-0ba2-4cbe-b9fb-240b123c5c83
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292333587 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.2292333587
Directory	/workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/31.adc_ctrl_alert_test.1280045482
Short name	T490
Test name
Test status
Simulation time	337112913 ps
CPU time	0.75 seconds
Started	Jan 03 01:17:28 PM PST 24
Finished	Jan 03 01:17:32 PM PST 24
Peak memory	200684 kb
Host	smart-085abe75-4d76-4a27-8466-25d9406f6d4b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280045482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.1280045482
Directory	/workspace/31.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/31.adc_ctrl_filters_both.330470086
Short name	T324
Test name
Test status
Simulation time	487108773932 ps
CPU time	1113.79 seconds
Started	Jan 03 01:17:14 PM PST 24
Finished	Jan 03 01:35:51 PM PST 24
Peak memory	200820 kb
Host	smart-2d407b26-9642-4c24-a405-80d8b9181c60
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=330470086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.330470086
Directory	/workspace/31.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.447628878
Short name	T499
Test name
Test status
Simulation time	331277956021 ps
CPU time	176.68 seconds
Started	Jan 03 01:17:30 PM PST 24
Finished	Jan 03 01:20:30 PM PST 24
Peak memory	200880 kb
Host	smart-fbc8f71b-f921-4ca7-a49c-038acee60d25
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=447628878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrup t_fixed.447628878
Directory	/workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/31.adc_ctrl_filters_polled.2572303501
Short name	T615
Test name
Test status
Simulation time	174684540604 ps
CPU time	193.09 seconds
Started	Jan 03 01:17:26 PM PST 24
Finished	Jan 03 01:20:43 PM PST 24
Peak memory	200896 kb
Host	smart-4db0622c-052b-4d88-9062-96a4db4dbf60
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2572303501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.2572303501
Directory	/workspace/31.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.2961590388
Short name	T777
Test name
Test status
Simulation time	490320720021 ps
CPU time	101.87 seconds
Started	Jan 03 01:17:27 PM PST 24
Finished	Jan 03 01:19:12 PM PST 24
Peak memory	200856 kb
Host	smart-754f1cfa-8561-4ce5-bfb4-4c37dc99abd2
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961590388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix ed.2961590388
Directory	/workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/31.adc_ctrl_filters_wakeup.3051044969
Short name	T816
Test name
Test status
Simulation time	169011718998 ps
CPU time	243.64 seconds
Started	Jan 03 01:17:30 PM PST 24
Finished	Jan 03 01:21:37 PM PST 24
Peak memory	200928 kb
Host	smart-f9314aa4-0f2c-47c6-b75a-0556fb4a9682
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051044969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters _wakeup.3051044969
Directory	/workspace/31.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.2857461527
Short name	T758
Test name
Test status
Simulation time	332145663497 ps
CPU time	408.33 seconds
Started	Jan 03 01:17:30 PM PST 24
Finished	Jan 03 01:24:22 PM PST 24
Peak memory	200888 kb
Host	smart-fc7c70d5-6256-4cf8-8992-f7d6f34291c2
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857461527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31 .adc_ctrl_filters_wakeup_fixed.2857461527
Directory	/workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/31.adc_ctrl_fsm_reset.746223758
Short name	T198
Test name
Test status
Simulation time	109424340459 ps
CPU time	433.78 seconds
Started	Jan 03 01:17:13 PM PST 24
Finished	Jan 03 01:24:30 PM PST 24
Peak memory	201280 kb
Host	smart-382cdd87-6109-43b3-9700-d93fabf4d79d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=746223758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.746223758
Directory	/workspace/31.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/31.adc_ctrl_lowpower_counter.826859170
Short name	T513
Test name
Test status
Simulation time	46875724736 ps
CPU time	41.76 seconds
Started	Jan 03 01:17:30 PM PST 24
Finished	Jan 03 01:18:15 PM PST 24
Peak memory	200736 kb
Host	smart-38ffe7c7-3cf2-4e84-819e-45929830bd22
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=826859170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.826859170
Directory	/workspace/31.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/31.adc_ctrl_poweron_counter.3742783498
Short name	T563
Test name
Test status
Simulation time	3369294124 ps
CPU time	4.72 seconds
Started	Jan 03 01:17:26 PM PST 24
Finished	Jan 03 01:17:34 PM PST 24
Peak memory	200724 kb
Host	smart-13e1d03f-c961-4dd0-9b65-ff4691a40003
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3742783498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.3742783498
Directory	/workspace/31.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/31.adc_ctrl_smoke.2148185623
Short name	T564
Test name
Test status
Simulation time	5840238269 ps
CPU time	4.13 seconds
Started	Jan 03 01:17:15 PM PST 24
Finished	Jan 03 01:17:23 PM PST 24
Peak memory	200660 kb
Host	smart-017416fa-dedb-4370-b278-e5514adb5f28
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2148185623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.2148185623
Directory	/workspace/31.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/31.adc_ctrl_stress_all.2401536814
Short name	T806
Test name
Test status
Simulation time	250576371330 ps
CPU time	321.53 seconds
Started	Jan 03 01:17:27 PM PST 24
Finished	Jan 03 01:22:52 PM PST 24
Peak memory	210936 kb
Host	smart-76111ca8-ce27-4a00-90f3-2e73a4814494
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401536814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all .2401536814
Directory	/workspace/31.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/32.adc_ctrl_alert_test.3745905651
Short name	T733
Test name
Test status
Simulation time	454632913 ps
CPU time	1.1 seconds
Started	Jan 03 01:17:40 PM PST 24
Finished	Jan 03 01:17:44 PM PST 24
Peak memory	200660 kb
Host	smart-9ebb29e6-dfc6-4d36-ad08-8c801ae2515d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745905651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.3745905651
Directory	/workspace/32.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/32.adc_ctrl_clock_gating.1110551724
Short name	T839
Test name
Test status
Simulation time	329118763894 ps
CPU time	152.7 seconds
Started	Jan 03 01:17:33 PM PST 24
Finished	Jan 03 01:20:10 PM PST 24
Peak memory	200908 kb
Host	smart-d48f1a71-86bf-44a7-87c0-071c26500079
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110551724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat ing.1110551724
Directory	/workspace/32.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/32.adc_ctrl_filters_both.1377708958
Short name	T763
Test name
Test status
Simulation time	165659604911 ps
CPU time	108.99 seconds
Started	Jan 03 01:17:34 PM PST 24
Finished	Jan 03 01:19:27 PM PST 24
Peak memory	200872 kb
Host	smart-3cb8a4af-8bf7-425f-ada1-1b5fa3f034c1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1377708958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.1377708958
Directory	/workspace/32.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/32.adc_ctrl_filters_interrupt.1923073488
Short name	T233
Test name
Test status
Simulation time	327791958871 ps
CPU time	741.35 seconds
Started	Jan 03 01:17:31 PM PST 24
Finished	Jan 03 01:29:57 PM PST 24
Peak memory	200868 kb
Host	smart-467e3798-10b3-4fa3-a757-2490b0aa6c07
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1923073488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.1923073488
Directory	/workspace/32.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.2164359388
Short name	T105
Test name
Test status
Simulation time	491466176120 ps
CPU time	110.41 seconds
Started	Jan 03 01:17:35 PM PST 24
Finished	Jan 03 01:19:30 PM PST 24
Peak memory	200852 kb
Host	smart-76f5f10d-5d29-442c-8abc-0defa710b7d8
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164359388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru pt_fixed.2164359388
Directory	/workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/32.adc_ctrl_filters_polled.2960728812
Short name	T166
Test name
Test status
Simulation time	498525391233 ps
CPU time	251.95 seconds
Started	Jan 03 01:17:33 PM PST 24
Finished	Jan 03 01:21:49 PM PST 24
Peak memory	200908 kb
Host	smart-96136cd6-e6c2-47d5-9ee1-a668862c7e00
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2960728812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.2960728812
Directory	/workspace/32.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.2417988821
Short name	T750
Test name
Test status
Simulation time	334060297826 ps
CPU time	566.08 seconds
Started	Jan 03 01:17:32 PM PST 24
Finished	Jan 03 01:27:02 PM PST 24
Peak memory	200932 kb
Host	smart-b5100fd2-c869-4854-aa38-8744480b1cb3
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417988821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix ed.2417988821
Directory	/workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/32.adc_ctrl_filters_wakeup.1975435085
Short name	T163
Test name
Test status
Simulation time	489804024042 ps
CPU time	290.02 seconds
Started	Jan 03 01:17:34 PM PST 24
Finished	Jan 03 01:22:28 PM PST 24
Peak memory	200408 kb
Host	smart-a09a4601-9e78-4cb0-a10b-e3257ac54725
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975435085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters _wakeup.1975435085
Directory	/workspace/32.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.1338827659
Short name	T133
Test name
Test status
Simulation time	330386182866 ps
CPU time	98.31 seconds
Started	Jan 03 01:17:31 PM PST 24
Finished	Jan 03 01:19:14 PM PST 24
Peak memory	200844 kb
Host	smart-d9ea56ce-487d-47e1-9db4-0755a5160ed4
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338827659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32 .adc_ctrl_filters_wakeup_fixed.1338827659
Directory	/workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/32.adc_ctrl_fsm_reset.3779053610
Short name	T53
Test name
Test status
Simulation time	95546374577 ps
CPU time	483.62 seconds
Started	Jan 03 01:17:35 PM PST 24
Finished	Jan 03 01:25:43 PM PST 24
Peak memory	201352 kb
Host	smart-57c84459-01ba-45c6-b80c-c316a0972854
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3779053610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.3779053610
Directory	/workspace/32.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/32.adc_ctrl_lowpower_counter.938676171
Short name	T453
Test name
Test status
Simulation time	25599802365 ps
CPU time	59.64 seconds
Started	Jan 03 01:17:34 PM PST 24
Finished	Jan 03 01:18:38 PM PST 24
Peak memory	200728 kb
Host	smart-a02e11cf-5eae-474f-98cc-e68388754d7a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=938676171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.938676171
Directory	/workspace/32.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/32.adc_ctrl_poweron_counter.1999773924
Short name	T507
Test name
Test status
Simulation time	4353298931 ps
CPU time	3.78 seconds
Started	Jan 03 01:17:33 PM PST 24
Finished	Jan 03 01:17:41 PM PST 24
Peak memory	200688 kb
Host	smart-d13cf9db-fae9-4f09-b30b-8335ab6fd402
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1999773924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.1999773924
Directory	/workspace/32.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/32.adc_ctrl_smoke.4133238504
Short name	T850
Test name
Test status
Simulation time	5795190007 ps
CPU time	14.55 seconds
Started	Jan 03 01:17:34 PM PST 24
Finished	Jan 03 01:17:53 PM PST 24
Peak memory	200756 kb
Host	smart-ce7f86f4-011b-4574-9c3a-5fd44b5b8946
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4133238504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.4133238504
Directory	/workspace/32.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/32.adc_ctrl_stress_all.2858456198
Short name	T834
Test name
Test status
Simulation time	329228012855 ps
CPU time	1218.16 seconds
Started	Jan 03 01:17:34 PM PST 24
Finished	Jan 03 01:37:57 PM PST 24
Peak memory	209520 kb
Host	smart-50b0ef49-68f3-4c6e-8687-3eece2f2f8d3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858456198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all .2858456198
Directory	/workspace/32.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.1862593037
Short name	T260
Test name
Test status
Simulation time	82917630995 ps
CPU time	181.81 seconds
Started	Jan 03 01:17:35 PM PST 24
Finished	Jan 03 01:20:41 PM PST 24
Peak memory	217268 kb
Host	smart-1c070c8d-d782-4f1c-a65b-a7efa15cf6b2
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862593037 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.1862593037
Directory	/workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/33.adc_ctrl_alert_test.1117587776
Short name	T43
Test name
Test status
Simulation time	394917920 ps
CPU time	0.83 seconds
Started	Jan 03 01:17:42 PM PST 24
Finished	Jan 03 01:17:46 PM PST 24
Peak memory	200592 kb
Host	smart-808b904d-ed39-43e2-92bd-e64b096592db
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117587776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.1117587776
Directory	/workspace/33.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/33.adc_ctrl_filters_interrupt.2348729986
Short name	T154
Test name
Test status
Simulation time	496789102508 ps
CPU time	147.34 seconds
Started	Jan 03 01:17:35 PM PST 24
Finished	Jan 03 01:20:06 PM PST 24
Peak memory	200948 kb
Host	smart-b9a670f3-c366-4d43-9915-ece29617f998
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2348729986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.2348729986
Directory	/workspace/33.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.2045690456
Short name	T774
Test name
Test status
Simulation time	494982252726 ps
CPU time	1127.77 seconds
Started	Jan 03 01:17:40 PM PST 24
Finished	Jan 03 01:36:31 PM PST 24
Peak memory	200900 kb
Host	smart-ea31e622-ce81-446c-83f0-da50d3aa2b57
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045690456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru pt_fixed.2045690456
Directory	/workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/33.adc_ctrl_filters_polled.529055329
Short name	T178
Test name
Test status
Simulation time	157993129804 ps
CPU time	91.2 seconds
Started	Jan 03 01:17:38 PM PST 24
Finished	Jan 03 01:19:13 PM PST 24
Peak memory	200836 kb
Host	smart-8ecaa6ae-af62-41d7-80a5-ed6553bcc1fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=529055329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.529055329
Directory	/workspace/33.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.1280471848
Short name	T116
Test name
Test status
Simulation time	329183723362 ps
CPU time	49.74 seconds
Started	Jan 03 01:17:45 PM PST 24
Finished	Jan 03 01:18:40 PM PST 24
Peak memory	200868 kb
Host	smart-6d7a47c3-58f7-41bd-ba04-6f93b6f951af
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280471848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix ed.1280471848
Directory	/workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.1901812142
Short name	T634
Test name
Test status
Simulation time	331341439830 ps
CPU time	355.9 seconds
Started	Jan 03 01:17:39 PM PST 24
Finished	Jan 03 01:23:38 PM PST 24
Peak memory	200940 kb
Host	smart-a02935e8-4e2a-4958-ba3a-ed2bca144add
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901812142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33 .adc_ctrl_filters_wakeup_fixed.1901812142
Directory	/workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/33.adc_ctrl_fsm_reset.1733577995
Short name	T37
Test name
Test status
Simulation time	97737239307 ps
CPU time	522.02 seconds
Started	Jan 03 01:17:58 PM PST 24
Finished	Jan 03 01:26:54 PM PST 24
Peak memory	201400 kb
Host	smart-c19e12e2-9754-4c16-982a-11b27b3cfe75
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1733577995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.1733577995
Directory	/workspace/33.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/33.adc_ctrl_lowpower_counter.1468269324
Short name	T526
Test name
Test status
Simulation time	38733383061 ps
CPU time	31.06 seconds
Started	Jan 03 01:17:41 PM PST 24
Finished	Jan 03 01:18:15 PM PST 24
Peak memory	200712 kb
Host	smart-4062d031-eff3-4563-a73d-04aaf180bce5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1468269324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.1468269324
Directory	/workspace/33.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/33.adc_ctrl_poweron_counter.2903369978
Short name	T485
Test name
Test status
Simulation time	2968899202 ps
CPU time	4.27 seconds
Started	Jan 03 01:17:55 PM PST 24
Finished	Jan 03 01:18:16 PM PST 24
Peak memory	200716 kb
Host	smart-7c107d1e-e803-4d64-9695-34a1dc38748a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2903369978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.2903369978
Directory	/workspace/33.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/33.adc_ctrl_smoke.2537521332
Short name	T791
Test name
Test status
Simulation time	5789508129 ps
CPU time	12.84 seconds
Started	Jan 03 01:17:34 PM PST 24
Finished	Jan 03 01:17:51 PM PST 24
Peak memory	200692 kb
Host	smart-a136410f-a16c-4a6a-abbb-56b0a7cb977b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2537521332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.2537521332
Directory	/workspace/33.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/33.adc_ctrl_stress_all.3531017737
Short name	T257
Test name
Test status
Simulation time	199238019992 ps
CPU time	164.49 seconds
Started	Jan 03 01:17:36 PM PST 24
Finished	Jan 03 01:20:25 PM PST 24
Peak memory	200912 kb
Host	smart-8fcca08f-6068-440b-8ff5-57642b1062a5
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531017737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all .3531017737
Directory	/workspace/33.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.546272150
Short name	T240
Test name
Test status
Simulation time	268275261830 ps
CPU time	144.43 seconds
Started	Jan 03 01:17:42 PM PST 24
Finished	Jan 03 01:20:09 PM PST 24
Peak memory	209556 kb
Host	smart-8b000be0-ea5d-4946-9d0e-bbdb174bc42d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546272150 -assert nopo stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.546272150
Directory	/workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/34.adc_ctrl_alert_test.970883876
Short name	T509
Test name
Test status
Simulation time	458790004 ps
CPU time	0.85 seconds
Started	Jan 03 01:17:15 PM PST 24
Finished	Jan 03 01:17:19 PM PST 24
Peak memory	200588 kb
Host	smart-ed326df6-f625-406e-b634-f771cd5cb8f4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970883876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.970883876
Directory	/workspace/34.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/34.adc_ctrl_clock_gating.3284340116
Short name	T341
Test name
Test status
Simulation time	324071059555 ps
CPU time	758.31 seconds
Started	Jan 03 01:17:49 PM PST 24
Finished	Jan 03 01:30:39 PM PST 24
Peak memory	200892 kb
Host	smart-dd299a90-cc17-4d88-be6b-3fdccbb14af8
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284340116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat ing.3284340116
Directory	/workspace/34.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/34.adc_ctrl_filters_both.3618944423
Short name	T174
Test name
Test status
Simulation time	495619299537 ps
CPU time	427.86 seconds
Started	Jan 03 01:17:50 PM PST 24
Finished	Jan 03 01:25:15 PM PST 24
Peak memory	200920 kb
Host	smart-9f2cdd21-0b98-4d79-8c7c-eefa96d99c7e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3618944423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.3618944423
Directory	/workspace/34.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/34.adc_ctrl_filters_interrupt.936341237
Short name	T209
Test name
Test status
Simulation time	169463180496 ps
CPU time	382.7 seconds
Started	Jan 03 01:17:48 PM PST 24
Finished	Jan 03 01:24:21 PM PST 24
Peak memory	200944 kb
Host	smart-fce4994e-8e92-4f39-8585-404765655a3e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=936341237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.936341237
Directory	/workspace/34.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.1607704038
Short name	T459
Test name
Test status
Simulation time	322159155946 ps
CPU time	131.28 seconds
Started	Jan 03 01:17:47 PM PST 24
Finished	Jan 03 01:20:04 PM PST 24
Peak memory	200200 kb
Host	smart-5e3b181b-9c25-4dd3-b25e-0dd96bcf36ef
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607704038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru pt_fixed.1607704038
Directory	/workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/34.adc_ctrl_filters_polled.3814093685
Short name	T269
Test name
Test status
Simulation time	160925583564 ps
CPU time	91.52 seconds
Started	Jan 03 01:17:39 PM PST 24
Finished	Jan 03 01:19:14 PM PST 24
Peak memory	200844 kb
Host	smart-dda79ee8-fe94-4631-b8ca-6217a4fba000
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3814093685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.3814093685
Directory	/workspace/34.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.1789373273
Short name	T409
Test name
Test status
Simulation time	501319287267 ps
CPU time	281.18 seconds
Started	Jan 03 01:17:55 PM PST 24
Finished	Jan 03 01:22:53 PM PST 24
Peak memory	200856 kb
Host	smart-ffedf170-44af-47e7-b9c9-4b7fdf70ead1
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789373273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix ed.1789373273
Directory	/workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.3146265819
Short name	T693
Test name
Test status
Simulation time	330891928638 ps
CPU time	110.51 seconds
Started	Jan 03 01:17:34 PM PST 24
Finished	Jan 03 01:19:29 PM PST 24
Peak memory	200784 kb
Host	smart-a5b39580-b65c-4d76-88d4-5eae81bd64a4
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146265819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34 .adc_ctrl_filters_wakeup_fixed.3146265819
Directory	/workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/34.adc_ctrl_fsm_reset.2750187799
Short name	T743
Test name
Test status
Simulation time	132300743823 ps
CPU time	465.15 seconds
Started	Jan 03 01:17:27 PM PST 24
Finished	Jan 03 01:25:15 PM PST 24
Peak memory	201200 kb
Host	smart-2f2793da-ca4b-44be-b537-4daa347b06fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2750187799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.2750187799
Directory	/workspace/34.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/34.adc_ctrl_lowpower_counter.2678240513
Short name	T530
Test name
Test status
Simulation time	34438616772 ps
CPU time	18.21 seconds
Started	Jan 03 01:17:26 PM PST 24
Finished	Jan 03 01:17:47 PM PST 24
Peak memory	200752 kb
Host	smart-688d32c7-0161-415f-8d43-33849a75644c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2678240513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.2678240513
Directory	/workspace/34.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/34.adc_ctrl_poweron_counter.1340152430
Short name	T12
Test name
Test status
Simulation time	4093039947 ps
CPU time	5.38 seconds
Started	Jan 03 01:17:27 PM PST 24
Finished	Jan 03 01:17:36 PM PST 24
Peak memory	200720 kb
Host	smart-7abea8b3-25c5-4f81-bf06-226f557984d3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1340152430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.1340152430
Directory	/workspace/34.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/34.adc_ctrl_smoke.3112341316
Short name	T638
Test name
Test status
Simulation time	5854577704 ps
CPU time	11.06 seconds
Started	Jan 03 01:17:46 PM PST 24
Finished	Jan 03 01:18:02 PM PST 24
Peak memory	200712 kb
Host	smart-09debdb9-0fb7-47f8-8280-a6eae2e33519
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3112341316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.3112341316
Directory	/workspace/34.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/34.adc_ctrl_stress_all.1215206079
Short name	T162
Test name
Test status
Simulation time	168410380215 ps
CPU time	100.11 seconds
Started	Jan 03 01:17:17 PM PST 24
Finished	Jan 03 01:19:01 PM PST 24
Peak memory	200904 kb
Host	smart-ef077085-77e6-421e-a7aa-bb0dd0312b7b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215206079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all .1215206079
Directory	/workspace/34.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.2855369173
Short name	T710
Test name
Test status
Simulation time	119177105040 ps
CPU time	172.97 seconds
Started	Jan 03 01:17:27 PM PST 24
Finished	Jan 03 01:20:23 PM PST 24
Peak memory	209580 kb
Host	smart-b02c6e2e-0616-4682-b7ee-f61b1fddde3d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855369173 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.2855369173
Directory	/workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/35.adc_ctrl_alert_test.673229788
Short name	T760
Test name
Test status
Simulation time	528603724 ps
CPU time	1.83 seconds
Started	Jan 03 01:17:34 PM PST 24
Finished	Jan 03 01:17:40 PM PST 24
Peak memory	200644 kb
Host	smart-67752de2-485e-4b66-a773-d5fc3f38fdf2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673229788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.673229788
Directory	/workspace/35.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/35.adc_ctrl_clock_gating.1008675903
Short name	T214
Test name
Test status
Simulation time	331811896149 ps
CPU time	209.01 seconds
Started	Jan 03 01:17:33 PM PST 24
Finished	Jan 03 01:21:06 PM PST 24
Peak memory	200896 kb
Host	smart-0aa37a13-6af1-4770-9dc5-3181ca516030
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008675903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat ing.1008675903
Directory	/workspace/35.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/35.adc_ctrl_filters_interrupt.1279310791
Short name	T691
Test name
Test status
Simulation time	483322844875 ps
CPU time	1089.5 seconds
Started	Jan 03 01:17:33 PM PST 24
Finished	Jan 03 01:35:47 PM PST 24
Peak memory	200940 kb
Host	smart-d9ab82bc-3706-40e9-be95-d0433470f107
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1279310791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.1279310791
Directory	/workspace/35.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/35.adc_ctrl_filters_polled.628648576
Short name	T584
Test name
Test status
Simulation time	492139705318 ps
CPU time	302.13 seconds
Started	Jan 03 01:17:15 PM PST 24
Finished	Jan 03 01:22:21 PM PST 24
Peak memory	200824 kb
Host	smart-ae680bd4-268d-4569-8c86-2d4977c94884
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=628648576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.628648576
Directory	/workspace/35.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.2296987547
Short name	T629
Test name
Test status
Simulation time	497483680260 ps
CPU time	314.11 seconds
Started	Jan 03 01:17:15 PM PST 24
Finished	Jan 03 01:22:33 PM PST 24
Peak memory	200856 kb
Host	smart-9b778073-2f36-476d-b8e7-2203a8309720
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296987547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix ed.2296987547
Directory	/workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/35.adc_ctrl_filters_wakeup.2389784533
Short name	T824
Test name
Test status
Simulation time	325477618437 ps
CPU time	373.44 seconds
Started	Jan 03 01:17:31 PM PST 24
Finished	Jan 03 01:23:48 PM PST 24
Peak memory	200828 kb
Host	smart-e766bd3e-aeee-4b19-9b4d-28bb48e8d8f7
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389784533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters _wakeup.2389784533
Directory	/workspace/35.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.1645359798
Short name	T461
Test name
Test status
Simulation time	495792672614 ps
CPU time	537.7 seconds
Started	Jan 03 01:17:38 PM PST 24
Finished	Jan 03 01:26:39 PM PST 24
Peak memory	200812 kb
Host	smart-61c2c494-c83f-4bba-a987-28a4e553b1dc
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645359798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35 .adc_ctrl_filters_wakeup_fixed.1645359798
Directory	/workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/35.adc_ctrl_fsm_reset.3938360405
Short name	T506
Test name
Test status
Simulation time	67826016895 ps
CPU time	317.9 seconds
Started	Jan 03 01:17:29 PM PST 24
Finished	Jan 03 01:22:50 PM PST 24
Peak memory	201328 kb
Host	smart-f1babdee-44ff-4dd9-a5f9-e2285e1dc47a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3938360405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.3938360405
Directory	/workspace/35.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/35.adc_ctrl_lowpower_counter.2052039725
Short name	T607
Test name
Test status
Simulation time	35835129373 ps
CPU time	16.66 seconds
Started	Jan 03 01:17:30 PM PST 24
Finished	Jan 03 01:17:51 PM PST 24
Peak memory	200748 kb
Host	smart-5aea74c6-eca4-4c0c-ae7b-c2788dbc5a57
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2052039725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.2052039725
Directory	/workspace/35.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/35.adc_ctrl_poweron_counter.3428643152
Short name	T661
Test name
Test status
Simulation time	3435125360 ps
CPU time	2.95 seconds
Started	Jan 03 01:17:32 PM PST 24
Finished	Jan 03 01:17:39 PM PST 24
Peak memory	200740 kb
Host	smart-bc829977-fd05-4b93-9c07-f976a6bfbef2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3428643152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.3428643152
Directory	/workspace/35.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/35.adc_ctrl_smoke.2488893554
Short name	T17
Test name
Test status
Simulation time	6099009923 ps
CPU time	15.72 seconds
Started	Jan 03 01:17:15 PM PST 24
Finished	Jan 03 01:17:34 PM PST 24
Peak memory	200672 kb
Host	smart-4a848bdd-516d-4e08-b749-6c61d7857d39
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2488893554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.2488893554
Directory	/workspace/35.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/35.adc_ctrl_stress_all.1058216159
Short name	T702
Test name
Test status
Simulation time	195894374298 ps
CPU time	432.1 seconds
Started	Jan 03 01:17:34 PM PST 24
Finished	Jan 03 01:24:51 PM PST 24
Peak memory	200980 kb
Host	smart-7082b27d-95c4-447c-92f4-b7bb4c1f50a2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058216159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all .1058216159
Directory	/workspace/35.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.1817406382
Short name	T251
Test name
Test status
Simulation time	196079465713 ps
CPU time	64.09 seconds
Started	Jan 03 01:17:34 PM PST 24
Finished	Jan 03 01:18:43 PM PST 24
Peak memory	209556 kb
Host	smart-468fdb30-89ee-4c27-9ac7-2226632a6a6d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817406382 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.1817406382
Directory	/workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/36.adc_ctrl_alert_test.3788932041
Short name	T522
Test name
Test status
Simulation time	375913438 ps
CPU time	1.38 seconds
Started	Jan 03 01:17:41 PM PST 24
Finished	Jan 03 01:17:45 PM PST 24
Peak memory	200624 kb
Host	smart-657cdc2d-3121-4327-928d-71732a76c162
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788932041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.3788932041
Directory	/workspace/36.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/36.adc_ctrl_clock_gating.586365100
Short name	T265
Test name
Test status
Simulation time	326638056205 ps
CPU time	221.3 seconds
Started	Jan 03 01:17:39 PM PST 24
Finished	Jan 03 01:21:24 PM PST 24
Peak memory	200848 kb
Host	smart-7eb6e8b9-65f7-4b25-b122-902a9d0794e2
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586365100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gati ng.586365100
Directory	/workspace/36.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/36.adc_ctrl_filters_both.1626924771
Short name	T204
Test name
Test status
Simulation time	168127264385 ps
CPU time	94.65 seconds
Started	Jan 03 01:17:39 PM PST 24
Finished	Jan 03 01:19:17 PM PST 24
Peak memory	200896 kb
Host	smart-7341d2cd-c939-48aa-b8a9-6950ffd83063
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1626924771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.1626924771
Directory	/workspace/36.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.1789496793
Short name	T762
Test name
Test status
Simulation time	494462591885 ps
CPU time	298.18 seconds
Started	Jan 03 01:17:39 PM PST 24
Finished	Jan 03 01:22:40 PM PST 24
Peak memory	200848 kb
Host	smart-f9939d0f-88af-45f9-96bf-5dfabff07c11
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789496793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru pt_fixed.1789496793
Directory	/workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/36.adc_ctrl_filters_polled.460385528
Short name	T681
Test name
Test status
Simulation time	327712568158 ps
CPU time	746.78 seconds
Started	Jan 03 01:17:33 PM PST 24
Finished	Jan 03 01:30:04 PM PST 24
Peak memory	200864 kb
Host	smart-6cf63750-8122-49a3-8885-0e34d898a978
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=460385528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.460385528
Directory	/workspace/36.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.158995652
Short name	T420
Test name
Test status
Simulation time	166425036042 ps
CPU time	176.4 seconds
Started	Jan 03 01:17:36 PM PST 24
Finished	Jan 03 01:20:37 PM PST 24
Peak memory	200876 kb
Host	smart-bb2f30f4-103c-4da8-83f1-4202b6295482
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=158995652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fixe d.158995652
Directory	/workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/36.adc_ctrl_filters_wakeup.1004712103
Short name	T826
Test name
Test status
Simulation time	166046461758 ps
CPU time	24.67 seconds
Started	Jan 03 01:17:40 PM PST 24
Finished	Jan 03 01:18:08 PM PST 24
Peak memory	200908 kb
Host	smart-efca2a54-f970-45f5-a30a-6f27be18bdd2
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004712103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters _wakeup.1004712103
Directory	/workspace/36.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.2241776213
Short name	T407
Test name
Test status
Simulation time	323546253964 ps
CPU time	741.26 seconds
Started	Jan 03 01:17:38 PM PST 24
Finished	Jan 03 01:30:03 PM PST 24
Peak memory	200860 kb
Host	smart-978febf9-7df0-48bb-b2a2-78164212659e
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241776213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36 .adc_ctrl_filters_wakeup_fixed.2241776213
Directory	/workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/36.adc_ctrl_fsm_reset.746656957
Short name	T560
Test name
Test status
Simulation time	84345667067 ps
CPU time	325.13 seconds
Started	Jan 03 01:17:39 PM PST 24
Finished	Jan 03 01:23:07 PM PST 24
Peak memory	201348 kb
Host	smart-64852314-ceaa-4e25-8050-ea930da2b6a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=746656957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.746656957
Directory	/workspace/36.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/36.adc_ctrl_lowpower_counter.2806314396
Short name	T725
Test name
Test status
Simulation time	41199306746 ps
CPU time	41.86 seconds
Started	Jan 03 01:17:35 PM PST 24
Finished	Jan 03 01:18:21 PM PST 24
Peak memory	200740 kb
Host	smart-6b4307d2-a894-4d02-bf65-e52beaaa6cf6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2806314396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.2806314396
Directory	/workspace/36.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/36.adc_ctrl_poweron_counter.1396317310
Short name	T531
Test name
Test status
Simulation time	3132548800 ps
CPU time	1.89 seconds
Started	Jan 03 01:17:35 PM PST 24
Finished	Jan 03 01:17:42 PM PST 24
Peak memory	200704 kb
Host	smart-0957a61d-d7ae-4e31-89ca-22c3537ff8d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1396317310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.1396317310
Directory	/workspace/36.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/36.adc_ctrl_smoke.3811431691
Short name	T655
Test name
Test status
Simulation time	5721938099 ps
CPU time	7.79 seconds
Started	Jan 03 01:17:30 PM PST 24
Finished	Jan 03 01:17:42 PM PST 24
Peak memory	200660 kb
Host	smart-c8d17d97-7302-416d-98a0-e62537c887fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3811431691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.3811431691
Directory	/workspace/36.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/36.adc_ctrl_stress_all.1783342762
Short name	T508
Test name
Test status
Simulation time	258682432152 ps
CPU time	568.54 seconds
Started	Jan 03 01:17:41 PM PST 24
Finished	Jan 03 01:27:13 PM PST 24
Peak memory	209588 kb
Host	smart-aa1624c4-36ca-4653-8a3f-388b0e2019aa
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783342762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all .1783342762
Directory	/workspace/36.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.893255391
Short name	T799
Test name
Test status
Simulation time	18507370625 ps
CPU time	48.28 seconds
Started	Jan 03 01:17:44 PM PST 24
Finished	Jan 03 01:18:37 PM PST 24
Peak memory	209200 kb
Host	smart-0fd2a849-7df4-4230-b30a-38416b212a09
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893255391 -assert nopo stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.893255391
Directory	/workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/37.adc_ctrl_alert_test.2439082993
Short name	T571
Test name
Test status
Simulation time	385485789 ps
CPU time	1.07 seconds
Started	Jan 03 01:17:15 PM PST 24
Finished	Jan 03 01:17:20 PM PST 24
Peak memory	200628 kb
Host	smart-f54fdd33-7440-4310-922f-548f60d07afe
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439082993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.2439082993
Directory	/workspace/37.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/37.adc_ctrl_filters_both.2296487891
Short name	T60
Test name
Test status
Simulation time	334468424199 ps
CPU time	417.25 seconds
Started	Jan 03 01:17:38 PM PST 24
Finished	Jan 03 01:24:39 PM PST 24
Peak memory	200896 kb
Host	smart-18e0cce3-38c2-4ba5-b02f-b9639761d0bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2296487891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.2296487891
Directory	/workspace/37.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.4169407628
Short name	T415
Test name
Test status
Simulation time	163754358411 ps
CPU time	375.55 seconds
Started	Jan 03 01:17:41 PM PST 24
Finished	Jan 03 01:24:00 PM PST 24
Peak memory	200880 kb
Host	smart-4445df5c-43ed-4fbb-a1bc-d0c23d62f880
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169407628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru pt_fixed.4169407628
Directory	/workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/37.adc_ctrl_filters_polled.785604977
Short name	T247
Test name
Test status
Simulation time	489440145394 ps
CPU time	599.08 seconds
Started	Jan 03 01:17:35 PM PST 24
Finished	Jan 03 01:27:39 PM PST 24
Peak memory	200808 kb
Host	smart-d62d290e-4198-4a89-a08a-effd9e2dfcf1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=785604977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.785604977
Directory	/workspace/37.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.3608993656
Short name	T474
Test name
Test status
Simulation time	328607915792 ps
CPU time	753.43 seconds
Started	Jan 03 01:17:50 PM PST 24
Finished	Jan 03 01:30:41 PM PST 24
Peak memory	200956 kb
Host	smart-f10135a5-fc85-4cb4-9313-543d246456bc
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608993656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix ed.3608993656
Directory	/workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/37.adc_ctrl_filters_wakeup.1893407505
Short name	T672
Test name
Test status
Simulation time	511405770834 ps
CPU time	1157.83 seconds
Started	Jan 03 01:17:47 PM PST 24
Finished	Jan 03 01:37:10 PM PST 24
Peak memory	200120 kb
Host	smart-ad664f69-6225-403c-bca2-9b6998089521
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893407505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters _wakeup.1893407505
Directory	/workspace/37.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.3491760576
Short name	T435
Test name
Test status
Simulation time	330831352992 ps
CPU time	194.88 seconds
Started	Jan 03 01:17:54 PM PST 24
Finished	Jan 03 01:21:27 PM PST 24
Peak memory	200856 kb
Host	smart-fe81a4f0-915e-4178-8a9d-6709e804d34c
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491760576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37 .adc_ctrl_filters_wakeup_fixed.3491760576
Directory	/workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/37.adc_ctrl_fsm_reset.1088093092
Short name	T833
Test name
Test status
Simulation time	136947620653 ps
CPU time	443.44 seconds
Started	Jan 03 01:17:28 PM PST 24
Finished	Jan 03 01:24:55 PM PST 24
Peak memory	201336 kb
Host	smart-c851b4e1-5f3f-4796-bc6e-1389317704e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1088093092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.1088093092
Directory	/workspace/37.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/37.adc_ctrl_lowpower_counter.2791072423
Short name	T593
Test name
Test status
Simulation time	44299875396 ps
CPU time	20.88 seconds
Started	Jan 03 01:18:01 PM PST 24
Finished	Jan 03 01:18:34 PM PST 24
Peak memory	200736 kb
Host	smart-ac7baaae-5d42-4f70-a91e-7e61bfaead84
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2791072423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.2791072423
Directory	/workspace/37.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/37.adc_ctrl_poweron_counter.281086940
Short name	T476
Test name
Test status
Simulation time	4127937372 ps
CPU time	3.26 seconds
Started	Jan 03 01:17:48 PM PST 24
Finished	Jan 03 01:17:56 PM PST 24
Peak memory	200736 kb
Host	smart-e69d1e44-8fc8-4fe0-b5de-09f3a8b6727d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=281086940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.281086940
Directory	/workspace/37.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/37.adc_ctrl_smoke.4186898768
Short name	T419
Test name
Test status
Simulation time	5871859364 ps
CPU time	13.08 seconds
Started	Jan 03 01:17:43 PM PST 24
Finished	Jan 03 01:18:01 PM PST 24
Peak memory	200664 kb
Host	smart-79c85dcc-605f-44fa-8d62-77f2c16aa439
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4186898768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.4186898768
Directory	/workspace/37.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/37.adc_ctrl_stress_all.3602581458
Short name	T314
Test name
Test status
Simulation time	345333038955 ps
CPU time	198.94 seconds
Started	Jan 03 01:18:11 PM PST 24
Finished	Jan 03 01:22:01 PM PST 24
Peak memory	200916 kb
Host	smart-fadc0e68-b24c-4856-b57c-5e288706980b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602581458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all .3602581458
Directory	/workspace/37.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.2395615478
Short name	T317
Test name
Test status
Simulation time	131753263708 ps
CPU time	35.67 seconds
Started	Jan 03 01:17:42 PM PST 24
Finished	Jan 03 01:18:21 PM PST 24
Peak memory	210240 kb
Host	smart-09dd4908-a3db-4278-b332-ac2293f7f8b1
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395615478 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.2395615478
Directory	/workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/38.adc_ctrl_alert_test.326487514
Short name	T675
Test name
Test status
Simulation time	380323547 ps
CPU time	1.05 seconds
Started	Jan 03 01:17:36 PM PST 24
Finished	Jan 03 01:17:41 PM PST 24
Peak memory	200604 kb
Host	smart-b6a8d0f6-5f5c-429f-9330-3252c911c744
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326487514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.326487514
Directory	/workspace/38.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/38.adc_ctrl_clock_gating.4120558130
Short name	T328
Test name
Test status
Simulation time	325209874012 ps
CPU time	358.02 seconds
Started	Jan 03 01:17:30 PM PST 24
Finished	Jan 03 01:23:31 PM PST 24
Peak memory	200840 kb
Host	smart-668d4729-22c7-44df-8436-48676cd9eee9
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120558130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat ing.4120558130
Directory	/workspace/38.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/38.adc_ctrl_filters_both.2599349176
Short name	T216
Test name
Test status
Simulation time	335356078267 ps
CPU time	763.58 seconds
Started	Jan 03 01:17:32 PM PST 24
Finished	Jan 03 01:30:20 PM PST 24
Peak memory	200916 kb
Host	smart-acc3948c-c899-4369-8f9a-34fecf73c291
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2599349176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.2599349176
Directory	/workspace/38.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.1367639989
Short name	T445
Test name
Test status
Simulation time	323044713873 ps
CPU time	189.06 seconds
Started	Jan 03 01:17:29 PM PST 24
Finished	Jan 03 01:20:42 PM PST 24
Peak memory	200904 kb
Host	smart-5e457baf-6243-4f1d-a541-86af98596260
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367639989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru pt_fixed.1367639989
Directory	/workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.1301173070
Short name	T569
Test name
Test status
Simulation time	167339207342 ps
CPU time	63.9 seconds
Started	Jan 03 01:17:35 PM PST 24
Finished	Jan 03 01:18:43 PM PST 24
Peak memory	200860 kb
Host	smart-6e68ad74-38ad-4483-9207-6308de382f74
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301173070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix ed.1301173070
Directory	/workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/38.adc_ctrl_filters_wakeup.1429233068
Short name	T109
Test name
Test status
Simulation time	168260079989 ps
CPU time	93.29 seconds
Started	Jan 03 01:17:33 PM PST 24
Finished	Jan 03 01:19:11 PM PST 24
Peak memory	200920 kb
Host	smart-0c5e3e71-bc09-4be2-bdb8-eced1939be76
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429233068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters _wakeup.1429233068
Directory	/workspace/38.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.3205785413
Short name	T525
Test name
Test status
Simulation time	166577652605 ps
CPU time	105.94 seconds
Started	Jan 03 01:17:35 PM PST 24
Finished	Jan 03 01:19:25 PM PST 24
Peak memory	200864 kb
Host	smart-5493e174-9eb6-49f0-83b8-4fdcfae0e316
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205785413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38 .adc_ctrl_filters_wakeup_fixed.3205785413
Directory	/workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/38.adc_ctrl_fsm_reset.1851385619
Short name	T191
Test name
Test status
Simulation time	68903619544 ps
CPU time	281.75 seconds
Started	Jan 03 01:17:31 PM PST 24
Finished	Jan 03 01:22:17 PM PST 24
Peak memory	201284 kb
Host	smart-568ce259-4028-456a-8c5a-2466d1cff129
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1851385619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.1851385619
Directory	/workspace/38.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/38.adc_ctrl_lowpower_counter.44604668
Short name	T404
Test name
Test status
Simulation time	44516487545 ps
CPU time	15.79 seconds
Started	Jan 03 01:17:31 PM PST 24
Finished	Jan 03 01:17:51 PM PST 24
Peak memory	200752 kb
Host	smart-40e10b3b-9b68-42c6-b276-e7807557aff4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=44604668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.44604668
Directory	/workspace/38.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/38.adc_ctrl_poweron_counter.4137157090
Short name	T430
Test name
Test status
Simulation time	4876076802 ps
CPU time	3.61 seconds
Started	Jan 03 01:17:30 PM PST 24
Finished	Jan 03 01:17:37 PM PST 24
Peak memory	200704 kb
Host	smart-b89a8f63-1a6a-41bd-b82d-54c20697c869
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4137157090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.4137157090
Directory	/workspace/38.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/38.adc_ctrl_smoke.1111006401
Short name	T716
Test name
Test status
Simulation time	5986840768 ps
CPU time	4.64 seconds
Started	Jan 03 01:17:25 PM PST 24
Finished	Jan 03 01:17:32 PM PST 24
Peak memory	200644 kb
Host	smart-54bf8b0a-b334-4625-b46c-b5a277e296ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1111006401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.1111006401
Directory	/workspace/38.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/38.adc_ctrl_stress_all.2318334816
Short name	T671
Test name
Test status
Simulation time	155802558651 ps
CPU time	498.66 seconds
Started	Jan 03 01:17:29 PM PST 24
Finished	Jan 03 01:25:51 PM PST 24
Peak memory	201300 kb
Host	smart-ed3e70c0-d752-4818-95f1-2180d2fd4fdb
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318334816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all .2318334816
Directory	/workspace/38.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.2487396446
Short name	T557
Test name
Test status
Simulation time	239237278992 ps
CPU time	337.48 seconds
Started	Jan 03 01:17:33 PM PST 24
Finished	Jan 03 01:23:15 PM PST 24
Peak memory	209676 kb
Host	smart-eecef360-5f9d-4732-a60b-3ad1d1d3253d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487396446 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.2487396446
Directory	/workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/39.adc_ctrl_alert_test.3494844632
Short name	T451
Test name
Test status
Simulation time	513619763 ps
CPU time	0.83 seconds
Started	Jan 03 01:17:46 PM PST 24
Finished	Jan 03 01:17:52 PM PST 24
Peak memory	200692 kb
Host	smart-28ad8912-d268-4589-b9d5-6707ee2e5cf5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494844632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.3494844632
Directory	/workspace/39.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/39.adc_ctrl_clock_gating.31430270
Short name	T688
Test name
Test status
Simulation time	502910063712 ps
CPU time	225.74 seconds
Started	Jan 03 01:17:43 PM PST 24
Finished	Jan 03 01:21:34 PM PST 24
Peak memory	200824 kb
Host	smart-6fef807f-4f6e-475c-bc3a-4d9f75767207
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31430270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gatin g.31430270
Directory	/workspace/39.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/39.adc_ctrl_filters_interrupt.3420275664
Short name	T311
Test name
Test status
Simulation time	333182868851 ps
CPU time	774.48 seconds
Started	Jan 03 01:17:34 PM PST 24
Finished	Jan 03 01:30:33 PM PST 24
Peak memory	201016 kb
Host	smart-206ef578-1ba9-4ad8-b90c-19d35d12bd55
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3420275664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.3420275664
Directory	/workspace/39.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.463123838
Short name	T836
Test name
Test status
Simulation time	491273082421 ps
CPU time	1154.11 seconds
Started	Jan 03 01:17:37 PM PST 24
Finished	Jan 03 01:36:55 PM PST 24
Peak memory	200896 kb
Host	smart-c8b6bf6f-9fc6-4d8d-865a-2c9a1466403e
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=463123838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrup t_fixed.463123838
Directory	/workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/39.adc_ctrl_filters_polled.3146009145
Short name	T848
Test name
Test status
Simulation time	492611328130 ps
CPU time	211.02 seconds
Started	Jan 03 01:17:35 PM PST 24
Finished	Jan 03 01:21:10 PM PST 24
Peak memory	200900 kb
Host	smart-ca29f07c-e1b5-4372-8083-227f944a4c68
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3146009145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.3146009145
Directory	/workspace/39.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.358771503
Short name	T596
Test name
Test status
Simulation time	490606665292 ps
CPU time	520.47 seconds
Started	Jan 03 01:17:33 PM PST 24
Finished	Jan 03 01:26:22 PM PST 24
Peak memory	200888 kb
Host	smart-a43b5723-f8b9-4ef3-b3aa-faf1e87cbb60
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=358771503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fixe d.358771503
Directory	/workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/39.adc_ctrl_filters_wakeup.3785479568
Short name	T326
Test name
Test status
Simulation time	174627869295 ps
CPU time	285.27 seconds
Started	Jan 03 01:17:32 PM PST 24
Finished	Jan 03 01:22:21 PM PST 24
Peak memory	200872 kb
Host	smart-99acf2e6-d010-40ef-a87a-2fdb9afb703f
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785479568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters _wakeup.3785479568
Directory	/workspace/39.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.3112166092
Short name	T621
Test name
Test status
Simulation time	166418374883 ps
CPU time	366.95 seconds
Started	Jan 03 01:17:38 PM PST 24
Finished	Jan 03 01:23:49 PM PST 24
Peak memory	200860 kb
Host	smart-29d3d1bd-00c1-44c1-83d5-e354ba72db37
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112166092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39 .adc_ctrl_filters_wakeup_fixed.3112166092
Directory	/workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/39.adc_ctrl_fsm_reset.1222304673
Short name	T194
Test name
Test status
Simulation time	115993695663 ps
CPU time	652.51 seconds
Started	Jan 03 01:17:59 PM PST 24
Finished	Jan 03 01:29:05 PM PST 24
Peak memory	201416 kb
Host	smart-4766c993-b456-4e6b-8f63-114b9e75cc3e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1222304673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.1222304673
Directory	/workspace/39.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/39.adc_ctrl_lowpower_counter.1839396582
Short name	T487
Test name
Test status
Simulation time	32762452287 ps
CPU time	39.54 seconds
Started	Jan 03 01:17:40 PM PST 24
Finished	Jan 03 01:18:23 PM PST 24
Peak memory	200724 kb
Host	smart-a0db2139-aa13-4064-affb-99c75479c785
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1839396582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.1839396582
Directory	/workspace/39.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/39.adc_ctrl_poweron_counter.1083156591
Short name	T786
Test name
Test status
Simulation time	2746277839 ps
CPU time	2.36 seconds
Started	Jan 03 01:17:41 PM PST 24
Finished	Jan 03 01:17:46 PM PST 24
Peak memory	200740 kb
Host	smart-52f0f77a-a976-4a9d-8b59-7221fb7a37e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1083156591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.1083156591
Directory	/workspace/39.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/39.adc_ctrl_smoke.1867027647
Short name	T819
Test name
Test status
Simulation time	5922652507 ps
CPU time	3.42 seconds
Started	Jan 03 01:17:31 PM PST 24
Finished	Jan 03 01:17:39 PM PST 24
Peak memory	200584 kb
Host	smart-0aa4fd7e-e4c9-4323-81ae-fb4578de85cd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1867027647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.1867027647
Directory	/workspace/39.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/39.adc_ctrl_stress_all.1744239822
Short name	T212
Test name
Test status
Simulation time	233884728847 ps
CPU time	126.49 seconds
Started	Jan 03 01:17:42 PM PST 24
Finished	Jan 03 01:19:52 PM PST 24
Peak memory	200888 kb
Host	smart-2f364077-df3f-4ed3-b928-697091e34ccb
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744239822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all .1744239822
Directory	/workspace/39.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/4.adc_ctrl_alert_test.1437328561
Short name	T647
Test name
Test status
Simulation time	525124998 ps
CPU time	0.85 seconds
Started	Jan 03 01:14:45 PM PST 24
Finished	Jan 03 01:15:39 PM PST 24
Peak memory	200652 kb
Host	smart-cf65a0a1-7fc7-4dac-887b-cd7649cb547e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437328561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.1437328561
Directory	/workspace/4.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/4.adc_ctrl_clock_gating.2354941658
Short name	T276
Test name
Test status
Simulation time	166826112414 ps
CPU time	350.6 seconds
Started	Jan 03 01:14:40 PM PST 24
Finished	Jan 03 01:21:21 PM PST 24
Peak memory	200956 kb
Host	smart-3b7490cd-3eed-45bc-8b4e-d0fff16e661f
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354941658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati ng.2354941658
Directory	/workspace/4.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/4.adc_ctrl_filters_both.1148415528
Short name	T255
Test name
Test status
Simulation time	162932610235 ps
CPU time	41.36 seconds
Started	Jan 03 01:14:45 PM PST 24
Finished	Jan 03 01:16:21 PM PST 24
Peak memory	200952 kb
Host	smart-406dfb54-b50d-40e9-b3ef-c1349208ca84
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1148415528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.1148415528
Directory	/workspace/4.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/4.adc_ctrl_filters_interrupt.2005976113
Short name	T821
Test name
Test status
Simulation time	162018421308 ps
CPU time	25.63 seconds
Started	Jan 03 01:14:47 PM PST 24
Finished	Jan 03 01:16:08 PM PST 24
Peak memory	200928 kb
Host	smart-3e25d059-524b-4aa5-9f4d-b61d84d33281
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2005976113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.2005976113
Directory	/workspace/4.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.1044952660
Short name	T467
Test name
Test status
Simulation time	496633153501 ps
CPU time	157.34 seconds
Started	Jan 03 01:14:38 PM PST 24
Finished	Jan 03 01:18:02 PM PST 24
Peak memory	200916 kb
Host	smart-e183b45b-b10d-4e86-aab8-fbcec71d3f85
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044952660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup t_fixed.1044952660
Directory	/workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/4.adc_ctrl_filters_polled.1275564298
Short name	T749
Test name
Test status
Simulation time	324011832647 ps
CPU time	773.57 seconds
Started	Jan 03 01:14:47 PM PST 24
Finished	Jan 03 01:28:36 PM PST 24
Peak memory	200836 kb
Host	smart-7606f7de-d97a-4e2c-8424-3cce10ba1778
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1275564298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.1275564298
Directory	/workspace/4.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.2438061133
Short name	T617
Test name
Test status
Simulation time	484263634013 ps
CPU time	1144.31 seconds
Started	Jan 03 01:14:41 PM PST 24
Finished	Jan 03 01:34:37 PM PST 24
Peak memory	200924 kb
Host	smart-e30fe1bd-2ac4-43e4-86d1-b28c6a829256
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438061133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe d.2438061133
Directory	/workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/4.adc_ctrl_filters_wakeup.80330521
Short name	T158
Test name
Test status
Simulation time	168349758231 ps
CPU time	100.4 seconds
Started	Jan 03 01:14:40 PM PST 24
Finished	Jan 03 01:17:11 PM PST 24
Peak memory	200884 kb
Host	smart-a6462211-4c58-4cd1-9611-27476972e77b
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80330521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_ wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_wa keup.80330521
Directory	/workspace/4.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.3893478858
Short name	T722
Test name
Test status
Simulation time	167276194586 ps
CPU time	131.82 seconds
Started	Jan 03 01:14:37 PM PST 24
Finished	Jan 03 01:17:33 PM PST 24
Peak memory	200840 kb
Host	smart-2c773be6-917b-4acd-be44-4405d750be97
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893478858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4. adc_ctrl_filters_wakeup_fixed.3893478858
Directory	/workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/4.adc_ctrl_fsm_reset.4217292406
Short name	T618
Test name
Test status
Simulation time	82773072850 ps
CPU time	319.29 seconds
Started	Jan 03 01:14:51 PM PST 24
Finished	Jan 03 01:21:10 PM PST 24
Peak memory	201260 kb
Host	smart-e506e187-3090-4193-a27c-2e8f5d9dfc58
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4217292406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.4217292406
Directory	/workspace/4.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/4.adc_ctrl_lowpower_counter.1448348098
Short name	T128
Test name
Test status
Simulation time	38381526435 ps
CPU time	48.79 seconds
Started	Jan 03 01:14:46 PM PST 24
Finished	Jan 03 01:16:29 PM PST 24
Peak memory	200676 kb
Host	smart-8e1a19d5-e310-4c6e-95a8-b811e564b357
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1448348098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.1448348098
Directory	/workspace/4.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/4.adc_ctrl_poweron_counter.1901490846
Short name	T553
Test name
Test status
Simulation time	3173336458 ps
CPU time	8.03 seconds
Started	Jan 03 01:14:40 PM PST 24
Finished	Jan 03 01:15:37 PM PST 24
Peak memory	200712 kb
Host	smart-b12ac6ce-fda8-497e-8587-2427fefb18d7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1901490846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.1901490846
Directory	/workspace/4.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/4.adc_ctrl_sec_cm.2789508982
Short name	T46
Test name
Test status
Simulation time	4336051269 ps
CPU time	3.25 seconds
Started	Jan 03 01:14:39 PM PST 24
Finished	Jan 03 01:15:31 PM PST 24
Peak memory	216092 kb
Host	smart-147a50ae-552f-41c8-baf1-8924e7e8346e
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789508982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.2789508982
Directory	/workspace/4.adc_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/4.adc_ctrl_smoke.632658735
Short name	T622
Test name
Test status
Simulation time	5989707239 ps
CPU time	9.93 seconds
Started	Jan 03 01:14:41 PM PST 24
Finished	Jan 03 01:15:43 PM PST 24
Peak memory	200688 kb
Host	smart-b86794c6-21d8-402b-88a6-83a2dd238398
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=632658735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.632658735
Directory	/workspace/4.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/40.adc_ctrl_alert_test.1855904023
Short name	T455
Test name
Test status
Simulation time	363002436 ps
CPU time	0.79 seconds
Started	Jan 03 01:17:35 PM PST 24
Finished	Jan 03 01:17:40 PM PST 24
Peak memory	200536 kb
Host	smart-bba619e0-16e5-4828-88fd-59e172e27a22
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855904023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.1855904023
Directory	/workspace/40.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/40.adc_ctrl_clock_gating.4256535495
Short name	T756
Test name
Test status
Simulation time	331885312520 ps
CPU time	735.96 seconds
Started	Jan 03 01:17:31 PM PST 24
Finished	Jan 03 01:29:52 PM PST 24
Peak memory	200848 kb
Host	smart-65895598-e967-4ba6-8386-07f841d52e85
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256535495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat ing.4256535495
Directory	/workspace/40.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/40.adc_ctrl_filters_both.2754800123
Short name	T823
Test name
Test status
Simulation time	162708725231 ps
CPU time	394.35 seconds
Started	Jan 03 01:17:29 PM PST 24
Finished	Jan 03 01:24:06 PM PST 24
Peak memory	200968 kb
Host	smart-7fec822f-10c9-4aad-a36e-76a03df671c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2754800123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.2754800123
Directory	/workspace/40.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/40.adc_ctrl_filters_interrupt.1249998325
Short name	T590
Test name
Test status
Simulation time	168410308108 ps
CPU time	157.73 seconds
Started	Jan 03 01:17:42 PM PST 24
Finished	Jan 03 01:20:24 PM PST 24
Peak memory	200828 kb
Host	smart-fb5785a9-6614-44b0-8b14-950ec3eb1abf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1249998325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.1249998325
Directory	/workspace/40.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.2963277755
Short name	T656
Test name
Test status
Simulation time	330430312327 ps
CPU time	138.56 seconds
Started	Jan 03 01:17:34 PM PST 24
Finished	Jan 03 01:19:57 PM PST 24
Peak memory	200916 kb
Host	smart-c1010068-ceba-45fa-a0bd-0a813de442bd
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963277755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru pt_fixed.2963277755
Directory	/workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/40.adc_ctrl_filters_polled.660564366
Short name	T325
Test name
Test status
Simulation time	329046762983 ps
CPU time	751.17 seconds
Started	Jan 03 01:17:52 PM PST 24
Finished	Jan 03 01:30:41 PM PST 24
Peak memory	200984 kb
Host	smart-d9eb7883-d0b0-4591-916d-2543812648c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=660564366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.660564366
Directory	/workspace/40.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.1698546146
Short name	T748
Test name
Test status
Simulation time	335288762944 ps
CPU time	205.79 seconds
Started	Jan 03 01:17:40 PM PST 24
Finished	Jan 03 01:21:09 PM PST 24
Peak memory	200820 kb
Host	smart-56d11308-5079-4ea2-a3e0-6d95df27b5e8
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698546146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix ed.1698546146
Directory	/workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/40.adc_ctrl_filters_wakeup.3840385339
Short name	T543
Test name
Test status
Simulation time	164090460972 ps
CPU time	381.56 seconds
Started	Jan 03 01:17:38 PM PST 24
Finished	Jan 03 01:24:03 PM PST 24
Peak memory	200892 kb
Host	smart-e1ec6462-075f-48e0-882c-b17614cedf24
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840385339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters _wakeup.3840385339
Directory	/workspace/40.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.2208755498
Short name	T236
Test name
Test status
Simulation time	336674445838 ps
CPU time	700.98 seconds
Started	Jan 03 01:17:32 PM PST 24
Finished	Jan 03 01:29:17 PM PST 24
Peak memory	200776 kb
Host	smart-500fc223-954a-4646-959b-fe579195ca33
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208755498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40 .adc_ctrl_filters_wakeup_fixed.2208755498
Directory	/workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/40.adc_ctrl_fsm_reset.2910441146
Short name	T350
Test name
Test status
Simulation time	129524366391 ps
CPU time	399.08 seconds
Started	Jan 03 01:17:34 PM PST 24
Finished	Jan 03 01:24:17 PM PST 24
Peak memory	200336 kb
Host	smart-1235388e-b0cd-49e1-a337-c5732225cfc4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2910441146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.2910441146
Directory	/workspace/40.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/40.adc_ctrl_lowpower_counter.3045383521
Short name	T630
Test name
Test status
Simulation time	39641216361 ps
CPU time	8.42 seconds
Started	Jan 03 01:17:34 PM PST 24
Finished	Jan 03 01:17:47 PM PST 24
Peak memory	200768 kb
Host	smart-869e3934-c43c-46bd-b746-278ae8275423
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3045383521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.3045383521
Directory	/workspace/40.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/40.adc_ctrl_poweron_counter.130682000
Short name	T515
Test name
Test status
Simulation time	3306649716 ps
CPU time	2.72 seconds
Started	Jan 03 01:17:34 PM PST 24
Finished	Jan 03 01:17:41 PM PST 24
Peak memory	200036 kb
Host	smart-1714f669-11cb-4117-8abb-d8e5af1e6efd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=130682000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.130682000
Directory	/workspace/40.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/40.adc_ctrl_smoke.1768122186
Short name	T483
Test name
Test status
Simulation time	5652070888 ps
CPU time	7.39 seconds
Started	Jan 03 01:17:54 PM PST 24
Finished	Jan 03 01:18:20 PM PST 24
Peak memory	200716 kb
Host	smart-ab4b8042-ee6c-41d7-a4d4-f5045b44867a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1768122186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.1768122186
Directory	/workspace/40.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/40.adc_ctrl_stress_all.2381937851
Short name	T720
Test name
Test status
Simulation time	339710910175 ps
CPU time	729.79 seconds
Started	Jan 03 01:17:36 PM PST 24
Finished	Jan 03 01:29:54 PM PST 24
Peak memory	200848 kb
Host	smart-2afc32c9-c829-4e27-9ad4-f7c242008d8c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381937851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all .2381937851
Directory	/workspace/40.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/41.adc_ctrl_alert_test.1608944811
Short name	T439
Test name
Test status
Simulation time	314802264 ps
CPU time	0.8 seconds
Started	Jan 03 01:17:52 PM PST 24
Finished	Jan 03 01:18:11 PM PST 24
Peak memory	200636 kb
Host	smart-d12dab14-7b0d-4662-8165-93351cee9286
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608944811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.1608944811
Directory	/workspace/41.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/41.adc_ctrl_filters_both.3468237894
Short name	T61
Test name
Test status
Simulation time	165915847256 ps
CPU time	362.38 seconds
Started	Jan 03 01:17:54 PM PST 24
Finished	Jan 03 01:24:15 PM PST 24
Peak memory	200900 kb
Host	smart-34466ed1-76b2-4eea-bd60-12136e1151c8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3468237894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.3468237894
Directory	/workspace/41.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/41.adc_ctrl_filters_interrupt.1355724253
Short name	T219
Test name
Test status
Simulation time	329111715489 ps
CPU time	702.46 seconds
Started	Jan 03 01:17:54 PM PST 24
Finished	Jan 03 01:29:55 PM PST 24
Peak memory	200808 kb
Host	smart-6a15a1d5-cc62-469c-a472-3f4937fc446b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1355724253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.1355724253
Directory	/workspace/41.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.2146680198
Short name	T138
Test name
Test status
Simulation time	491594061193 ps
CPU time	617.82 seconds
Started	Jan 03 01:17:51 PM PST 24
Finished	Jan 03 01:28:27 PM PST 24
Peak memory	200872 kb
Host	smart-06cf7a08-4107-4225-8cfb-7a14b20387bc
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146680198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru pt_fixed.2146680198
Directory	/workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/41.adc_ctrl_filters_polled.4131206778
Short name	T290
Test name
Test status
Simulation time	166951710453 ps
CPU time	395.41 seconds
Started	Jan 03 01:17:45 PM PST 24
Finished	Jan 03 01:24:26 PM PST 24
Peak memory	200888 kb
Host	smart-eaae8d19-a13f-4322-8a53-79cfa9ebfcf8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4131206778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.4131206778
Directory	/workspace/41.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.3686128026
Short name	T127
Test name
Test status
Simulation time	328901634954 ps
CPU time	736.59 seconds
Started	Jan 03 01:17:38 PM PST 24
Finished	Jan 03 01:29:58 PM PST 24
Peak memory	200848 kb
Host	smart-434ebfb6-5431-4868-b1d5-e0736d0179b4
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686128026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix ed.3686128026
Directory	/workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/41.adc_ctrl_filters_wakeup.3108186843
Short name	T294
Test name
Test status
Simulation time	508451570545 ps
CPU time	324.23 seconds
Started	Jan 03 01:18:02 PM PST 24
Finished	Jan 03 01:23:37 PM PST 24
Peak memory	200964 kb
Host	smart-f6fc32ac-6634-4318-a18f-e3b29eec0324
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108186843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters _wakeup.3108186843
Directory	/workspace/41.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.2916451584
Short name	T452
Test name
Test status
Simulation time	164654073422 ps
CPU time	198.88 seconds
Started	Jan 03 01:17:55 PM PST 24
Finished	Jan 03 01:21:31 PM PST 24
Peak memory	200792 kb
Host	smart-084418a2-43c2-43be-88e4-216189c634f7
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916451584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41 .adc_ctrl_filters_wakeup_fixed.2916451584
Directory	/workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/41.adc_ctrl_fsm_reset.2980009636
Short name	T541
Test name
Test status
Simulation time	90944970688 ps
CPU time	310.3 seconds
Started	Jan 03 01:17:58 PM PST 24
Finished	Jan 03 01:23:23 PM PST 24
Peak memory	201272 kb
Host	smart-f67a878e-639c-4c71-9fa6-d9c2c3372309
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2980009636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.2980009636
Directory	/workspace/41.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/41.adc_ctrl_lowpower_counter.2907811982
Short name	T444
Test name
Test status
Simulation time	37730264458 ps
CPU time	5.62 seconds
Started	Jan 03 01:18:01 PM PST 24
Finished	Jan 03 01:18:18 PM PST 24
Peak memory	200760 kb
Host	smart-33676d4c-427c-4b0a-abae-1c36348688d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2907811982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.2907811982
Directory	/workspace/41.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/41.adc_ctrl_poweron_counter.3586058899
Short name	T545
Test name
Test status
Simulation time	5034694669 ps
CPU time	6.28 seconds
Started	Jan 03 01:18:04 PM PST 24
Finished	Jan 03 01:18:21 PM PST 24
Peak memory	200732 kb
Host	smart-83bfdd93-e6b8-47f1-9564-9f4baea740fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3586058899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.3586058899
Directory	/workspace/41.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/41.adc_ctrl_smoke.3433858939
Short name	T603
Test name
Test status
Simulation time	5880221398 ps
CPU time	3.88 seconds
Started	Jan 03 01:17:35 PM PST 24
Finished	Jan 03 01:17:43 PM PST 24
Peak memory	200708 kb
Host	smart-8e892c90-b033-4a00-ab5e-f8a0025221db
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3433858939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.3433858939
Directory	/workspace/41.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/41.adc_ctrl_stress_all.1558665685
Short name	T768
Test name
Test status
Simulation time	369114085871 ps
CPU time	277.37 seconds
Started	Jan 03 01:18:06 PM PST 24
Finished	Jan 03 01:23:06 PM PST 24
Peak memory	200888 kb
Host	smart-681006f3-3228-43a5-a69e-04d56ecc50b0
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558665685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all .1558665685
Directory	/workspace/41.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.2996381627
Short name	T745
Test name
Test status
Simulation time	177778811612 ps
CPU time	174.05 seconds
Started	Jan 03 01:18:09 PM PST 24
Finished	Jan 03 01:21:29 PM PST 24
Peak memory	209248 kb
Host	smart-62a7c72e-ae2a-4872-b1a8-e79875aad694
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996381627 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.2996381627
Directory	/workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/42.adc_ctrl_alert_test.1764950781
Short name	T575
Test name
Test status
Simulation time	498567286 ps
CPU time	1.73 seconds
Started	Jan 03 01:18:00 PM PST 24
Finished	Jan 03 01:18:15 PM PST 24
Peak memory	200656 kb
Host	smart-bdb544d2-d474-4be5-af98-94ea39ecc2fa
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764950781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.1764950781
Directory	/workspace/42.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/42.adc_ctrl_clock_gating.2960037382
Short name	T579
Test name
Test status
Simulation time	164481585782 ps
CPU time	101.71 seconds
Started	Jan 03 01:18:19 PM PST 24
Finished	Jan 03 01:20:28 PM PST 24
Peak memory	200908 kb
Host	smart-8209a106-584a-46ff-bd2c-14eca8b1e7be
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960037382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat ing.2960037382
Directory	/workspace/42.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/42.adc_ctrl_filters_both.2919629413
Short name	T230
Test name
Test status
Simulation time	322077330821 ps
CPU time	208.46 seconds
Started	Jan 03 01:18:11 PM PST 24
Finished	Jan 03 01:22:10 PM PST 24
Peak memory	200948 kb
Host	smart-d8b6dc1c-9588-495c-8d17-2df22c50b054
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2919629413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.2919629413
Directory	/workspace/42.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/42.adc_ctrl_filters_interrupt.2046338566
Short name	T721
Test name
Test status
Simulation time	163938680660 ps
CPU time	342.45 seconds
Started	Jan 03 01:18:06 PM PST 24
Finished	Jan 03 01:24:11 PM PST 24
Peak memory	200888 kb
Host	smart-5f793eaf-f294-4196-b790-e97c2af9e456
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2046338566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.2046338566
Directory	/workspace/42.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.4080759167
Short name	T624
Test name
Test status
Simulation time	166910463452 ps
CPU time	182.52 seconds
Started	Jan 03 01:18:08 PM PST 24
Finished	Jan 03 01:21:36 PM PST 24
Peak memory	200864 kb
Host	smart-af203751-95a1-43b3-8dca-dff4783761af
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080759167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru pt_fixed.4080759167
Directory	/workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/42.adc_ctrl_filters_polled.1331592318
Short name	T837
Test name
Test status
Simulation time	493976400761 ps
CPU time	82.53 seconds
Started	Jan 03 01:18:03 PM PST 24
Finished	Jan 03 01:19:35 PM PST 24
Peak memory	200848 kb
Host	smart-94e6f5cc-cf01-403e-b493-43adf27036af
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1331592318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.1331592318
Directory	/workspace/42.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.2373846939
Short name	T587
Test name
Test status
Simulation time	490839447584 ps
CPU time	272.09 seconds
Started	Jan 03 01:18:04 PM PST 24
Finished	Jan 03 01:22:47 PM PST 24
Peak memory	200860 kb
Host	smart-1b9a7919-c5ab-4ef0-949b-1ff3e1c217a9
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373846939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix ed.2373846939
Directory	/workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/42.adc_ctrl_filters_wakeup.1558791719
Short name	T299
Test name
Test status
Simulation time	509102518598 ps
CPU time	381.06 seconds
Started	Jan 03 01:18:14 PM PST 24
Finished	Jan 03 01:25:11 PM PST 24
Peak memory	200912 kb
Host	smart-18100839-210f-4420-8f05-26a61b8692d7
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558791719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters _wakeup.1558791719
Directory	/workspace/42.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.2626196333
Short name	T736
Test name
Test status
Simulation time	160308381740 ps
CPU time	248.75 seconds
Started	Jan 03 01:18:00 PM PST 24
Finished	Jan 03 01:22:21 PM PST 24
Peak memory	200824 kb
Host	smart-1c4624cf-678c-4491-be60-9797b4a46304
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626196333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42 .adc_ctrl_filters_wakeup_fixed.2626196333
Directory	/workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/42.adc_ctrl_fsm_reset.1486048159
Short name	T788
Test name
Test status
Simulation time	98261375183 ps
CPU time	373.49 seconds
Started	Jan 03 01:17:56 PM PST 24
Finished	Jan 03 01:24:26 PM PST 24
Peak memory	201376 kb
Host	smart-5a22c239-2e5e-45b5-a17e-62fc4cff3a46
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1486048159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.1486048159
Directory	/workspace/42.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/42.adc_ctrl_poweron_counter.3026254847
Short name	T503
Test name
Test status
Simulation time	2964863144 ps
CPU time	2.45 seconds
Started	Jan 03 01:18:17 PM PST 24
Finished	Jan 03 01:18:53 PM PST 24
Peak memory	200704 kb
Host	smart-e1b4e712-1ce2-48da-bebd-971dd197ae47
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3026254847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.3026254847
Directory	/workspace/42.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/42.adc_ctrl_smoke.258903560
Short name	T520
Test name
Test status
Simulation time	6109198898 ps
CPU time	13.78 seconds
Started	Jan 03 01:18:18 PM PST 24
Finished	Jan 03 01:19:04 PM PST 24
Peak memory	200684 kb
Host	smart-e1bad716-a0c9-4085-b0d8-d06010462eb4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=258903560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.258903560
Directory	/workspace/42.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/43.adc_ctrl_alert_test.4271165591
Short name	T554
Test name
Test status
Simulation time	503194784 ps
CPU time	0.94 seconds
Started	Jan 03 01:18:47 PM PST 24
Finished	Jan 03 01:19:04 PM PST 24
Peak memory	200672 kb
Host	smart-6a92c410-7aeb-4605-9e66-edde03984953
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271165591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.4271165591
Directory	/workspace/43.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/43.adc_ctrl_clock_gating.4083534158
Short name	T227
Test name
Test status
Simulation time	175445153436 ps
CPU time	29.71 seconds
Started	Jan 03 01:18:34 PM PST 24
Finished	Jan 03 01:19:24 PM PST 24
Peak memory	200852 kb
Host	smart-4a7d1dd3-c882-4a94-a2a5-cf3019522659
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083534158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat ing.4083534158
Directory	/workspace/43.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/43.adc_ctrl_filters_both.764814000
Short name	T663
Test name
Test status
Simulation time	166722542742 ps
CPU time	372.68 seconds
Started	Jan 03 01:18:43 PM PST 24
Finished	Jan 03 01:25:13 PM PST 24
Peak memory	200984 kb
Host	smart-9469a48b-2292-430c-992f-42ac57f1b580
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=764814000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.764814000
Directory	/workspace/43.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/43.adc_ctrl_filters_interrupt.2730025296
Short name	T210
Test name
Test status
Simulation time	493311797933 ps
CPU time	325.88 seconds
Started	Jan 03 01:18:07 PM PST 24
Finished	Jan 03 01:23:57 PM PST 24
Peak memory	200952 kb
Host	smart-ae0354a9-e9b1-494e-be71-b6ced525c698
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2730025296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.2730025296
Directory	/workspace/43.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.2682463072
Short name	T470
Test name
Test status
Simulation time	163714333688 ps
CPU time	199.99 seconds
Started	Jan 03 01:18:01 PM PST 24
Finished	Jan 03 01:21:33 PM PST 24
Peak memory	200872 kb
Host	smart-bb8c1d12-07c6-4df0-bdad-b96fdd9695fb
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682463072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru pt_fixed.2682463072
Directory	/workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/43.adc_ctrl_filters_polled.1214727297
Short name	T246
Test name
Test status
Simulation time	330311359404 ps
CPU time	501.94 seconds
Started	Jan 03 01:17:49 PM PST 24
Finished	Jan 03 01:26:25 PM PST 24
Peak memory	200900 kb
Host	smart-2905a666-95fe-4788-8adb-d4c1c0faa291
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1214727297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.1214727297
Directory	/workspace/43.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/43.adc_ctrl_filters_wakeup.3213504652
Short name	T567
Test name
Test status
Simulation time	182398511739 ps
CPU time	411.17 seconds
Started	Jan 03 01:18:40 PM PST 24
Finished	Jan 03 01:25:50 PM PST 24
Peak memory	200804 kb
Host	smart-9cfa5e5a-b599-460c-a557-ad804982ba1e
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213504652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters _wakeup.3213504652
Directory	/workspace/43.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.2939835917
Short name	T709
Test name
Test status
Simulation time	324467473778 ps
CPU time	175.54 seconds
Started	Jan 03 01:18:42 PM PST 24
Finished	Jan 03 01:21:56 PM PST 24
Peak memory	200832 kb
Host	smart-5465add4-2318-4c4b-9a60-ebad5b4f9ff2
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939835917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43 .adc_ctrl_filters_wakeup_fixed.2939835917
Directory	/workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/43.adc_ctrl_fsm_reset.3894483208
Short name	T186
Test name
Test status
Simulation time	89741410794 ps
CPU time	473.33 seconds
Started	Jan 03 01:18:46 PM PST 24
Finished	Jan 03 01:26:56 PM PST 24
Peak memory	201336 kb
Host	smart-6a3f6b36-feea-4d8a-b6cf-bb5258bbc605
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3894483208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.3894483208
Directory	/workspace/43.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/43.adc_ctrl_lowpower_counter.3554670761
Short name	T410
Test name
Test status
Simulation time	26337045508 ps
CPU time	15.89 seconds
Started	Jan 03 01:18:45 PM PST 24
Finished	Jan 03 01:19:18 PM PST 24
Peak memory	200712 kb
Host	smart-e3b8389e-e1e8-4b19-9013-30a4b3978eb4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3554670761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.3554670761
Directory	/workspace/43.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/43.adc_ctrl_poweron_counter.3409744802
Short name	T532
Test name
Test status
Simulation time	4009027686 ps
CPU time	5.02 seconds
Started	Jan 03 01:18:43 PM PST 24
Finished	Jan 03 01:19:06 PM PST 24
Peak memory	200744 kb
Host	smart-e64f2eb6-d193-4a8e-a87c-cd55ad1d9558
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3409744802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.3409744802
Directory	/workspace/43.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/43.adc_ctrl_smoke.578677563
Short name	T794
Test name
Test status
Simulation time	5713568652 ps
CPU time	13.68 seconds
Started	Jan 03 01:18:07 PM PST 24
Finished	Jan 03 01:18:45 PM PST 24
Peak memory	200688 kb
Host	smart-8fcfd23c-7ebe-4f4f-91ad-70d2b13e49e5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=578677563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.578677563
Directory	/workspace/43.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/43.adc_ctrl_stress_all.3573480366
Short name	T333
Test name
Test status
Simulation time	417122540828 ps
CPU time	491.31 seconds
Started	Jan 03 01:18:57 PM PST 24
Finished	Jan 03 01:27:17 PM PST 24
Peak memory	200852 kb
Host	smart-da3ec6ff-8430-4fda-8d43-6e09ae201f34
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573480366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all .3573480366
Directory	/workspace/43.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.1644374636
Short name	T805
Test name
Test status
Simulation time	192548635180 ps
CPU time	166.05 seconds
Started	Jan 03 01:18:45 PM PST 24
Finished	Jan 03 01:21:48 PM PST 24
Peak memory	209572 kb
Host	smart-6a69a6be-98cc-4784-a99d-e9f0301be33c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644374636 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.1644374636
Directory	/workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/44.adc_ctrl_alert_test.4262134290
Short name	T665
Test name
Test status
Simulation time	316528144 ps
CPU time	1.11 seconds
Started	Jan 03 01:18:44 PM PST 24
Finished	Jan 03 01:19:02 PM PST 24
Peak memory	200660 kb
Host	smart-47916b78-d35a-49db-bc20-d50594819906
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262134290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.4262134290
Directory	/workspace/44.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/44.adc_ctrl_clock_gating.2425881375
Short name	T338
Test name
Test status
Simulation time	499864673019 ps
CPU time	1104.76 seconds
Started	Jan 03 01:19:05 PM PST 24
Finished	Jan 03 01:37:37 PM PST 24
Peak memory	200888 kb
Host	smart-f103f890-1de2-4082-999a-e05bfd8f9946
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425881375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat ing.2425881375
Directory	/workspace/44.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/44.adc_ctrl_filters_both.455070861
Short name	T336
Test name
Test status
Simulation time	330063240483 ps
CPU time	81.24 seconds
Started	Jan 03 01:19:03 PM PST 24
Finished	Jan 03 01:20:32 PM PST 24
Peak memory	200980 kb
Host	smart-3f082ed1-1411-48d9-9fd1-a5f4d9d84517
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=455070861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.455070861
Directory	/workspace/44.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/44.adc_ctrl_filters_interrupt.186129489
Short name	T283
Test name
Test status
Simulation time	326685443739 ps
CPU time	811.09 seconds
Started	Jan 03 01:19:06 PM PST 24
Finished	Jan 03 01:32:45 PM PST 24
Peak memory	200996 kb
Host	smart-f7b39c02-2dae-44b0-8cdf-56dae620a6f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=186129489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.186129489
Directory	/workspace/44.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.2595393039
Short name	T161
Test name
Test status
Simulation time	492947801873 ps
CPU time	1145.64 seconds
Started	Jan 03 01:19:00 PM PST 24
Finished	Jan 03 01:38:14 PM PST 24
Peak memory	200896 kb
Host	smart-4055e5ce-2a71-4e4e-8076-44678bbee0bc
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595393039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru pt_fixed.2595393039
Directory	/workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/44.adc_ctrl_filters_polled.1523543571
Short name	T657
Test name
Test status
Simulation time	489555247124 ps
CPU time	1130.02 seconds
Started	Jan 03 01:19:04 PM PST 24
Finished	Jan 03 01:38:02 PM PST 24
Peak memory	200956 kb
Host	smart-8ca9975a-6157-4ab2-a57d-7705f8a63b4f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1523543571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.1523543571
Directory	/workspace/44.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.2226697519
Short name	T581
Test name
Test status
Simulation time	317792018055 ps
CPU time	372.93 seconds
Started	Jan 03 01:19:04 PM PST 24
Finished	Jan 03 01:25:25 PM PST 24
Peak memory	200952 kb
Host	smart-87c71525-fd47-4775-b0b0-f99bffdd24af
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226697519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix ed.2226697519
Directory	/workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/44.adc_ctrl_filters_wakeup.3117502557
Short name	T151
Test name
Test status
Simulation time	493221868338 ps
CPU time	351.52 seconds
Started	Jan 03 01:19:05 PM PST 24
Finished	Jan 03 01:25:04 PM PST 24
Peak memory	200896 kb
Host	smart-c6c2de92-dcf5-45aa-a4c5-56ddac9da966
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117502557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters _wakeup.3117502557
Directory	/workspace/44.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.1547375371
Short name	T440
Test name
Test status
Simulation time	497018656745 ps
CPU time	1112.82 seconds
Started	Jan 03 01:19:04 PM PST 24
Finished	Jan 03 01:37:45 PM PST 24
Peak memory	200740 kb
Host	smart-139a8d05-341c-4f9c-bd72-02ee34118b25
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547375371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44 .adc_ctrl_filters_wakeup_fixed.1547375371
Directory	/workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/44.adc_ctrl_fsm_reset.1452989719
Short name	T741
Test name
Test status
Simulation time	114667151476 ps
CPU time	611.02 seconds
Started	Jan 03 01:18:44 PM PST 24
Finished	Jan 03 01:29:12 PM PST 24
Peak memory	201052 kb
Host	smart-bee474ca-4d52-4891-a88b-ad287511d2c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1452989719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.1452989719
Directory	/workspace/44.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/44.adc_ctrl_lowpower_counter.2800934812
Short name	T478
Test name
Test status
Simulation time	29865276478 ps
CPU time	75.31 seconds
Started	Jan 03 01:18:44 PM PST 24
Finished	Jan 03 01:20:17 PM PST 24
Peak memory	200756 kb
Host	smart-4d7d1ee5-3d17-4b6a-a521-01a28d922a0b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2800934812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.2800934812
Directory	/workspace/44.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/44.adc_ctrl_poweron_counter.3519511068
Short name	T465
Test name
Test status
Simulation time	2931659444 ps
CPU time	2.41 seconds
Started	Jan 03 01:18:44 PM PST 24
Finished	Jan 03 01:19:04 PM PST 24
Peak memory	200540 kb
Host	smart-2d451ceb-a634-4141-a414-c376bb272b1d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3519511068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.3519511068
Directory	/workspace/44.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/44.adc_ctrl_smoke.562937742
Short name	T633
Test name
Test status
Simulation time	5886583347 ps
CPU time	7.25 seconds
Started	Jan 03 01:19:00 PM PST 24
Finished	Jan 03 01:19:16 PM PST 24
Peak memory	200676 kb
Host	smart-87ad9f46-cd82-42ea-95e4-5f5b2e799c21
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=562937742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.562937742
Directory	/workspace/44.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/44.adc_ctrl_stress_all.3013265952
Short name	T682
Test name
Test status
Simulation time	331159271385 ps
CPU time	811.71 seconds
Started	Jan 03 01:18:45 PM PST 24
Finished	Jan 03 01:32:34 PM PST 24
Peak memory	200856 kb
Host	smart-0b7ecea6-26d1-4db4-a209-acac1733842f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013265952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all .3013265952
Directory	/workspace/44.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/45.adc_ctrl_alert_test.2472929694
Short name	T589
Test name
Test status
Simulation time	426546506 ps
CPU time	1.66 seconds
Started	Jan 03 01:18:43 PM PST 24
Finished	Jan 03 01:19:03 PM PST 24
Peak memory	200692 kb
Host	smart-26b8001c-b6ca-4090-a235-4c60a21dcfb8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472929694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.2472929694
Directory	/workspace/45.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/45.adc_ctrl_clock_gating.4085864729
Short name	T527
Test name
Test status
Simulation time	164302996928 ps
CPU time	101.01 seconds
Started	Jan 03 01:19:03 PM PST 24
Finished	Jan 03 01:20:51 PM PST 24
Peak memory	200948 kb
Host	smart-d1abb9ca-d40b-40d3-8a24-99b3b6d764d3
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085864729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat ing.4085864729
Directory	/workspace/45.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/45.adc_ctrl_filters_both.1292716335
Short name	T308
Test name
Test status
Simulation time	160138504901 ps
CPU time	116.86 seconds
Started	Jan 03 01:19:04 PM PST 24
Finished	Jan 03 01:21:09 PM PST 24
Peak memory	200824 kb
Host	smart-080af946-8180-441f-a63d-0c5d9087320c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1292716335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.1292716335
Directory	/workspace/45.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/45.adc_ctrl_filters_interrupt.1851462261
Short name	T303
Test name
Test status
Simulation time	492591364815 ps
CPU time	948.4 seconds
Started	Jan 03 01:18:57 PM PST 24
Finished	Jan 03 01:34:54 PM PST 24
Peak memory	200904 kb
Host	smart-bf6a8f93-52c5-4861-b357-2c6b1ea7669f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1851462261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.1851462261
Directory	/workspace/45.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.2604929963
Short name	T605
Test name
Test status
Simulation time	164321306515 ps
CPU time	96.86 seconds
Started	Jan 03 01:19:01 PM PST 24
Finished	Jan 03 01:20:46 PM PST 24
Peak memory	200812 kb
Host	smart-132399e9-c846-4289-ad9f-eb944a4c488c
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604929963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru pt_fixed.2604929963
Directory	/workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/45.adc_ctrl_filters_polled.2312829212
Short name	T726
Test name
Test status
Simulation time	162954736310 ps
CPU time	106.52 seconds
Started	Jan 03 01:18:46 PM PST 24
Finished	Jan 03 01:20:49 PM PST 24
Peak memory	200844 kb
Host	smart-16253cdf-40ca-4d79-8a7d-6644daceaa1f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2312829212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.2312829212
Directory	/workspace/45.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.1485398100
Short name	T838
Test name
Test status
Simulation time	324364030396 ps
CPU time	507.78 seconds
Started	Jan 03 01:19:00 PM PST 24
Finished	Jan 03 01:27:37 PM PST 24
Peak memory	200892 kb
Host	smart-9d896279-08ef-40ea-b803-d04047a7bfa3
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485398100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix ed.1485398100
Directory	/workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/45.adc_ctrl_filters_wakeup.1132425088
Short name	T270
Test name
Test status
Simulation time	165598754836 ps
CPU time	53.61 seconds
Started	Jan 03 01:19:01 PM PST 24
Finished	Jan 03 01:20:03 PM PST 24
Peak memory	200940 kb
Host	smart-66d039de-fa18-43b2-9c22-c8246f2c642a
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132425088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters _wakeup.1132425088
Directory	/workspace/45.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.3244101461
Short name	T132
Test name
Test status
Simulation time	159671121821 ps
CPU time	81.89 seconds
Started	Jan 03 01:18:59 PM PST 24
Finished	Jan 03 01:20:30 PM PST 24
Peak memory	200908 kb
Host	smart-14a9425b-8444-4e30-83a4-b78b7ded278a
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244101461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45 .adc_ctrl_filters_wakeup_fixed.3244101461
Directory	/workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/45.adc_ctrl_fsm_reset.496902487
Short name	T93
Test name
Test status
Simulation time	108050505571 ps
CPU time	531.08 seconds
Started	Jan 03 01:19:03 PM PST 24
Finished	Jan 03 01:28:02 PM PST 24
Peak memory	201204 kb
Host	smart-5c434e45-8f0e-4463-8714-aead6ee3c268
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=496902487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.496902487
Directory	/workspace/45.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/45.adc_ctrl_lowpower_counter.983548385
Short name	T405
Test name
Test status
Simulation time	24694069473 ps
CPU time	17.16 seconds
Started	Jan 03 01:19:03 PM PST 24
Finished	Jan 03 01:19:28 PM PST 24
Peak memory	200628 kb
Host	smart-8b6f8a98-de7a-4b56-b971-3fafe39b6cbd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=983548385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.983548385
Directory	/workspace/45.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/45.adc_ctrl_poweron_counter.1589709468
Short name	T739
Test name
Test status
Simulation time	4813810951 ps
CPU time	3.79 seconds
Started	Jan 03 01:19:02 PM PST 24
Finished	Jan 03 01:19:14 PM PST 24
Peak memory	200732 kb
Host	smart-c067266e-53b9-4715-9a6a-87be946f4284
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1589709468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.1589709468
Directory	/workspace/45.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/45.adc_ctrl_smoke.3733821002
Short name	T547
Test name
Test status
Simulation time	5833472539 ps
CPU time	4.18 seconds
Started	Jan 03 01:19:00 PM PST 24
Finished	Jan 03 01:19:12 PM PST 24
Peak memory	200684 kb
Host	smart-42afe6de-c9e8-4ee4-b084-ce664619549b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3733821002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.3733821002
Directory	/workspace/45.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.4061018600
Short name	T790
Test name
Test status
Simulation time	29643869362 ps
CPU time	48.85 seconds
Started	Jan 03 01:18:27 PM PST 24
Finished	Jan 03 01:19:39 PM PST 24
Peak memory	209164 kb
Host	smart-8c5d1100-efe1-41b0-afd9-63c1cc09bbda
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061018600 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.4061018600
Directory	/workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/46.adc_ctrl_alert_test.2249931776
Short name	T558
Test name
Test status
Simulation time	425286865 ps
CPU time	0.86 seconds
Started	Jan 03 01:18:59 PM PST 24
Finished	Jan 03 01:19:08 PM PST 24
Peak memory	200688 kb
Host	smart-1f6e0327-e029-446b-9bd0-4968b30fe9aa
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249931776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.2249931776
Directory	/workspace/46.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/46.adc_ctrl_clock_gating.1342491985
Short name	T744
Test name
Test status
Simulation time	162032144633 ps
CPU time	171.38 seconds
Started	Jan 03 01:18:49 PM PST 24
Finished	Jan 03 01:21:54 PM PST 24
Peak memory	200984 kb
Host	smart-02845e30-c8a1-4594-933b-81d56cfd81f7
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342491985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat ing.1342491985
Directory	/workspace/46.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/46.adc_ctrl_filters_both.2902234049
Short name	T99
Test name
Test status
Simulation time	161248101045 ps
CPU time	103.26 seconds
Started	Jan 03 01:19:02 PM PST 24
Finished	Jan 03 01:20:53 PM PST 24
Peak memory	200996 kb
Host	smart-21e8b536-06de-493c-93d2-95b8932234ed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2902234049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.2902234049
Directory	/workspace/46.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/46.adc_ctrl_filters_interrupt.2137656302
Short name	T539
Test name
Test status
Simulation time	167802063085 ps
CPU time	279.37 seconds
Started	Jan 03 01:18:46 PM PST 24
Finished	Jan 03 01:23:42 PM PST 24
Peak memory	200764 kb
Host	smart-cf5ae6cd-f000-4155-b8b2-01ee32d8eefc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2137656302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.2137656302
Directory	/workspace/46.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.1352033103
Short name	T779
Test name
Test status
Simulation time	163160134008 ps
CPU time	188.74 seconds
Started	Jan 03 01:18:47 PM PST 24
Finished	Jan 03 01:22:12 PM PST 24
Peak memory	200904 kb
Host	smart-ef144910-8fcd-4faa-a058-4245d2630ad8
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352033103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru pt_fixed.1352033103
Directory	/workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/46.adc_ctrl_filters_polled.110451831
Short name	T613
Test name
Test status
Simulation time	490011342485 ps
CPU time	566.51 seconds
Started	Jan 03 01:18:41 PM PST 24
Finished	Jan 03 01:28:26 PM PST 24
Peak memory	200820 kb
Host	smart-33d29492-93f2-45ab-9bd7-c615872c578b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=110451831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.110451831
Directory	/workspace/46.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.2808718205
Short name	T626
Test name
Test status
Simulation time	494147859805 ps
CPU time	1215.01 seconds
Started	Jan 03 01:18:47 PM PST 24
Finished	Jan 03 01:39:18 PM PST 24
Peak memory	200828 kb
Host	smart-00d1d7ba-c6f3-48c7-a11e-65ec1dc6ccee
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808718205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix ed.2808718205
Directory	/workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.3157928901
Short name	T820
Test name
Test status
Simulation time	494121330457 ps
CPU time	1047.05 seconds
Started	Jan 03 01:19:02 PM PST 24
Finished	Jan 03 01:36:37 PM PST 24
Peak memory	200812 kb
Host	smart-56c35e58-4e41-4605-996e-ebe36e90cb65
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157928901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46 .adc_ctrl_filters_wakeup_fixed.3157928901
Directory	/workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/46.adc_ctrl_fsm_reset.3837152903
Short name	T187
Test name
Test status
Simulation time	72362425457 ps
CPU time	273.41 seconds
Started	Jan 03 01:18:58 PM PST 24
Finished	Jan 03 01:23:40 PM PST 24
Peak memory	201380 kb
Host	smart-91ac4c61-c1c4-4fc0-b12d-a9b202da9c33
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3837152903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.3837152903
Directory	/workspace/46.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/46.adc_ctrl_lowpower_counter.415768899
Short name	T585
Test name
Test status
Simulation time	26630391840 ps
CPU time	31.46 seconds
Started	Jan 03 01:18:45 PM PST 24
Finished	Jan 03 01:19:33 PM PST 24
Peak memory	200728 kb
Host	smart-f509e7ab-be94-4f85-b454-643242cfdef2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=415768899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.415768899
Directory	/workspace/46.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/46.adc_ctrl_poweron_counter.1000362512
Short name	T611
Test name
Test status
Simulation time	4292376908 ps
CPU time	8.01 seconds
Started	Jan 03 01:19:01 PM PST 24
Finished	Jan 03 01:19:18 PM PST 24
Peak memory	200692 kb
Host	smart-895ed4df-b620-44b1-b943-05ab95e6d6ec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1000362512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.1000362512
Directory	/workspace/46.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/46.adc_ctrl_smoke.3852498858
Short name	T680
Test name
Test status
Simulation time	5686743331 ps
CPU time	5.87 seconds
Started	Jan 03 01:18:39 PM PST 24
Finished	Jan 03 01:19:04 PM PST 24
Peak memory	200696 kb
Host	smart-60f2a3a7-2aba-4cc9-a9b3-043f782253c7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3852498858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.3852498858
Directory	/workspace/46.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.3186595034
Short name	T602
Test name
Test status
Simulation time	363006209322 ps
CPU time	89.89 seconds
Started	Jan 03 01:19:00 PM PST 24
Finished	Jan 03 01:20:39 PM PST 24
Peak memory	201032 kb
Host	smart-3aef21a1-d909-41f3-9661-f2dbaf5c2e98
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186595034 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.3186595034
Directory	/workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/47.adc_ctrl_alert_test.2950595641
Short name	T493
Test name
Test status
Simulation time	418914651 ps
CPU time	1.53 seconds
Started	Jan 03 01:18:39 PM PST 24
Finished	Jan 03 01:19:00 PM PST 24
Peak memory	200672 kb
Host	smart-42ccc4df-36b3-401d-aa19-ed29bcfcaa20
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950595641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.2950595641
Directory	/workspace/47.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/47.adc_ctrl_clock_gating.3294794319
Short name	T313
Test name
Test status
Simulation time	160841714782 ps
CPU time	377.97 seconds
Started	Jan 03 01:18:41 PM PST 24
Finished	Jan 03 01:25:17 PM PST 24
Peak memory	200892 kb
Host	smart-e38100e8-2d3d-4e65-bdd6-4991bd6b9208
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294794319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat ing.3294794319
Directory	/workspace/47.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/47.adc_ctrl_filters_both.203689531
Short name	T286
Test name
Test status
Simulation time	161473251850 ps
CPU time	99.16 seconds
Started	Jan 03 01:18:46 PM PST 24
Finished	Jan 03 01:20:41 PM PST 24
Peak memory	200972 kb
Host	smart-effbdb13-7af4-4074-884f-2ef7d3ce76fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=203689531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.203689531
Directory	/workspace/47.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.2313074667
Short name	T180
Test name
Test status
Simulation time	485853699478 ps
CPU time	292.6 seconds
Started	Jan 03 01:19:01 PM PST 24
Finished	Jan 03 01:24:02 PM PST 24
Peak memory	200896 kb
Host	smart-19a66971-1a75-40a4-aa01-b92da7c71055
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313074667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru pt_fixed.2313074667
Directory	/workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/47.adc_ctrl_filters_polled.2499855444
Short name	T142
Test name
Test status
Simulation time	327536901130 ps
CPU time	74.4 seconds
Started	Jan 03 01:19:01 PM PST 24
Finished	Jan 03 01:20:23 PM PST 24
Peak memory	200912 kb
Host	smart-a1091f25-a2e2-40e2-9891-679c2cba7671
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2499855444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.2499855444
Directory	/workspace/47.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.9843348
Short name	T606
Test name
Test status
Simulation time	495214532621 ps
CPU time	555.7 seconds
Started	Jan 03 01:19:02 PM PST 24
Finished	Jan 03 01:28:26 PM PST 24
Peak memory	200868 kb
Host	smart-b5d8c416-5158-447a-bef8-d8c8ae54c799
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=9843348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fixed.9843348
Directory	/workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/47.adc_ctrl_filters_wakeup.2959011205
Short name	T16
Test name
Test status
Simulation time	330307558057 ps
CPU time	673.6 seconds
Started	Jan 03 01:19:03 PM PST 24
Finished	Jan 03 01:30:25 PM PST 24
Peak memory	200960 kb
Host	smart-6203c0c2-5fb1-413b-8b29-0a087e4aa74c
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959011205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters _wakeup.2959011205
Directory	/workspace/47.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.291269948
Short name	T450
Test name
Test status
Simulation time	329193096575 ps
CPU time	408.65 seconds
Started	Jan 03 01:19:03 PM PST 24
Finished	Jan 03 01:25:59 PM PST 24
Peak memory	200848 kb
Host	smart-6787acaf-5a7a-4d4c-8f0b-3e39de16b559
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291269948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ =adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47. adc_ctrl_filters_wakeup_fixed.291269948
Directory	/workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/47.adc_ctrl_fsm_reset.3329341213
Short name	T189
Test name
Test status
Simulation time	112142321940 ps
CPU time	607.56 seconds
Started	Jan 03 01:18:43 PM PST 24
Finished	Jan 03 01:29:08 PM PST 24
Peak memory	201288 kb
Host	smart-62ed45fb-8869-4357-a4c1-e85a221b1a74
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3329341213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.3329341213
Directory	/workspace/47.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/47.adc_ctrl_lowpower_counter.3291889078
Short name	T468
Test name
Test status
Simulation time	33187570840 ps
CPU time	75.39 seconds
Started	Jan 03 01:19:02 PM PST 24
Finished	Jan 03 01:20:26 PM PST 24
Peak memory	200720 kb
Host	smart-ed360647-d27d-425a-9b79-a773f3f03f89
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3291889078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.3291889078
Directory	/workspace/47.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/47.adc_ctrl_poweron_counter.1424157933
Short name	T706
Test name
Test status
Simulation time	3764169150 ps
CPU time	1.65 seconds
Started	Jan 03 01:18:40 PM PST 24
Finished	Jan 03 01:19:01 PM PST 24
Peak memory	200664 kb
Host	smart-22d3dbaa-c47b-4639-87a5-3f35dbfa7f65
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1424157933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.1424157933
Directory	/workspace/47.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/47.adc_ctrl_smoke.2511577256
Short name	T666
Test name
Test status
Simulation time	5717472435 ps
CPU time	14 seconds
Started	Jan 03 01:19:00 PM PST 24
Finished	Jan 03 01:19:23 PM PST 24
Peak memory	200612 kb
Host	smart-20c10a5e-aeb8-440c-a08a-f9135b7f091b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2511577256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.2511577256
Directory	/workspace/47.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/47.adc_ctrl_stress_all.2285479697
Short name	T217
Test name
Test status
Simulation time	178362585367 ps
CPU time	414.73 seconds
Started	Jan 03 01:18:41 PM PST 24
Finished	Jan 03 01:25:54 PM PST 24
Peak memory	200948 kb
Host	smart-85813b1e-9654-4b21-b33b-c3cc7f7f04f4
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285479697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all .2285479697
Directory	/workspace/47.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/48.adc_ctrl_alert_test.1397593123
Short name	T825
Test name
Test status
Simulation time	497586510 ps
CPU time	1.8 seconds
Started	Jan 03 01:18:44 PM PST 24
Finished	Jan 03 01:19:03 PM PST 24
Peak memory	200592 kb
Host	smart-5e1d064c-e3b3-4375-82dd-19c75ab96cae
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397593123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.1397593123
Directory	/workspace/48.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/48.adc_ctrl_clock_gating.346980876
Short name	T692
Test name
Test status
Simulation time	159718821817 ps
CPU time	94.52 seconds
Started	Jan 03 01:18:44 PM PST 24
Finished	Jan 03 01:20:36 PM PST 24
Peak memory	200908 kb
Host	smart-a41cf751-902e-4912-a4bb-6d495d512616
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346980876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gati ng.346980876
Directory	/workspace/48.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.3675060066
Short name	T411
Test name
Test status
Simulation time	163178368663 ps
CPU time	183.56 seconds
Started	Jan 03 01:18:45 PM PST 24
Finished	Jan 03 01:22:05 PM PST 24
Peak memory	200908 kb
Host	smart-9a9287f2-80bd-4011-a219-a9c8885d9542
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675060066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru pt_fixed.3675060066
Directory	/workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/48.adc_ctrl_filters_polled.3546609101
Short name	T751
Test name
Test status
Simulation time	326844809169 ps
CPU time	424.36 seconds
Started	Jan 03 01:18:42 PM PST 24
Finished	Jan 03 01:26:04 PM PST 24
Peak memory	200848 kb
Host	smart-9f392535-4aa2-474a-b5fa-ba40c08b2991
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3546609101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.3546609101
Directory	/workspace/48.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.2342615057
Short name	T11
Test name
Test status
Simulation time	160584975153 ps
CPU time	357.23 seconds
Started	Jan 03 01:18:42 PM PST 24
Finished	Jan 03 01:24:57 PM PST 24
Peak memory	200912 kb
Host	smart-9e972a0a-fa37-49ba-82d5-ee1c38fbab55
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342615057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix ed.2342615057
Directory	/workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/48.adc_ctrl_filters_wakeup.2606455146
Short name	T98
Test name
Test status
Simulation time	509829235922 ps
CPU time	1218.15 seconds
Started	Jan 03 01:18:42 PM PST 24
Finished	Jan 03 01:39:18 PM PST 24
Peak memory	200908 kb
Host	smart-f907a14b-0e45-444b-9502-91a045118c7b
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606455146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters _wakeup.2606455146
Directory	/workspace/48.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.3215840320
Short name	T641
Test name
Test status
Simulation time	486894976780 ps
CPU time	266.17 seconds
Started	Jan 03 01:18:44 PM PST 24
Finished	Jan 03 01:23:27 PM PST 24
Peak memory	200800 kb
Host	smart-5d62e991-43d5-4f97-ab24-22604d95ecca
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215840320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48 .adc_ctrl_filters_wakeup_fixed.3215840320
Directory	/workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/48.adc_ctrl_fsm_reset.908499654
Short name	T496
Test name
Test status
Simulation time	88987889467 ps
CPU time	363.52 seconds
Started	Jan 03 01:18:47 PM PST 24
Finished	Jan 03 01:25:06 PM PST 24
Peak memory	201340 kb
Host	smart-f6b92c25-997e-4cc8-9cb9-cd0547ef0a45
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=908499654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.908499654
Directory	/workspace/48.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/48.adc_ctrl_lowpower_counter.1974806287
Short name	T102
Test name
Test status
Simulation time	40241093819 ps
CPU time	14.86 seconds
Started	Jan 03 01:18:45 PM PST 24
Finished	Jan 03 01:19:17 PM PST 24
Peak memory	200712 kb
Host	smart-217b410b-bc55-4e8f-ae0b-6e8ac97615ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1974806287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.1974806287
Directory	/workspace/48.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/48.adc_ctrl_poweron_counter.2797509533
Short name	T754
Test name
Test status
Simulation time	4818273091 ps
CPU time	11.73 seconds
Started	Jan 03 01:18:44 PM PST 24
Finished	Jan 03 01:19:13 PM PST 24
Peak memory	200768 kb
Host	smart-91ddcaab-2af6-46f1-9228-f0b2aa101e0b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2797509533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.2797509533
Directory	/workspace/48.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/48.adc_ctrl_smoke.1578443484
Short name	T454
Test name
Test status
Simulation time	5868045738 ps
CPU time	4.52 seconds
Started	Jan 03 01:18:43 PM PST 24
Finished	Jan 03 01:19:05 PM PST 24
Peak memory	200712 kb
Host	smart-b0970715-48cd-46be-8c0b-034238e9c336
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1578443484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.1578443484
Directory	/workspace/48.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.3296674932
Short name	T22
Test name
Test status
Simulation time	93176117967 ps
CPU time	127.13 seconds
Started	Jan 03 01:18:45 PM PST 24
Finished	Jan 03 01:21:09 PM PST 24
Peak memory	209556 kb
Host	smart-c795c52c-e79f-44d1-878b-411ec90894ad
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296674932 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.3296674932
Directory	/workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/49.adc_ctrl_alert_test.939994702
Short name	T486
Test name
Test status
Simulation time	409130382 ps
CPU time	0.82 seconds
Started	Jan 03 01:19:01 PM PST 24
Finished	Jan 03 01:19:11 PM PST 24
Peak memory	200624 kb
Host	smart-6f83e35e-402e-4611-b5f6-253ed10da565
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939994702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.939994702
Directory	/workspace/49.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/49.adc_ctrl_clock_gating.2293784205
Short name	T156
Test name
Test status
Simulation time	331014156500 ps
CPU time	108.33 seconds
Started	Jan 03 01:18:47 PM PST 24
Finished	Jan 03 01:20:51 PM PST 24
Peak memory	200940 kb
Host	smart-31077e8c-542c-4099-94e4-ddff18f89b21
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293784205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat ing.2293784205
Directory	/workspace/49.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/49.adc_ctrl_filters_both.3847248650
Short name	T330
Test name
Test status
Simulation time	499415004845 ps
CPU time	601.29 seconds
Started	Jan 03 01:18:49 PM PST 24
Finished	Jan 03 01:29:04 PM PST 24
Peak memory	200960 kb
Host	smart-ae7cb0a5-2aaa-41ee-990d-1b236bdee62e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3847248650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.3847248650
Directory	/workspace/49.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/49.adc_ctrl_filters_interrupt.1178565081
Short name	T153
Test name
Test status
Simulation time	331375130956 ps
CPU time	217.68 seconds
Started	Jan 03 01:18:50 PM PST 24
Finished	Jan 03 01:22:41 PM PST 24
Peak memory	200924 kb
Host	smart-f623fc13-1703-4de6-be17-3deff48c997a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1178565081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.1178565081
Directory	/workspace/49.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.128610825
Short name	T731
Test name
Test status
Simulation time	323846261925 ps
CPU time	389.3 seconds
Started	Jan 03 01:18:59 PM PST 24
Finished	Jan 03 01:25:37 PM PST 24
Peak memory	200804 kb
Host	smart-68b273d1-0cef-42d6-8e2e-a087e5647101
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=128610825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrup t_fixed.128610825
Directory	/workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/49.adc_ctrl_filters_polled.3140730252
Short name	T577
Test name
Test status
Simulation time	161487935650 ps
CPU time	366.6 seconds
Started	Jan 03 01:18:57 PM PST 24
Finished	Jan 03 01:25:12 PM PST 24
Peak memory	200952 kb
Host	smart-be39e50f-5a2b-49b8-ab67-6b3caf390151
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3140730252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.3140730252
Directory	/workspace/49.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.2123787371
Short name	T23
Test name
Test status
Simulation time	166223283479 ps
CPU time	212.33 seconds
Started	Jan 03 01:18:46 PM PST 24
Finished	Jan 03 01:22:35 PM PST 24
Peak memory	200820 kb
Host	smart-7981fd0d-e557-40e5-99a0-a427a19e66e0
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123787371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix ed.2123787371
Directory	/workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/49.adc_ctrl_filters_wakeup.2910994269
Short name	T773
Test name
Test status
Simulation time	341919786609 ps
CPU time	252.26 seconds
Started	Jan 03 01:18:47 PM PST 24
Finished	Jan 03 01:23:15 PM PST 24
Peak memory	200940 kb
Host	smart-e7f30438-d459-45f4-bb73-0ed3e1e62b20
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910994269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters _wakeup.2910994269
Directory	/workspace/49.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.21692052
Short name	T604
Test name
Test status
Simulation time	324705264016 ps
CPU time	185.39 seconds
Started	Jan 03 01:18:45 PM PST 24
Finished	Jan 03 01:22:07 PM PST 24
Peak memory	200896 kb
Host	smart-f065d395-b3e9-4716-9f46-ab6e816ccf3f
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21692052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ= adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.a dc_ctrl_filters_wakeup_fixed.21692052
Directory	/workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/49.adc_ctrl_fsm_reset.447360441
Short name	T793
Test name
Test status
Simulation time	80232393836 ps
CPU time	322.79 seconds
Started	Jan 03 01:19:04 PM PST 24
Finished	Jan 03 01:24:35 PM PST 24
Peak memory	201352 kb
Host	smart-b6f575cb-9b11-4195-94f3-64b4609f0f62
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=447360441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.447360441
Directory	/workspace/49.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/49.adc_ctrl_lowpower_counter.4125084836
Short name	T697
Test name
Test status
Simulation time	28740185681 ps
CPU time	34.42 seconds
Started	Jan 03 01:19:04 PM PST 24
Finished	Jan 03 01:19:46 PM PST 24
Peak memory	200740 kb
Host	smart-691d809e-8471-4e74-868d-7cc92a04ae7f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4125084836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.4125084836
Directory	/workspace/49.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/49.adc_ctrl_poweron_counter.1081774811
Short name	T414
Test name
Test status
Simulation time	5223537808 ps
CPU time	4.27 seconds
Started	Jan 03 01:18:48 PM PST 24
Finished	Jan 03 01:19:07 PM PST 24
Peak memory	200768 kb
Host	smart-c890b580-9ab8-4ad0-8e29-5b2211ffe0e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1081774811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.1081774811
Directory	/workspace/49.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/49.adc_ctrl_smoke.4244506001
Short name	T92
Test name
Test status
Simulation time	5809872423 ps
CPU time	14.78 seconds
Started	Jan 03 01:18:45 PM PST 24
Finished	Jan 03 01:19:17 PM PST 24
Peak memory	200764 kb
Host	smart-abbf1298-5bd1-4f0d-a32a-e0adcd8c1f9f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4244506001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.4244506001
Directory	/workspace/49.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/49.adc_ctrl_stress_all.3214657293
Short name	T730
Test name
Test status
Simulation time	206791090126 ps
CPU time	79.76 seconds
Started	Jan 03 01:19:03 PM PST 24
Finished	Jan 03 01:20:30 PM PST 24
Peak memory	200800 kb
Host	smart-b74d3e4c-6284-4123-935f-6b12aebd9f5d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214657293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all .3214657293
Directory	/workspace/49.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.987970079
Short name	T300
Test name
Test status
Simulation time	32263147603 ps
CPU time	37.32 seconds
Started	Jan 03 01:19:02 PM PST 24
Finished	Jan 03 01:19:47 PM PST 24
Peak memory	209120 kb
Host	smart-cd329c63-d4ea-4225-89a2-d85cbef5fa2c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987970079 -assert nopo stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.987970079
Directory	/workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/5.adc_ctrl_alert_test.902785828
Short name	T471
Test name
Test status
Simulation time	414005219 ps
CPU time	1.52 seconds
Started	Jan 03 01:14:56 PM PST 24
Finished	Jan 03 01:15:59 PM PST 24
Peak memory	200632 kb
Host	smart-804cdf2f-dfe2-40c8-bfea-bf10bf801b23
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902785828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.902785828
Directory	/workspace/5.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/5.adc_ctrl_filters_both.249009332
Short name	T267
Test name
Test status
Simulation time	500884931659 ps
CPU time	1061.12 seconds
Started	Jan 03 01:14:41 PM PST 24
Finished	Jan 03 01:33:14 PM PST 24
Peak memory	200924 kb
Host	smart-63ed07b8-780c-414f-b5ef-5e504df80184
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=249009332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.249009332
Directory	/workspace/5.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/5.adc_ctrl_filters_interrupt.464452369
Short name	T717
Test name
Test status
Simulation time	155950297137 ps
CPU time	91.27 seconds
Started	Jan 03 01:14:40 PM PST 24
Finished	Jan 03 01:17:00 PM PST 24
Peak memory	200968 kb
Host	smart-5bb00e96-547a-4b6b-84c3-13ebeebaa6c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=464452369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.464452369
Directory	/workspace/5.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.1675235842
Short name	T699
Test name
Test status
Simulation time	488348257290 ps
CPU time	565.29 seconds
Started	Jan 03 01:14:40 PM PST 24
Finished	Jan 03 01:24:56 PM PST 24
Peak memory	200832 kb
Host	smart-2b88e7e6-8b51-4755-a66c-b424367014c1
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675235842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup t_fixed.1675235842
Directory	/workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/5.adc_ctrl_filters_polled.525771597
Short name	T761
Test name
Test status
Simulation time	335236503675 ps
CPU time	804.55 seconds
Started	Jan 03 01:14:45 PM PST 24
Finished	Jan 03 01:29:04 PM PST 24
Peak memory	200908 kb
Host	smart-b8a76f7a-e63f-4c6c-9e87-7a00e867b6be
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=525771597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.525771597
Directory	/workspace/5.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.3129141672
Short name	T129
Test name
Test status
Simulation time	329082057855 ps
CPU time	333.17 seconds
Started	Jan 03 01:14:39 PM PST 24
Finished	Jan 03 01:21:00 PM PST 24
Peak memory	200872 kb
Host	smart-695298bf-5970-4814-be0e-0a86e3df613b
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129141672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe d.3129141672
Directory	/workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/5.adc_ctrl_filters_wakeup.4059185153
Short name	T327
Test name
Test status
Simulation time	326115420147 ps
CPU time	698.8 seconds
Started	Jan 03 01:14:45 PM PST 24
Finished	Jan 03 01:27:17 PM PST 24
Peak memory	200932 kb
Host	smart-14380477-41c2-4fd8-b2ea-1f5fcf6efe43
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059185153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_ wakeup.4059185153
Directory	/workspace/5.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.869319808
Short name	T235
Test name
Test status
Simulation time	169702802801 ps
CPU time	394.18 seconds
Started	Jan 03 01:14:45 PM PST 24
Finished	Jan 03 01:22:14 PM PST 24
Peak memory	200856 kb
Host	smart-997b8134-30e1-471a-b92a-3f37bd36e6a6
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869319808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ =adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.a dc_ctrl_filters_wakeup_fixed.869319808
Directory	/workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/5.adc_ctrl_fsm_reset.2670347841
Short name	T351
Test name
Test status
Simulation time	65000243355 ps
CPU time	278.02 seconds
Started	Jan 03 01:14:46 PM PST 24
Finished	Jan 03 01:20:19 PM PST 24
Peak memory	201364 kb
Host	smart-76173c07-ba84-4f11-9eaa-30934791249f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2670347841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.2670347841
Directory	/workspace/5.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/5.adc_ctrl_lowpower_counter.1264043928
Short name	T502
Test name
Test status
Simulation time	28501726799 ps
CPU time	69.19 seconds
Started	Jan 03 01:14:46 PM PST 24
Finished	Jan 03 01:16:50 PM PST 24
Peak memory	200672 kb
Host	smart-c6fee4f0-1aab-4a93-b3b4-3d7186bf1029
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1264043928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.1264043928
Directory	/workspace/5.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/5.adc_ctrl_poweron_counter.276297437
Short name	T550
Test name
Test status
Simulation time	2962581747 ps
CPU time	7.79 seconds
Started	Jan 03 01:14:45 PM PST 24
Finished	Jan 03 01:15:46 PM PST 24
Peak memory	200716 kb
Host	smart-ebef372a-ae99-4436-88a5-fa5dcf27ba9d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=276297437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.276297437
Directory	/workspace/5.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/5.adc_ctrl_smoke.99281386
Short name	T653
Test name
Test status
Simulation time	6037487027 ps
CPU time	15.14 seconds
Started	Jan 03 01:14:53 PM PST 24
Finished	Jan 03 01:16:09 PM PST 24
Peak memory	200652 kb
Host	smart-0c2e6037-2f4f-417b-afd4-b771e459a82f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=99281386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.99281386
Directory	/workspace/5.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.276475652
Short name	T753
Test name
Test status
Simulation time	73363309600 ps
CPU time	161.7 seconds
Started	Jan 03 01:14:42 PM PST 24
Finished	Jan 03 01:18:15 PM PST 24
Peak memory	209744 kb
Host	smart-f857f3e4-8a65-405b-b36d-2ac6eb2f58b9
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276475652 -assert nopo stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.276475652
Directory	/workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/6.adc_ctrl_alert_test.2324096956
Short name	T667
Test name
Test status
Simulation time	526198378 ps
CPU time	1.71 seconds
Started	Jan 03 01:14:57 PM PST 24
Finished	Jan 03 01:16:01 PM PST 24
Peak memory	200656 kb
Host	smart-0eb65e6f-9c17-461d-8c5d-165810a83de2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324096956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.2324096956
Directory	/workspace/6.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/6.adc_ctrl_clock_gating.387648452
Short name	T705
Test name
Test status
Simulation time	162433277658 ps
CPU time	376.44 seconds
Started	Jan 03 01:14:49 PM PST 24
Finished	Jan 03 01:22:04 PM PST 24
Peak memory	200920 kb
Host	smart-3dee5ca7-48da-4b88-8a89-073cbc65ed55
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387648452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gatin g.387648452
Directory	/workspace/6.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/6.adc_ctrl_filters_both.3572054302
Short name	T780
Test name
Test status
Simulation time	495528053638 ps
CPU time	319.56 seconds
Started	Jan 03 01:14:52 PM PST 24
Finished	Jan 03 01:21:11 PM PST 24
Peak memory	200968 kb
Host	smart-db09f1fd-9930-4782-92a9-83e681d7bf42
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3572054302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.3572054302
Directory	/workspace/6.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/6.adc_ctrl_filters_interrupt.1498633084
Short name	T280
Test name
Test status
Simulation time	489569625587 ps
CPU time	600.53 seconds
Started	Jan 03 01:14:55 PM PST 24
Finished	Jan 03 01:25:57 PM PST 24
Peak memory	200868 kb
Host	smart-6ae64fc6-98aa-45b8-8ea0-70545838c902
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1498633084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.1498633084
Directory	/workspace/6.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.209502817
Short name	T511
Test name
Test status
Simulation time	486108860762 ps
CPU time	1138.11 seconds
Started	Jan 03 01:15:01 PM PST 24
Finished	Jan 03 01:35:04 PM PST 24
Peak memory	200800 kb
Host	smart-d9b8cb94-2e24-4b7c-b93a-08cca7803fb5
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=209502817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt _fixed.209502817
Directory	/workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/6.adc_ctrl_filters_polled.3390890985
Short name	T708
Test name
Test status
Simulation time	167098588736 ps
CPU time	109.71 seconds
Started	Jan 03 01:14:54 PM PST 24
Finished	Jan 03 01:17:45 PM PST 24
Peak memory	200956 kb
Host	smart-a9fa93d0-a42b-4ba1-a627-4144f878d6a7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3390890985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.3390890985
Directory	/workspace/6.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.843313886
Short name	T481
Test name
Test status
Simulation time	487636256719 ps
CPU time	1225.66 seconds
Started	Jan 03 01:14:53 PM PST 24
Finished	Jan 03 01:36:19 PM PST 24
Peak memory	200856 kb
Host	smart-e83a3204-81f2-422a-9b9a-47798793c3ce
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=843313886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixed .843313886
Directory	/workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/6.adc_ctrl_filters_wakeup.1908415859
Short name	T340
Test name
Test status
Simulation time	332972128410 ps
CPU time	382.64 seconds
Started	Jan 03 01:15:00 PM PST 24
Finished	Jan 03 01:22:26 PM PST 24
Peak memory	200980 kb
Host	smart-857b64e4-04a8-47bd-99f7-ab31990880fd
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908415859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_ wakeup.1908415859
Directory	/workspace/6.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.830141413
Short name	T448
Test name
Test status
Simulation time	325764267597 ps
CPU time	544.64 seconds
Started	Jan 03 01:14:57 PM PST 24
Finished	Jan 03 01:25:04 PM PST 24
Peak memory	200808 kb
Host	smart-a20abc70-814e-44a0-80bf-821af741bdc4
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830141413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ =adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.a dc_ctrl_filters_wakeup_fixed.830141413
Directory	/workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/6.adc_ctrl_fsm_reset.3332713564
Short name	T56
Test name
Test status
Simulation time	136240135143 ps
CPU time	630.26 seconds
Started	Jan 03 01:15:06 PM PST 24
Finished	Jan 03 01:26:40 PM PST 24
Peak memory	201436 kb
Host	smart-702184dd-aa30-4e33-af32-092fb73f5e59
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3332713564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.3332713564
Directory	/workspace/6.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/6.adc_ctrl_lowpower_counter.1041256652
Short name	T830
Test name
Test status
Simulation time	28216184424 ps
CPU time	17.13 seconds
Started	Jan 03 01:15:07 PM PST 24
Finished	Jan 03 01:16:29 PM PST 24
Peak memory	200608 kb
Host	smart-cb34d896-215d-495e-80c5-48ba13d2e4b3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1041256652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.1041256652
Directory	/workspace/6.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/6.adc_ctrl_poweron_counter.695650533
Short name	T426
Test name
Test status
Simulation time	3733744600 ps
CPU time	7.61 seconds
Started	Jan 03 01:14:57 PM PST 24
Finished	Jan 03 01:16:07 PM PST 24
Peak memory	200692 kb
Host	smart-239319a6-b148-4aa8-a66b-a42bb33d378d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=695650533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.695650533
Directory	/workspace/6.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/6.adc_ctrl_smoke.3615434441
Short name	T148
Test name
Test status
Simulation time	5667016273 ps
CPU time	3.9 seconds
Started	Jan 03 01:14:49 PM PST 24
Finished	Jan 03 01:15:50 PM PST 24
Peak memory	200612 kb
Host	smart-b8833011-2690-4f2b-bd31-40406f83551f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3615434441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.3615434441
Directory	/workspace/6.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.3316632079
Short name	T595
Test name
Test status
Simulation time	478874049181 ps
CPU time	303.2 seconds
Started	Jan 03 01:14:53 PM PST 24
Finished	Jan 03 01:20:57 PM PST 24
Peak memory	217768 kb
Host	smart-72015681-510d-4a3f-9c92-8131359aa3bf
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316632079 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.3316632079
Directory	/workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/7.adc_ctrl_alert_test.4262052600
Short name	T44
Test name
Test status
Simulation time	502880360 ps
CPU time	1.09 seconds
Started	Jan 03 01:15:04 PM PST 24
Finished	Jan 03 01:16:08 PM PST 24
Peak memory	200532 kb
Host	smart-00ec2df4-f67a-408b-b368-4626dfb4529f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262052600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.4262052600
Directory	/workspace/7.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/7.adc_ctrl_clock_gating.796675869
Short name	T847
Test name
Test status
Simulation time	490251231188 ps
CPU time	264.37 seconds
Started	Jan 03 01:15:02 PM PST 24
Finished	Jan 03 01:20:30 PM PST 24
Peak memory	200856 kb
Host	smart-6dbf1f0a-3baf-4c6f-9f3a-d392eb9fc2a1
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796675869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gatin g.796675869
Directory	/workspace/7.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/7.adc_ctrl_filters_both.923889861
Short name	T297
Test name
Test status
Simulation time	490582466649 ps
CPU time	1102.66 seconds
Started	Jan 03 01:15:09 PM PST 24
Finished	Jan 03 01:34:37 PM PST 24
Peak memory	200940 kb
Host	smart-6f73d10a-9709-4c8b-b225-b532649dba1a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=923889861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.923889861
Directory	/workspace/7.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.2997067665
Short name	T140
Test name
Test status
Simulation time	328681601199 ps
CPU time	795.01 seconds
Started	Jan 03 01:15:01 PM PST 24
Finished	Jan 03 01:29:21 PM PST 24
Peak memory	200832 kb
Host	smart-9302297c-22a2-4da7-b0e0-cfd6b7430232
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997067665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup t_fixed.2997067665
Directory	/workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/7.adc_ctrl_filters_polled.660631806
Short name	T208
Test name
Test status
Simulation time	495213570721 ps
CPU time	1064.91 seconds
Started	Jan 03 01:15:01 PM PST 24
Finished	Jan 03 01:33:50 PM PST 24
Peak memory	200916 kb
Host	smart-ea960892-547f-4ac0-94b3-d1f6358b7e08
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=660631806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.660631806
Directory	/workspace/7.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.1338359834
Short name	T782
Test name
Test status
Simulation time	327854892872 ps
CPU time	403 seconds
Started	Jan 03 01:14:52 PM PST 24
Finished	Jan 03 01:22:36 PM PST 24
Peak memory	200804 kb
Host	smart-ce0c5286-b105-46a7-b692-3023c67964cb
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338359834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe d.1338359834
Directory	/workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/7.adc_ctrl_filters_wakeup.3828253043
Short name	T818
Test name
Test status
Simulation time	331148163632 ps
CPU time	315.58 seconds
Started	Jan 03 01:15:10 PM PST 24
Finished	Jan 03 01:21:31 PM PST 24
Peak memory	200956 kb
Host	smart-186c07aa-ce60-441a-a726-6753fa996756
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828253043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_ wakeup.3828253043
Directory	/workspace/7.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.1937956978
Short name	T642
Test name
Test status
Simulation time	167195860339 ps
CPU time	364.07 seconds
Started	Jan 03 01:14:40 PM PST 24
Finished	Jan 03 01:21:33 PM PST 24
Peak memory	200892 kb
Host	smart-8cfb8fde-a061-48a1-91a0-cf0de51287f6
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937956978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7. adc_ctrl_filters_wakeup_fixed.1937956978
Directory	/workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/7.adc_ctrl_fsm_reset.4177651180
Short name	T676
Test name
Test status
Simulation time	83296804753 ps
CPU time	457.43 seconds
Started	Jan 03 01:15:05 PM PST 24
Finished	Jan 03 01:23:47 PM PST 24
Peak memory	201324 kb
Host	smart-76054883-c6ba-4b75-9c29-18a1e06bf547
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4177651180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.4177651180
Directory	/workspace/7.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/7.adc_ctrl_lowpower_counter.738072328
Short name	T559
Test name
Test status
Simulation time	38373631599 ps
CPU time	84.18 seconds
Started	Jan 03 01:15:08 PM PST 24
Finished	Jan 03 01:17:38 PM PST 24
Peak memory	200768 kb
Host	smart-e20d67a7-7062-4a7a-b3b1-2e3261f3c4fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=738072328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.738072328
Directory	/workspace/7.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/7.adc_ctrl_poweron_counter.1397272284
Short name	T548
Test name
Test status
Simulation time	4154753259 ps
CPU time	10.28 seconds
Started	Jan 03 01:15:13 PM PST 24
Finished	Jan 03 01:16:29 PM PST 24
Peak memory	200692 kb
Host	smart-a0faffed-21c8-40a7-abcc-8d1a61ee7fd0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1397272284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.1397272284
Directory	/workspace/7.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/7.adc_ctrl_smoke.1255001334
Short name	T137
Test name
Test status
Simulation time	5909695831 ps
CPU time	7.68 seconds
Started	Jan 03 01:15:09 PM PST 24
Finished	Jan 03 01:16:22 PM PST 24
Peak memory	200344 kb
Host	smart-cf07e9ac-234a-4d84-9923-2b300393ef3d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1255001334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.1255001334
Directory	/workspace/7.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/7.adc_ctrl_stress_all.3636108934
Short name	T248
Test name
Test status
Simulation time	277785428158 ps
CPU time	401.9 seconds
Started	Jan 03 01:15:02 PM PST 24
Finished	Jan 03 01:22:48 PM PST 24
Peak memory	201332 kb
Host	smart-aa763617-11bd-4365-9eba-5b4ea8052276
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636108934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all. 3636108934
Directory	/workspace/7.adc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.3810874570
Short name	T807
Test name
Test status
Simulation time	19801216518 ps
CPU time	51.56 seconds
Started	Jan 03 01:15:05 PM PST 24
Finished	Jan 03 01:17:00 PM PST 24
Peak memory	209424 kb
Host	smart-44781378-d17f-4866-bf04-856330268ec2
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810874570 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.3810874570
Directory	/workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/8.adc_ctrl_alert_test.4274652970
Short name	T703
Test name
Test status
Simulation time	360135783 ps
CPU time	0.79 seconds
Started	Jan 03 01:14:45 PM PST 24
Finished	Jan 03 01:15:41 PM PST 24
Peak memory	200636 kb
Host	smart-be169920-f986-4260-bfd8-9ad6be0196d8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274652970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.4274652970
Directory	/workspace/8.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/8.adc_ctrl_clock_gating.1343762107
Short name	T101
Test name
Test status
Simulation time	486863452598 ps
CPU time	79.37 seconds
Started	Jan 03 01:14:56 PM PST 24
Finished	Jan 03 01:17:17 PM PST 24
Peak memory	200756 kb
Host	smart-89d04653-637c-47db-894d-d9ef3bfab83b
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343762107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati ng.1343762107
Directory	/workspace/8.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/8.adc_ctrl_filters_both.142921631
Short name	T224
Test name
Test status
Simulation time	322464088956 ps
CPU time	382.2 seconds
Started	Jan 03 01:14:51 PM PST 24
Finished	Jan 03 01:22:12 PM PST 24
Peak memory	200860 kb
Host	smart-cbc48e57-96a8-482e-9d11-2f4baec27020
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=142921631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.142921631
Directory	/workspace/8.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.2131560735
Short name	T810
Test name
Test status
Simulation time	162123918895 ps
CPU time	97.18 seconds
Started	Jan 03 01:15:07 PM PST 24
Finished	Jan 03 01:17:49 PM PST 24
Peak memory	200900 kb
Host	smart-5df5d4d2-ae5a-4bcb-b944-ce57a8d4544e
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131560735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup t_fixed.2131560735
Directory	/workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/8.adc_ctrl_filters_polled.380008520
Short name	T331
Test name
Test status
Simulation time	488187889096 ps
CPU time	1176.26 seconds
Started	Jan 03 01:15:12 PM PST 24
Finished	Jan 03 01:35:54 PM PST 24
Peak memory	200812 kb
Host	smart-6d6f6e69-26da-4f04-b25c-523f6c8fdac3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=380008520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.380008520
Directory	/workspace/8.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.3710107213
Short name	T662
Test name
Test status
Simulation time	324236930420 ps
CPU time	209.23 seconds
Started	Jan 03 01:15:11 PM PST 24
Finished	Jan 03 01:19:46 PM PST 24
Peak memory	200832 kb
Host	smart-c1f24913-bc48-4dde-a229-021fcd63ffa7
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710107213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe d.3710107213
Directory	/workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/8.adc_ctrl_filters_wakeup.3015313457
Short name	T126
Test name
Test status
Simulation time	499529526135 ps
CPU time	288.06 seconds
Started	Jan 03 01:14:50 PM PST 24
Finished	Jan 03 01:20:38 PM PST 24
Peak memory	200780 kb
Host	smart-1bd4fabe-1eeb-4584-bd23-12ada2b7ce4a
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015313457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_ wakeup.3015313457
Directory	/workspace/8.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.982754294
Short name	T446
Test name
Test status
Simulation time	320917845399 ps
CPU time	208.17 seconds
Started	Jan 03 01:14:41 PM PST 24
Finished	Jan 03 01:18:59 PM PST 24
Peak memory	200964 kb
Host	smart-da853162-def3-4e87-baa5-fb1c6ae98c7d
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982754294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ =adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.a dc_ctrl_filters_wakeup_fixed.982754294
Directory	/workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/8.adc_ctrl_fsm_reset.1699211247
Short name	T197
Test name
Test status
Simulation time	107903209523 ps
CPU time	390.85 seconds
Started	Jan 03 01:14:40 PM PST 24
Finished	Jan 03 01:22:01 PM PST 24
Peak memory	201272 kb
Host	smart-181d79b7-20ff-4349-a738-3cad561ef1c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1699211247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.1699211247
Directory	/workspace/8.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/8.adc_ctrl_lowpower_counter.154676513
Short name	T114
Test name
Test status
Simulation time	23890396415 ps
CPU time	55.63 seconds
Started	Jan 03 01:14:51 PM PST 24
Finished	Jan 03 01:16:46 PM PST 24
Peak memory	200632 kb
Host	smart-70da7bc8-664d-4aca-9ddb-14f52664ae0b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=154676513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.154676513
Directory	/workspace/8.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/8.adc_ctrl_poweron_counter.2322482122
Short name	T660
Test name
Test status
Simulation time	3483902463 ps
CPU time	8.7 seconds
Started	Jan 03 01:14:48 PM PST 24
Finished	Jan 03 01:15:55 PM PST 24
Peak memory	200760 kb
Host	smart-0bf3ebcc-95d1-4c22-82c1-39bd46dbf120
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2322482122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.2322482122
Directory	/workspace/8.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/8.adc_ctrl_smoke.262616143
Short name	T521
Test name
Test status
Simulation time	5770744843 ps
CPU time	3.88 seconds
Started	Jan 03 01:15:10 PM PST 24
Finished	Jan 03 01:16:20 PM PST 24
Peak memory	200688 kb
Host	smart-3eb652bb-380c-40cc-8824-a9bf50b43930
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=262616143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.262616143
Directory	/workspace/8.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.3510473076
Short name	T307
Test name
Test status
Simulation time	26624256996 ps
CPU time	58.06 seconds
Started	Jan 03 01:14:44 PM PST 24
Finished	Jan 03 01:16:36 PM PST 24
Peak memory	209108 kb
Host	smart-34422ea5-b1ee-477f-949c-24945594c5d1
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510473076 -assert nop ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.3510473076
Directory	/workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/9.adc_ctrl_alert_test.3632031103
Short name	T501
Test name
Test status
Simulation time	550895855 ps
CPU time	0.92 seconds
Started	Jan 03 01:15:01 PM PST 24
Finished	Jan 03 01:16:06 PM PST 24
Peak memory	200612 kb
Host	smart-b9cff71b-dc60-4370-bcab-b64636fb910b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632031103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.3632031103
Directory	/workspace/9.adc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/9.adc_ctrl_clock_gating.2389211627
Short name	T679
Test name
Test status
Simulation time	160603861261 ps
CPU time	95.65 seconds
Started	Jan 03 01:14:51 PM PST 24
Finished	Jan 03 01:17:26 PM PST 24
Peak memory	200952 kb
Host	smart-175a0e7e-844e-4a16-9b81-b14990394ece
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389211627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati ng.2389211627
Directory	/workspace/9.adc_ctrl_clock_gating/latest

Test location	/workspace/coverage/default/9.adc_ctrl_filters_both.3218782967
Short name	T318
Test name
Test status
Simulation time	163653561660 ps
CPU time	30.08 seconds
Started	Jan 03 01:14:57 PM PST 24
Finished	Jan 03 01:16:29 PM PST 24
Peak memory	200944 kb
Host	smart-65bb7c1d-d942-43a8-976d-9b952addd822
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3218782967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.3218782967
Directory	/workspace/9.adc_ctrl_filters_both/latest

Test location	/workspace/coverage/default/9.adc_ctrl_filters_interrupt.606800599
Short name	T332
Test name
Test status
Simulation time	490581567455 ps
CPU time	1115.77 seconds
Started	Jan 03 01:14:53 PM PST 24
Finished	Jan 03 01:34:30 PM PST 24
Peak memory	200932 kb
Host	smart-9680184e-8835-47d0-9f1c-f5257d211b2a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=606800599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.606800599
Directory	/workspace/9.adc_ctrl_filters_interrupt/latest

Test location	/workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.500944482
Short name	T803
Test name
Test status
Simulation time	167029290177 ps
CPU time	112.34 seconds
Started	Jan 03 01:14:50 PM PST 24
Finished	Jan 03 01:17:41 PM PST 24
Peak memory	200736 kb
Host	smart-4bcede7b-6a4d-456c-b88d-da664b60d062
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=500944482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt _fixed.500944482
Directory	/workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location	/workspace/coverage/default/9.adc_ctrl_filters_polled.3670044545
Short name	T100
Test name
Test status
Simulation time	329442466457 ps
CPU time	88.8 seconds
Started	Jan 03 01:14:41 PM PST 24
Finished	Jan 03 01:17:02 PM PST 24
Peak memory	200908 kb
Host	smart-d84f2964-102a-4051-bdbd-30c7c8198591
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3670044545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.3670044545
Directory	/workspace/9.adc_ctrl_filters_polled/latest

Test location	/workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.2487204190
Short name	T849
Test name
Test status
Simulation time	500532495849 ps
CPU time	1235.25 seconds
Started	Jan 03 01:14:49 PM PST 24
Finished	Jan 03 01:36:22 PM PST 24
Peak memory	200804 kb
Host	smart-cec3116e-bf22-48f1-88c6-4f8d105a5e8e
User	root
Command	/workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487204190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe d.2487204190
Directory	/workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location	/workspace/coverage/default/9.adc_ctrl_filters_wakeup.3569223662
Short name	T727
Test name
Test status
Simulation time	160217497509 ps
CPU time	181.07 seconds
Started	Jan 03 01:14:53 PM PST 24
Finished	Jan 03 01:18:55 PM PST 24
Peak memory	200912 kb
Host	smart-93708011-3f77-4f9a-beea-460edfbd9d49
User	root
Command	/workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569223662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_ wakeup.3569223662
Directory	/workspace/9.adc_ctrl_filters_wakeup/latest

Test location	/workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.331769294
Short name	T425
Test name
Test status
Simulation time	166302274007 ps
CPU time	403.19 seconds
Started	Jan 03 01:14:53 PM PST 24
Finished	Jan 03 01:22:37 PM PST 24
Peak memory	200904 kb
Host	smart-dab57439-cef8-4a3a-8d70-dd160a11f90f
User	root
Command	/workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331769294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ =adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.a dc_ctrl_filters_wakeup_fixed.331769294
Directory	/workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location	/workspace/coverage/default/9.adc_ctrl_fsm_reset.945741805
Short name	T183
Test name
Test status
Simulation time	114441697625 ps
CPU time	620.66 seconds
Started	Jan 03 01:15:01 PM PST 24
Finished	Jan 03 01:26:26 PM PST 24
Peak memory	201260 kb
Host	smart-5d309da1-74e9-4116-a609-5f6eb8af6a9d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=945741805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.945741805
Directory	/workspace/9.adc_ctrl_fsm_reset/latest

Test location	/workspace/coverage/default/9.adc_ctrl_lowpower_counter.2293243530
Short name	T619
Test name
Test status
Simulation time	41562978401 ps
CPU time	22.42 seconds
Started	Jan 03 01:14:53 PM PST 24
Finished	Jan 03 01:16:16 PM PST 24
Peak memory	200768 kb
Host	smart-19b8c225-5d4f-4e3d-b146-f0a6a163b0da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2293243530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.2293243530
Directory	/workspace/9.adc_ctrl_lowpower_counter/latest

Test location	/workspace/coverage/default/9.adc_ctrl_poweron_counter.1983881126
Short name	T460
Test name
Test status
Simulation time	5181803524 ps
CPU time	3.94 seconds
Started	Jan 03 01:14:58 PM PST 24
Finished	Jan 03 01:16:04 PM PST 24
Peak memory	200696 kb
Host	smart-0e099ae3-7f65-4e30-8219-76f1da084fcd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1983881126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.1983881126
Directory	/workspace/9.adc_ctrl_poweron_counter/latest

Test location	/workspace/coverage/default/9.adc_ctrl_smoke.1581237128
Short name	T517
Test name
Test status
Simulation time	5933659977 ps
CPU time	4.37 seconds
Started	Jan 03 01:14:54 PM PST 24
Finished	Jan 03 01:15:59 PM PST 24
Peak memory	200800 kb
Host	smart-0618672a-9347-42d9-a688-16d6cc7323ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1581237128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.1581237128
Directory	/workspace/9.adc_ctrl_smoke/latest

Test location	/workspace/coverage/default/9.adc_ctrl_stress_all.1017525513
Short name	T225
Test name
Test status
Simulation time	341997139639 ps
CPU time	199.91 seconds
Started	Jan 03 01:15:07 PM PST 24
Finished	Jan 03 01:19:31 PM PST 24
Peak memory	200716 kb
Host	smart-2bbf1eac-486d-42a8-b908-35a6540bb100
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017525513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all. 1017525513
Directory	/workspace/9.adc_ctrl_stress_all/latest