Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6888	1			T18	27		T28	20		T29	33
testmodes[AdcCtrlTestmodeNormal]	5340	1			T13	1		T14	2		T17	3
testmodes[AdcCtrlTestmodeLowpower]	5638	1			T13	1		T15	1		T16	3
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3719	1			T18	6		T28	19		T29	13
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1702	1			T18	11		T29	9		T88	3
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1355	1			T18	10		T29	10		T30	25
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1684	1			T18	14		T29	13		T88	2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1957	1			T14	1		T17	2		T18	14
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1365	1			T18	10		T32	1		T85	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1360	1			T18	7		T29	6		T88	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1357	1			T13	1		T18	13		T19	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2675	1			T16	2		T18	17		T19	1