Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24993

1

T5

2

T6

1

T27

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21935

1

T5

2

T6

1

T27

2

auto[ADC_CTRL_FILTER_COND_OUT]

3058

1

T14

1

T18

6

T19

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19713

1

T5

2

T6

1

T27

2

auto[1]

5280

1

T13

16

T15

3

T16

29

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21262

1

T13

11

T14

2

T15

3

auto[1]

3731

1

T5

2

T6

1

T27

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	262	1			T13	6		T19	15		T112	1
values[0]	15	1			T159	1		T194	14		-	-
values[1]	595	1			T13	16		T22	13		T31	7
values[2]	727	1			T18	6		T21	8		T32	18
values[3]	581	1			T14	1		T19	3		T89	6
values[4]	782	1			T22	15		T105	2		T96	17
values[5]	2612	1			T15	3		T16	29		T17	23
values[6]	498	1			T14	1		T20	10		T32	26
values[7]	547	1			T32	27		T85	15		T106	1
values[8]	521	1			T33	8		T106	1		T113	2
values[9]	874	1			T18	2		T19	5		T20	15
minimum	16979	1			T5	2		T6	1		T27	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	631	1			T22	13		T31	7		T109	29
values[1]	672	1			T14	1		T18	6		T21	8
values[2]	645	1			T19	3		T118	13		T90	28
values[3]	2701	1			T15	3		T16	29		T17	23
values[4]	565	1			T107	13		T88	7		T113	13
values[5]	553	1			T14	1		T20	10		T32	41
values[6]	509	1			T33	8		T32	12		T85	15
values[7]	604	1			T113	2		T108	1		T114	10
values[8]	841	1			T13	6		T18	2		T19	20
values[9]	92	1			T195	11		T196	15		T140	10
minimum	17180	1			T5	2		T6	1		T27	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21597

1

T5

2

T6

1

T27

2

auto[1]

3396

1

T13

9

T15

2

T16

26

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T22	7		T197	1		T102	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T31	7		T109	14		T100	25
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T21	3		T197	1		T110	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T14	1		T18	5		T32	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T118	11		T90	15		T102	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T19	3		T98	9		T111	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1242	1			T15	3		T16	29		T17	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T105	1		T96	17		T198	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T107	8		T113	13		T115	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T88	7		T115	1		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T14	1		T32	17		T108	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T20	1		T32	8		T106	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T85	5		T106	1		T99	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T33	3		T32	1		T159	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T113	1		T108	1		T114	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T135	3		T110	7		T162	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T13	4		T18	2		T19	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T20	1		T104	8		T135	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T140	1		T199	1		T200	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T195	7		T196	10		T186	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16897	1			T13	7		T18	98		T32	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T109	8		T159	1		T164	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T22	6		T197	10		T102	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T109	15		T100	17		T123	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T21	5		T197	4		T110	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T18	1		T32	5		T89	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T118	2		T90	13		T165	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T98	11		T111	7		T201	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	999	1			T17	20		T22	17		T95	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T198	5		T100	7		T161	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T107	5		T115	13		T122	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T115	2		T136	1		T202	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T32	9		T136	10		T162	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T20	9		T32	7		T117	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T85	10		T203	4		T131	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T33	5		T32	11		T204	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T113	1		T114	9		T98	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T110	6		T162	8		T123	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T13	2		T19	13		T97	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T20	14		T104	1		T161	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T140	9		T199	5		T200	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T195	4		T196	5		T205	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T5	2		T6	1		T27	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T109	7		T164	7		T138	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T13	4		T19	6		T112	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T195	7		T119	10		T196	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T159	1		T194	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T13	7		T22	7		T102	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T31	7		T109	22		T100	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T21	3		T197	1		T110	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T18	5		T32	13		T99	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T118	11		T90	15		T197	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T14	1		T19	3		T89	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T22	5		T105	1		T115	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T105	1		T96	17		T198	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1265	1			T15	3		T16	29		T17	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T88	7		T115	1		T161	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T14	1		T32	17		T108	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T20	1		T113	1		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T85	5		T206	1		T99	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T32	9		T106	1		T159	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T106	1		T113	1		T108	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T33	3		T135	3		T110	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T18	2		T19	1		T106	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T20	1		T104	8		T135	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16832	1			T18	98		T32	14		T28	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T13	2		T19	9		T161	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T195	4		T119	6		T196	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T194	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T13	9		T22	6		T102	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T109	22		T164	7		T138	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T21	5		T197	10		T110	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T18	1		T32	5		T100	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T118	2		T90	13		T197	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T89	1		T111	7		T207	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T22	10		T115	6		T165	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T198	5		T98	11		T100	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	970	1			T17	20		T22	7		T95	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T115	2		T161	3		T103	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T32	9		T136	10		T165	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T20	9		T136	1		T202	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T85	10		T162	2		T203	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T32	18		T117	8		T124	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T113	1		T98	13		T208	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T33	5		T110	6		T162	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T19	4		T97	13		T118	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T20	14		T104	1		T161	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T5	2		T6	1		T27	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T22	7		T197	11		T102	19
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T31	1		T109	16		T100	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T21	6		T197	5		T110	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T14	1		T18	4		T32	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T118	3		T90	14		T102	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T19	1		T98	12		T111	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1322	1			T15	1		T16	3		T17	23
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T105	1		T96	1		T198	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T107	6		T113	1		T115	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T88	5		T115	3		T136	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T14	1		T32	10		T108	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T20	10		T32	8		T106	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T85	14		T106	1		T99	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T33	6		T32	12		T159	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T113	2		T108	1		T114	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T135	1		T110	7		T162	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T13	3		T18	2		T19	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T20	15		T104	3		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T140	10		T199	6		T200	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T195	9		T196	12		T186	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17015	1			T5	2		T6	1		T27	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T109	8		T159	1		T164	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T22	6		T102	13		T209	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T31	6		T109	13		T100	23
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T21	2		T110	9		T166	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T18	2		T32	12		T89	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T118	10		T90	14		T102	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T19	2		T98	8		T111	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	919	1			T15	2		T16	26		T22	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T96	16		T100	10		T210	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T107	7		T113	12		T122	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T88	2		T202	6		T211	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T32	16		T136	11		T165	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T32	7		T117	3		T124	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T85	1		T212	9		T131	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T33	2		T204	4		T211	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T98	3		T213	4		T120	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T135	2		T110	6		T214	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T13	3		T19	5		T97	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T104	6		T135	4		T119	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T215	9		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T195	2		T196	3		T216	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T13	6		T120	11		T217	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T109	7		T129	8		T218	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T13	3		T19	10		T112	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T195	9		T119	13		T196	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T159	1		T194	14		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T13	10		T22	7		T102	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T31	1		T109	24		T100	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T21	6		T197	11		T110	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T18	4		T32	6		T99	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T118	3		T90	14		T197	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T14	1		T19	1		T89	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T22	11		T105	1		T115	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T105	1		T96	1		T198	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1301	1			T15	1		T16	3		T17	23
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T88	5		T115	3		T161	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T14	1		T32	10		T108	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T20	10		T113	1		T136	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T85	14		T206	1		T99	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T32	20		T106	1		T159	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T106	1		T113	2		T108	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T33	6		T135	1		T110	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T18	2		T19	5		T106	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T20	15		T104	3		T135	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16979	1			T5	2		T6	1		T27	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T13	3		T19	5		T117	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T195	2		T119	3		T196	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T13	6		T22	6		T102	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T31	6		T109	20		T100	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T21	2		T110	9		T166	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T18	2		T32	12		T100	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T118	10		T90	14		T102	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T19	2		T89	1		T111	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T22	4		T214	14		T204	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T96	16		T98	8		T100	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	934	1			T15	2		T16	26		T22	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T88	2		T103	7		T211	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T32	16		T136	11		T165	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T202	6		T130	10		T219	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T85	1		T131	9		T219	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T32	7		T117	3		T124	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T98	3		T213	4		T212	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T33	2		T135	2		T110	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T97	9		T118	11		T120	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T104	6		T135	4		T220	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21597

1

T5

2

T6

1

T27

2

auto[1]

auto[0]

3396

1

T13

9

T15

2

T16

26

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24993

1

T5

2

T6

1

T27

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19950

1

T5

2

T6

1

T27

2

auto[ADC_CTRL_FILTER_COND_OUT]

5043

1

T13

22

T14

1

T15

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19504

1

T5

2

T6

1

T27

2

auto[1]

5489

1

T13

16

T14

1

T15

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21262

1

T13

11

T14

2

T15

3

auto[1]

3731

1

T5

2

T6

1

T27

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	312	1			T31	7		T164	5		T195	11
values[0]	18	1			T221	1		T157	17		-	-
values[1]	600	1			T13	6		T14	1		T32	12
values[2]	607	1			T32	15		T106	1		T113	13
values[3]	757	1			T18	6		T21	8		T22	15
values[4]	688	1			T14	1		T19	20		T22	15
values[5]	523	1			T85	15		T106	1		T96	17
values[6]	567	1			T20	15		T22	13		T109	44
values[7]	706	1			T32	18		T105	1		T118	12
values[8]	548	1			T107	13		T97	22		T110	19
values[9]	2688	1			T13	16		T15	3		T16	29
minimum	16979	1			T5	2		T6	1		T27	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	522	1			T32	12		T113	1		T108	1
values[1]	2509	1			T15	3		T16	29		T17	23
values[2]	746	1			T14	1		T22	15		T88	7
values[3]	635	1			T19	20		T22	15		T118	6
values[4]	598	1			T85	15		T106	1		T96	17
values[5]	579	1			T20	15		T22	13		T32	18
values[6]	687	1			T105	1		T118	12		T135	3
values[7]	595	1			T105	1		T107	13		T97	22
values[8]	784	1			T13	16		T18	2		T19	3
values[9]	125	1			T123	11		T137	18		T222	1
minimum	17213	1			T5	2		T6	1		T27	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21597

1

T5

2

T6

1

T27

2

auto[1]

3396

1

T13

9

T15

2

T16

26

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T108	1		T90	15		T99	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T32	1		T113	1		T98	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T18	5		T32	8		T106	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1254	1			T15	3		T16	29		T17	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T14	1		T88	7		T108	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T22	5		T89	5		T118	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T115	1		T136	1		T223	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T19	7		T22	8		T118	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T85	5		T106	1		T198	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T96	17		T98	9		T99	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T20	1		T22	7		T32	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T204	13		T224	5		T225	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T105	1		T226	1		T214	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T118	10		T135	3		T110	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T105	1		T107	8		T97	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T100	25		T102	14		T212	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T18	2		T33	3		T104	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T13	7		T19	3		T20	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T123	1		T147	11		T227	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T137	18		T222	1		T228	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16924	1			T18	98		T32	14		T28	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T13	4		T14	1		T111	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T90	13		T123	13		T168	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T32	11		T98	13		T103	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T18	1		T32	7		T97	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1006	1			T17	20		T21	5		T95	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T197	10		T119	6		T190	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T22	10		T89	1		T118	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T115	13		T136	1		T204	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T19	13		T22	7		T118	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T85	10		T198	5		T162	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T98	11		T162	8		T124	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T20	14		T22	6		T32	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T204	11		T224	4		T185	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T226	6		T214	16		T203	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T118	2		T110	16		T115	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T107	5		T97	12		T110	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T100	24		T102	18		T121	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T33	5		T104	1		T197	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T13	9		T20	9		T32	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T123	10		T147	14		T227	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T229	1		T230	11		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T5	2		T6	1		T27	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T13	2		T111	7		T201	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T31	7		T127	1		T231	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T164	1		T195	7		T127	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T221	1		T157	17		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T108	1		T99	1		T159	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T13	4		T14	1		T32	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T32	8		T106	1		T90	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T113	13		T101	1		T161	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T18	5		T88	7		T97	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T21	3		T22	5		T89	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T14	1		T136	1		T223	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T19	7		T22	8		T136	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T85	5		T106	1		T115	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T96	17		T118	3		T98	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T20	1		T22	7		T109	22
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T162	1		T224	13		T185	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T32	13		T105	1		T232	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T118	10		T135	3		T110	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T107	8		T97	10		T110	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T100	14		T212	10		T121	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T18	2		T33	3		T104	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1255	1			T13	7		T15	3		T16	29
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16832	1			T18	98		T32	14		T28	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T233	11		T138	10		T234	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T164	4		T195	4		T235	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T123	13		T236	6		T168	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T13	2		T32	11		T98	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T32	7		T90	13		T164	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T161	3		T165	2		T103	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T18	1		T97	1		T197	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T21	5		T22	10		T89	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T136	1		T204	4		T140	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T19	13		T22	7		T136	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T85	10		T115	13		T237	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T118	3		T98	11		T123	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T20	14		T22	6		T109	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T162	8		T224	9		T185	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T32	5		T226	6		T214	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T118	2		T110	16		T115	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T107	5		T97	12		T110	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T100	17		T121	9		T117	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T33	5		T104	1		T197	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	993	1			T13	9		T17	20		T20	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T5	2		T6	1		T27	2