Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24993

1

T5

2

T6

1

T27

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21777

1

T5

2

T6

1

T27

2

auto[ADC_CTRL_FILTER_COND_OUT]

3216

1

T13

16

T14

1

T18

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19903

1

T5

2

T6

1

T27

2

auto[1]

5090

1

T13

22

T14

1

T15

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21262

1

T13

11

T14

2

T15

3

auto[1]

3731

1

T5

2

T6

1

T27

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	202	1			T113	13		T206	1		T115	7
values[0]	32	1			T136	2		T204	15		T285	15
values[1]	725	1			T13	16		T14	1		T19	15
values[2]	2476	1			T14	1		T15	3		T16	29
values[3]	590	1			T32	41		T88	7		T108	1
values[4]	432	1			T18	2		T19	3		T106	1
values[5]	641	1			T20	15		T32	18		T104	2
values[6]	622	1			T22	13		T32	12		T104	7
values[7]	612	1			T21	8		T33	8		T98	17
values[8]	575	1			T19	5		T105	1		T89	6
values[9]	1107	1			T13	6		T20	10		T22	30
minimum	16979	1			T5	2		T6	1		T27	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	684	1			T13	16		T18	6		T106	1
values[1]	2481	1			T14	1		T15	3		T16	29
values[2]	495	1			T18	2		T32	41		T88	7
values[3]	556	1			T19	3		T104	2		T105	1
values[4]	562	1			T20	15		T32	18		T118	19
values[5]	707	1			T21	8		T22	13		T32	12
values[6]	606	1			T33	8		T89	6		T97	2
values[7]	562	1			T19	5		T105	1		T106	1
values[8]	1039	1			T13	6		T20	10		T22	30
values[9]	83	1			T162	3		T195	11		T123	14
minimum	17218	1			T5	2		T6	1		T27	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21597

1

T5

2

T6

1

T27

2

auto[1]

3396

1

T13

9

T15

2

T16

26

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T18	5		T135	5		T100	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T13	7		T106	1		T110	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1232	1			T15	3		T16	29		T17	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T14	1		T107	8		T159	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T32	17		T197	1		T202	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T18	2		T32	8		T88	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T19	3		T105	1		T98	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T104	1		T106	1		T113	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T20	1		T118	3		T198	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T32	13		T118	11		T108	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T21	3		T104	7		T103	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T22	7		T32	1		T118	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T33	3		T97	1		T164	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T89	5		T98	4		T122	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T19	1		T105	1		T197	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T106	1		T31	7		T103	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	340	1			T13	4		T20	1		T22	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T97	10		T114	1		T206	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T162	1		T123	1		T272	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T195	7		T315	1		T288	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16894	1			T14	1		T18	98		T32	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T19	6		T113	1		T115	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T18	1		T164	7		T165	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T13	9		T110	9		T165	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	935	1			T17	20		T95	20		T274	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T107	5		T161	3		T249	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T32	9		T202	11		T123	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T32	7		T90	13		T110	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T98	11		T161	7		T116	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T104	1		T113	1		T111	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T20	14		T118	3		T198	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T32	5		T118	2		T109	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T21	5		T103	2		T310	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T22	6		T32	11		T118	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T33	5		T97	1		T164	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T89	1		T98	13		T122	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T19	4		T197	4		T276	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T103	5		T233	2		T250	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T13	2		T20	9		T22	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T97	12		T114	9		T197	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T162	2		T123	13		T263	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T195	4		T315	15		T288	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T5	2		T6	1		T27	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T19	9		T115	2		T254	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T113	13		T115	1		T102	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T206	1		T112	1		T195	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T136	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T204	11		T285	15		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T14	1		T135	5		T100	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T13	7		T19	6		T113	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1237	1			T15	3		T16	29		T17	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T14	1		T106	1		T107	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T32	17		T197	1		T202	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T32	8		T88	7		T108	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T19	3		T161	1		T116	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T18	2		T106	1		T113	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T20	1		T105	1		T118	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T32	13		T104	1		T118	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T104	7		T164	1		T103	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T22	7		T32	1		T118	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T21	3		T33	3		T164	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T98	4		T100	14		T159	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T19	1		T105	1		T97	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T89	5		T122	8		T102	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T13	4		T20	1		T22	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T106	1		T97	10		T31	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16832	1			T18	98		T32	14		T28	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T115	6		T281	4		T269	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T195	4		T224	4		T236	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T136	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T204	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T165	2		T123	13		T208	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T13	9		T19	9		T110	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	953	1			T17	20		T18	1		T95	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T107	5		T249	6		T226	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T32	9		T202	11		T123	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T32	7		T90	13		T110	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T161	7		T116	1		T226	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T113	1		T100	7		T136	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T20	14		T118	3		T198	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T32	5		T104	1		T118	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T164	4		T103	2		T310	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T22	6		T32	11		T118	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T21	5		T33	5		T164	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T98	13		T100	17		T226	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T19	4		T97	1		T289	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T89	1		T122	2		T102	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T13	2		T20	9		T22	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T97	12		T114	9		T197	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T5	2		T6	1		T27	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T18	4		T135	1		T100	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T13	10		T106	1		T110	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1258	1			T15	1		T16	3		T17	23
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T14	1		T107	6		T159	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T32	10		T197	1		T202	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T18	2		T32	8		T88	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T19	1		T105	1		T98	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T104	2		T106	1		T113	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T20	15		T118	4		T198	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T32	6		T118	3		T108	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T21	6		T104	1		T103	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T22	7		T32	12		T118	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T33	6		T97	2		T164	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T89	5		T98	14		T122	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T19	5		T105	1		T197	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T106	1		T31	1		T103	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	372	1			T13	3		T20	10		T22	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T97	13		T114	10		T206	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T162	3		T123	14		T272	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T195	9		T315	16		T288	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17058	1			T5	2		T6	1		T27	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T19	10		T113	1		T115	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T18	2		T135	4		T100	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T13	6		T110	9		T165	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	909	1			T15	2		T16	26		T96	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T107	7		T120	11		T255	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T32	16		T202	6		T124	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T32	7		T88	2		T90	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T19	2		T98	8		T251	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T111	9		T100	10		T136	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T118	2		T212	9		T207	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T32	12		T118	10		T109	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T21	2		T104	6		T103	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T22	6		T118	9		T210	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T33	2		T210	9		T260	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T89	1		T98	3		T122	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T268	8		T276	10		T299	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T31	6		T103	5		T233	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T13	3		T22	11		T85	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T97	9		T110	13		T224	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T263	3		T316	12		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T195	2		T288	6		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T208	3		T137	17		T262	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T19	5		T204	22		T145	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T113	1		T115	7		T102	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T206	1		T112	1		T195	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T136	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T204	5		T285	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T14	1		T135	1		T100	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T13	10		T19	10		T113	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1289	1			T15	1		T16	3		T17	23
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T14	1		T106	1		T107	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T32	10		T197	1		T202	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T32	8		T88	5		T108	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T19	1		T161	8		T116	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T18	2		T106	1		T113	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T20	15		T105	1		T118	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T32	6		T104	2		T118	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T104	1		T164	5		T103	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T22	7		T32	12		T118	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T21	6		T33	6		T164	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T98	14		T100	18		T159	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T19	5		T105	1		T97	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T89	5		T122	3		T102	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	390	1			T13	3		T20	10		T22	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T106	1		T97	13		T31	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16979	1			T5	2		T6	1		T27	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T113	12		T102	2		T281	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T195	2		T224	4		T236	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T204	10		T285	14		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T135	4		T100	10		T208	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T13	6		T19	5		T110	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	901	1			T15	2		T16	26		T18	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T107	7		T120	11		T117	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T32	16		T202	6		T124	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T32	7		T88	2		T90	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T19	2		T251	10		T137	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T100	10		T136	9		T209	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T118	2		T98	8		T212	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T32	12		T118	10		T109	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T104	6		T103	2		T209	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T22	6		T118	9		T210	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T21	2		T33	2		T210	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T98	3		T100	13		T120	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T268	8		T289	17		T299	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T89	1		T122	7		T102	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T13	3		T22	11		T85	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T97	9		T31	6		T110	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21597

1

T5

2

T6

1

T27

2

auto[1]

auto[0]

3396

1

T13

9

T15

2

T16

26