Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24993

1

T5

2

T6

1

T27

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21893

1

T5

2

T6

1

T27

2

auto[ADC_CTRL_FILTER_COND_OUT]

3100

1

T13

6

T18

2

T19

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19716

1

T5

2

T6

1

T27

2

auto[1]

5277

1

T13

22

T14

1

T15

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21262

1

T13

11

T14

2

T15

3

auto[1]

3731

1

T5

2

T6

1

T27

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	58	1			T317	21		T200	7		T318	30
values[0]	55	1			T22	15		T104	7		T208	13
values[1]	664	1			T13	6		T22	15		T105	1
values[2]	618	1			T19	5		T106	1		T88	7
values[3]	741	1			T21	8		T32	33		T85	15
values[4]	515	1			T18	6		T113	2		T197	5
values[5]	2373	1			T14	2		T15	3		T16	29
values[6]	581	1			T19	15		T33	8		T106	1
values[7]	624	1			T18	2		T105	1		T107	13
values[8]	724	1			T13	16		T19	3		T104	2
values[9]	1061	1			T20	25		T22	13		T32	38
minimum	16979	1			T5	2		T6	1		T27	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	866	1			T13	6		T22	15		T104	7
values[1]	734	1			T19	5		T21	8		T106	1
values[2]	563	1			T32	33		T89	6		T31	7
values[3]	2518	1			T14	1		T15	3		T16	29
values[4]	438	1			T14	1		T106	1		T118	12
values[5]	535	1			T19	15		T33	8		T118	19
values[6]	805	1			T18	2		T105	1		T107	13
values[7]	614	1			T13	16		T19	3		T32	12
values[8]	764	1			T20	15		T22	13		T32	26
values[9]	162	1			T20	10		T97	2		T136	22
minimum	16994	1			T5	2		T6	1		T27	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21597

1

T5

2

T6

1

T27

2

auto[1]

3396

1

T13

9

T15

2

T16

26

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T22	8		T105	1		T113	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T13	4		T104	7		T88	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T19	1		T21	3		T106	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T96	17		T159	1		T162	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T32	8		T89	5		T31	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T32	13		T206	1		T135	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1222	1			T14	1		T15	3		T16	29
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T109	14		T197	1		T111	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T14	1		T118	10		T109	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T106	1		T108	1		T201	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T33	3		T118	11		T161	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T19	6		T118	3		T164	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T107	8		T90	15		T270	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T18	2		T105	1		T97	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T13	7		T104	1		T110	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T19	3		T32	1		T106	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T20	1		T22	7		T123	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T32	17		T113	13		T99	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T97	1		T136	12		T272	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T20	1		T214	15		T319	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16832	1			T18	98		T32	14		T28	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T22	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T22	7		T197	10		T164	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T13	2		T198	5		T100	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T19	4		T21	5		T114	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T162	8		T165	18		T203	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T32	7		T89	1		T115	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T32	5		T122	2		T136	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	947	1			T17	20		T18	1		T95	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T109	15		T197	4		T111	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T118	2		T109	7		T115	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T201	12		T121	9		T208	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T33	5		T118	2		T161	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T19	9		T118	3		T164	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T107	5		T90	13		T103	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T97	12		T116	1		T245	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T13	9		T104	1		T110	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T32	11		T129	15		T299	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T20	14		T22	6		T123	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T32	9		T100	17		T136	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T97	1		T136	10		T315	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T20	9		T214	17		T239	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T5	2		T6	1		T27	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T22	10		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T317	7		T200	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T318	16		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T22	8		T290	5		T320	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T104	7		T208	4		T169	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T105	1		T113	1		T197	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T13	4		T22	5		T198	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T19	1		T106	1		T98	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T88	7		T135	5		T162	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T21	3		T32	8		T85	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T32	13		T96	17		T206	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T18	5		T113	1		T115	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T197	1		T111	10		T122	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1201	1			T14	2		T15	3		T16	29
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T108	1		T109	14		T112	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T33	3		T118	11		T161	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T19	6		T106	1		T118	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T107	8		T270	1		T127	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T18	2		T105	1		T101	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T13	7		T104	1		T90	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T19	3		T106	1		T97	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T20	1		T22	7		T97	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T20	1		T32	18		T113	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16832	1			T18	98		T32	14		T28	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T317	14		T200	6		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T318	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T22	7		T290	5		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T208	9		T267	3		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T197	10		T190	1		T125	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T13	2		T22	10		T198	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T19	4		T98	13		T164	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T162	8		T203	4		T147	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T21	5		T32	7		T85	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T32	5		T165	18		T123	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T18	1		T113	1		T115	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T197	4		T111	7		T122	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	930	1			T17	20		T95	20		T274	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T109	15		T201	12		T124	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T33	5		T118	2		T161	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T19	9		T118	3		T164	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T107	5		T202	11		T103	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T203	9		T321	14		T275	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T13	9		T104	1		T90	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T97	12		T116	1		T250	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T20	14		T22	6		T97	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T20	9		T32	20		T100	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T5	2		T6	1		T27	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T22	8		T105	1		T113	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T13	3		T104	1		T88	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T19	5		T21	6		T106	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T96	1		T159	1		T162	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T32	8		T89	5		T31	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T32	6		T206	1		T135	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1277	1			T14	1		T15	1		T16	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T109	16		T197	5		T111	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T14	1		T118	3		T109	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T106	1		T108	1		T201	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T33	6		T118	3		T161	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T19	10		T118	4		T164	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T107	6		T90	14		T270	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T18	2		T105	1		T97	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T13	10		T104	2		T110	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T19	1		T32	12		T106	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T20	15		T22	7		T123	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T32	10		T113	1		T99	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T97	2		T136	11		T272	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T20	10		T214	18		T319	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16979	1			T5	2		T6	1		T27	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T22	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T22	7		T103	5		T190	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T13	3		T104	6		T88	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T21	2		T98	3		T255	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T96	16		T165	12		T210	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T32	7		T89	1		T31	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T32	12		T135	4		T122	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	892	1			T15	2		T16	26		T18	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T109	13		T111	9		T210	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T118	9		T109	7		T211	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T201	1		T124	8		T208	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T33	2		T118	10		T117	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T19	5		T118	2		T137	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T107	7		T90	14		T103	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T97	9		T212	9		T255	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T13	6		T110	15		T202	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T19	2		T211	2		T129	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T22	6		T166	9		T218	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T32	16		T113	12		T100	23
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T136	11		T148	4		T300	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T214	14		T239	5		T215	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T22	4		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T317	18		T200	7		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T318	15		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T22	8		T290	7		T320	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T104	1		T208	10		T169	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T105	1		T113	1		T197	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T13	3		T22	11		T198	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T19	5		T106	1		T98	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T88	5		T135	1		T162	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T21	6		T32	8		T85	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T32	6		T96	1		T206	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T18	4		T113	2		T115	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T197	5		T111	8		T122	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1245	1			T14	2		T15	1		T16	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T108	1		T109	16		T112	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T33	6		T118	3		T161	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T19	10		T106	1		T118	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T107	6		T270	1		T127	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T18	2		T105	1		T101	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T13	10		T104	2		T90	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T19	1		T106	1		T97	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T20	15		T22	7		T97	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	332	1			T20	10		T32	22		T113	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16979	1			T5	2		T6	1		T27	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T317	3		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T318	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T22	7		T290	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T104	6		T208	3		T267	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T190	1		T204	12		T268	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T13	3		T22	4		T100	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T98	3		T103	5		T255	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T88	2		T135	4		T210	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T21	2		T32	7		T85	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T32	12		T96	16		T165	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T18	2		T213	4		T224	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T111	9		T122	7		T210	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	886	1			T15	2		T16	26		T256	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T109	13		T201	1		T124	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T33	2		T118	10		T117	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T19	5		T118	2		T214	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T107	7		T202	6		T103	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T212	9		T137	7		T130	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T13	6		T90	14		T110	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T19	2		T97	9		T255	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T22	6		T110	6		T136	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T32	16		T113	12		T100	23

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21597

1

T5

2

T6

1

T27

2

auto[1]

auto[0]

3396

1

T13

9

T15

2

T16

26