Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24993

1

T5

2

T6

1

T27

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22258

1

T5

2

T6

1

T27

2

auto[ADC_CTRL_FILTER_COND_OUT]

2735

1

T13

6

T14

2

T18

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19824

1

T5

2

T6

1

T27

2

auto[1]

5169

1

T13

16

T14

2

T15

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21262

1

T13

11

T14

2

T15

3

auto[1]

3731

1

T5

2

T6

1

T27

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	49	1			T226	18		T324	8		T156	1
values[0]	74	1			T96	17		T305	1		T306	8
values[1]	508	1			T104	7		T105	1		T106	1
values[2]	766	1			T21	8		T32	26		T105	1
values[3]	629	1			T22	13		T113	13		T99	1
values[4]	529	1			T106	1		T113	2		T197	1
values[5]	541	1			T14	1		T18	2		T22	15
values[6]	551	1			T20	10		T32	15		T89	6
values[7]	625	1			T19	3		T107	13		T108	1
values[8]	2449	1			T14	1		T15	3		T16	29
values[9]	1293	1			T13	22		T18	6		T19	20
minimum	16979	1			T5	2		T6	1		T27	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	733	1			T104	7		T105	1		T106	1
values[1]	772	1			T21	8		T32	26		T105	1
values[2]	482	1			T22	13		T99	1		T111	17
values[3]	682	1			T106	1		T113	2		T197	1
values[4]	444	1			T14	1		T18	2		T22	15
values[5]	646	1			T20	10		T32	15		T108	1
values[6]	2381	1			T15	3		T16	29		T17	23
values[7]	768	1			T14	1		T22	15		T32	18
values[8]	843	1			T13	22		T18	6		T19	5
values[9]	240	1			T19	15		T213	5		T269	11
minimum	17002	1			T5	2		T6	1		T27	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21597

1

T5

2

T6

1

T27

2

auto[1]

3396

1

T13

9

T15

2

T16

26

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T106	1		T118	21		T108	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T104	7		T105	1		T198	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T32	17		T105	1		T161	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T21	3		T113	13		T122	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T99	1		T159	1		T165	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T22	7		T111	10		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T106	1		T197	1		T115	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T113	1		T115	1		T101	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T18	2		T33	3		T89	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T14	1		T22	8		T115	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T20	1		T90	15		T197	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T32	8		T108	1		T109	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1220	1			T15	3		T16	29		T17	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T107	8		T117	4		T207	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T22	5		T32	13		T118	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T14	1		T85	5		T100	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T13	7		T20	1		T32	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T13	4		T18	5		T19	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T19	6		T126	3		T307	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T213	5		T269	8		T301	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16849	1			T18	98		T32	14		T28	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T325	3		T326	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T118	4		T109	7		T162	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T198	5		T110	9		T119	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T32	9		T161	3		T162	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T21	5		T122	1		T251	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T165	2		T248	7		T146	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T22	6		T111	7		T136	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T115	13		T122	2		T100	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T113	1		T115	2		T161	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T33	5		T89	1		T214	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T22	7		T115	6		T164	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T20	9		T90	13		T197	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T32	7		T109	15		T136	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	970	1			T17	20		T95	20		T274	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T107	5		T117	8		T207	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T22	10		T32	5		T118	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T85	10		T100	17		T165	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T13	9		T20	14		T32	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T13	2		T18	1		T19	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T19	9		T126	11		T307	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T269	3		T301	2		T312	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T5	2		T6	1		T27	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T325	2		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T226	1		T324	7		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T156	1		T327	5		T328	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T96	17		T305	1		T288	18
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T306	8		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T106	1		T118	10		T108	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T104	7		T105	1		T198	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T32	17		T105	1		T118	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T21	3		T135	5		T122	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T99	1		T159	1		T161	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T22	7		T113	13		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T106	1		T197	1		T99	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T113	1		T111	10		T161	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T18	2		T33	3		T115	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T14	1		T22	8		T115	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T20	1		T89	5		T113	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T32	8		T136	12		T164	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T19	3		T90	15		T197	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T107	8		T108	1		T109	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1219	1			T15	3		T16	29		T17	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T14	1		T85	5		T165	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	359	1			T13	7		T19	6		T20	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	368	1			T13	4		T18	5		T19	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16832	1			T18	98		T32	14		T28	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T226	17		T324	1		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T327	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T288	13		T309	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T118	2		T109	7		T195	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T198	5		T110	9		T249	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T32	9		T118	2		T162	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T21	5		T122	1		T119	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T161	3		T165	2		T248	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T22	6		T136	1		T125	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T100	7		T123	13		T203	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T113	1		T111	7		T161	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T33	5		T115	13		T122	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T22	7		T115	8		T207	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T20	9		T89	1		T202	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T32	7		T136	10		T164	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T90	13		T197	4		T98	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T107	5		T109	15		T100	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	978	1			T17	20		T22	10		T95	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T85	10		T165	18		T207	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T13	9		T19	9		T20	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T13	2		T18	1		T19	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T5	2		T6	1		T27	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T106	1		T118	6		T108	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T104	1		T105	1		T198	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	334	1			T32	10		T105	1		T161	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T21	6		T113	1		T122	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T99	1		T159	1		T165	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T22	7		T111	8		T136	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T106	1		T197	1		T115	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T113	2		T115	3		T101	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T18	2		T33	6		T89	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T14	1		T22	8		T115	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T20	10		T90	14		T197	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T32	8		T108	1		T109	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1300	1			T15	1		T16	3		T17	23
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T107	6		T117	9		T207	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T22	11		T32	6		T118	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T14	1		T85	14		T100	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T13	10		T20	15		T32	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T13	3		T18	4		T19	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T19	10		T126	12		T307	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T213	1		T269	9		T301	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16980	1			T5	2		T6	1		T27	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T325	3		T326	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T118	19		T109	7		T135	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T104	6		T135	4		T110	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T32	16		T299	5		T131	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T21	2		T113	12		T102	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T145	2		T220	9		T146	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T22	6		T111	9		T137	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T122	7		T100	20		T209	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T120	11		T255	1		T126	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T33	2		T89	1		T214	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T22	7		T207	14		T238	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T90	14		T202	6		T117	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T32	7		T109	13		T136	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	890	1			T15	2		T16	26		T19	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T107	7		T117	3		T207	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T22	4		T32	12		T118	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T85	1		T100	13		T165	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T13	6		T88	2		T136	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T13	3		T18	2		T31	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T19	5		T126	2		T307	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T213	4		T269	2		T312	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T96	16		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T325	2		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T226	18		T324	6		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T156	1		T327	5		T328	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T96	1		T305	1		T288	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T306	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T106	1		T118	3		T108	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T104	1		T105	1		T198	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	338	1			T32	10		T105	1		T118	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T21	6		T135	1		T122	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T99	1		T159	1		T161	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T22	7		T113	1		T136	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T106	1		T197	1		T99	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T113	2		T111	8		T161	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T18	2		T33	6		T115	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T14	1		T22	8		T115	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T20	10		T89	5		T113	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T32	8		T136	11		T164	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T19	1		T90	14		T197	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T107	6		T108	1		T109	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1312	1			T15	1		T16	3		T17	23
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T14	1		T85	14		T165	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	400	1			T13	10		T19	10		T20	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T13	3		T18	4		T19	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16979	1			T5	2		T6	1		T27	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T324	2		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T327	4		T328	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T96	16		T288	17		T309	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T306	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T118	9		T109	7		T135	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T104	6		T110	9		T260	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T32	16		T118	10		T299	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T21	2		T135	4		T102	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T220	9		T131	9		T146	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T22	6		T113	12		T251	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T100	10		T209	11		T190	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T111	9		T120	11		T255	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T33	2		T122	7		T100	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T22	7		T207	14		T238	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T89	1		T202	6		T117	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T32	7		T136	11		T201	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T19	2		T90	14		T98	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T107	7		T109	13		T100	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	885	1			T15	2		T16	26		T22	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T85	1		T165	12		T207	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T13	6		T19	5		T32	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T13	3		T18	2		T31	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21597

1

T5

2

T6

1

T27

2

auto[1]

auto[0]

3396

1

T13

9

T15

2

T16

26