Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24993

1

T5

2

T6

1

T27

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21774

1

T5

2

T6

1

T27

2

auto[ADC_CTRL_FILTER_COND_OUT]

3219

1

T13

16

T14

1

T18

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19896

1

T5

2

T6

1

T27

2

auto[1]

5097

1

T13

22

T14

1

T15

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21262

1

T13

11

T14

2

T15

3

auto[1]

3731

1

T5

2

T6

1

T27

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	44	1			T240	23		T325	5		T329	16
values[0]	65	1			T19	15		T136	2		T125	6
values[1]	700	1			T13	16		T14	1		T113	1
values[2]	2431	1			T14	1		T15	3		T16	29
values[3]	644	1			T32	41		T88	7		T108	1
values[4]	383	1			T18	2		T19	3		T106	1
values[5]	644	1			T20	15		T104	2		T105	1
values[6]	559	1			T21	8		T32	30		T104	7
values[7]	783	1			T22	13		T33	8		T89	6
values[8]	534	1			T19	5		T105	1		T97	2
values[9]	1227	1			T13	6		T20	10		T22	30
minimum	16979	1			T5	2		T6	1		T27	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	900	1			T13	16		T14	1		T18	6
values[1]	2457	1			T14	1		T15	3		T16	29
values[2]	549	1			T18	2		T32	41		T88	7
values[3]	473	1			T19	3		T104	2		T105	1
values[4]	610	1			T20	15		T32	18		T118	19
values[5]	718	1			T21	8		T22	13		T32	12
values[6]	572	1			T33	8		T105	1		T97	2
values[7]	605	1			T19	5		T106	1		T89	6
values[8]	1020	1			T13	6		T20	10		T22	30
values[9]	85	1			T206	1		T162	3		T195	11
minimum	17004	1			T5	2		T6	1		T27	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21597

1

T5

2

T6

1

T27

2

auto[1]

3396

1

T13

9

T15

2

T16

26

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T14	1		T18	5		T135	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T13	7		T19	6		T113	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1222	1			T15	3		T16	29		T17	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T14	1		T106	1		T107	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T32	17		T197	1		T202	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T18	2		T32	8		T88	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T19	3		T105	1		T98	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T104	1		T106	1		T113	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T20	1		T118	3		T198	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T32	13		T118	11		T108	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T21	3		T104	7		T164	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T22	7		T32	1		T118	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T33	3		T105	1		T97	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T98	4		T122	8		T100	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T19	1		T197	1		T112	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T106	1		T89	5		T31	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T13	4		T20	1		T22	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T97	10		T114	1		T197	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T162	1		T123	1		T272	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T206	1		T195	7		T315	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16832	1			T18	98		T32	14		T28	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T204	11		T330	1		T327	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T18	1		T136	1		T164	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T13	9		T19	9		T110	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	925	1			T17	20		T95	20		T274	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T107	5		T161	3		T226	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T32	9		T202	11		T123	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T32	7		T90	13		T110	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T98	11		T161	7		T116	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T104	1		T113	1		T111	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T20	14		T118	3		T198	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T32	5		T118	2		T109	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T21	5		T164	13		T103	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T22	6		T32	11		T118	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T33	5		T97	1		T125	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T98	13		T122	2		T100	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T19	4		T197	4		T129	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T89	1		T103	5		T233	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T13	2		T20	9		T22	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T97	12		T114	9		T197	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T162	2		T123	13		T263	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T195	4		T315	15		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T5	2		T6	1		T27	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T204	4		T327	4		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T240	13		T329	5		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T325	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T136	1		T294	1		T271	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T19	6		T125	1		T331	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T14	1		T135	5		T100	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T13	7		T113	1		T110	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1222	1			T15	3		T16	29		T17	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T14	1		T106	1		T107	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T32	17		T197	1		T202	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T32	8		T88	7		T108	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T19	3		T226	1		T251	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T18	2		T106	1		T113	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T20	1		T105	1		T118	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T104	1		T118	11		T108	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T21	3		T104	7		T164	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T32	14		T118	10		T159	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T33	3		T164	1		T202	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T22	7		T89	5		T98	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T19	1		T105	1		T97	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T122	8		T102	17		T233	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	341	1			T13	4		T20	1		T22	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T106	1		T97	10		T31	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16832	1			T18	98		T32	14		T28	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T240	10		T329	11		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T325	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T136	1		T332	5		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T19	9		T125	5		T313	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T164	7		T165	2		T123	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T13	9		T110	9		T115	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	934	1			T17	20		T18	1		T95	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T107	5		T249	6		T226	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T32	9		T202	11		T123	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T32	7		T90	13		T110	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T226	17		T251	9		T185	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T113	1		T100	7		T136	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T20	14		T118	3		T198	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T104	1		T118	2		T109	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T21	5		T164	4		T103	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T32	16		T118	2		T161	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T33	5		T164	13		T254	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T22	6		T89	1		T98	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T19	4		T97	1		T289	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T122	2		T102	18		T233	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T13	2		T20	9		T22	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T97	12		T114	9		T197	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T5	2		T6	1		T27	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T14	1		T18	4		T135	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T13	10		T19	10		T113	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1254	1			T15	1		T16	3		T17	23
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T14	1		T106	1		T107	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T32	10		T197	1		T202	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T18	2		T32	8		T88	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T19	1		T105	1		T98	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T104	2		T106	1		T113	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T20	15		T118	4		T198	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T32	6		T118	3		T108	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T21	6		T104	1		T164	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T22	7		T32	12		T118	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T33	6		T105	1		T97	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T98	14		T122	3		T100	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T19	5		T197	5		T112	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T106	1		T89	5		T31	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	351	1			T13	3		T20	10		T22	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T97	13		T114	10		T197	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T162	3		T123	14		T272	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T206	1		T195	9		T315	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16979	1			T5	2		T6	1		T27	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T204	5		T330	1		T327	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T18	2		T135	4		T100	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T13	6		T19	5		T110	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	893	1			T15	2		T16	26		T96	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T107	7		T120	11		T255	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T32	16		T202	6		T124	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T32	7		T88	2		T90	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T19	2		T98	8		T251	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T111	9		T100	10		T136	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T118	2		T212	9		T207	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T32	12		T118	10		T109	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T21	2		T104	6		T103	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T22	6		T118	9		T210	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T33	2		T210	9		T209	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T98	3		T122	7		T100	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T268	8		T129	12		T276	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T89	1		T31	6		T103	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T13	3		T22	11		T85	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T97	9		T110	13		T224	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T263	3		T316	12		T296	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T195	2		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T204	10		T327	4		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T240	11		T329	12		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T325	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T136	2		T294	1		T271	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T19	10		T125	6		T331	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T14	1		T135	1		T100	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T13	10		T113	1		T110	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1265	1			T15	1		T16	3		T17	23
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T14	1		T106	1		T107	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T32	10		T197	1		T202	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T32	8		T88	5		T108	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T19	1		T226	18		T251	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T18	2		T106	1		T113	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T20	15		T105	1		T118	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T104	2		T118	3		T108	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T21	6		T104	1		T164	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T32	18		T118	3		T159	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T33	6		T164	14		T202	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T22	7		T89	5		T98	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T19	5		T105	1		T97	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T122	3		T102	20		T233	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	393	1			T13	3		T20	10		T22	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	369	1			T106	1		T97	13		T31	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16979	1			T5	2		T6	1		T27	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T240	12		T329	4		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T325	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T271	7		T332	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T19	5		T331	10		T313	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T135	4		T100	10		T208	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T13	6		T110	9		T165	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	891	1			T15	2		T16	26		T18	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T107	7		T120	11		T117	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T32	16		T202	6		T124	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T32	7		T88	2		T90	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T19	2		T251	10		T137	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T100	10		T136	9		T209	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T118	2		T98	8		T212	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T118	10		T109	7		T111	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T21	2		T104	6		T103	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T32	12		T118	9		T201	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T33	2		T210	9		T137	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T22	6		T89	1		T98	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T268	8		T289	17		T126	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T122	7		T102	15		T233	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T13	3		T22	11		T85	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T97	9		T31	6		T110	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21597

1

T5

2

T6

1

T27

2

auto[1]

auto[0]

3396

1

T13

9

T15

2

T16

26