Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24993

1

T5

2

T6

1

T27

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22061

1

T5

2

T6

1

T27

2

auto[ADC_CTRL_FILTER_COND_OUT]

2932

1

T13

22

T18

2

T19

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19858

1

T5

2

T6

1

T27

2

auto[1]

5135

1

T13

22

T14

1

T15

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21262

1

T13

11

T14

2

T15

3

auto[1]

3731

1

T5

2

T6

1

T27

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	198	1			T22	13		T254	3		T166	10
values[0]	29	1			T22	15		T208	13		T320	1
values[1]	722	1			T13	6		T22	15		T104	7
values[2]	628	1			T19	5		T106	1		T88	7
values[3]	691	1			T21	8		T32	33		T85	15
values[4]	558	1			T18	6		T113	2		T135	3
values[5]	2355	1			T14	2		T15	3		T16	29
values[6]	513	1			T19	15		T33	8		T106	1
values[7]	671	1			T18	2		T107	13		T270	1
values[8]	695	1			T13	16		T19	3		T32	12
values[9]	954	1			T20	25		T32	26		T97	2
minimum	16979	1			T5	2		T6	1		T27	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	596	1			T13	6		T105	1		T88	7
values[1]	717	1			T19	5		T21	8		T106	1
values[2]	598	1			T32	33		T96	17		T89	6
values[3]	2530	1			T14	2		T15	3		T16	29
values[4]	426	1			T106	1		T118	12		T108	1
values[5]	553	1			T19	15		T33	8		T118	19
values[6]	754	1			T18	2		T105	1		T107	13
values[7]	611	1			T13	16		T19	3		T32	12
values[8]	773	1			T20	15		T22	13		T32	26
values[9]	184	1			T20	10		T97	2		T101	1
minimum	17251	1			T5	2		T6	1		T27	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21597

1

T5

2

T6

1

T27

2

auto[1]

3396

1

T13

9

T15

2

T16

26

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T105	1		T113	1		T99	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T13	4		T88	7		T198	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T19	1		T21	3		T106	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T159	1		T162	1		T165	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T32	8		T89	5		T31	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T32	13		T96	17		T108	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1265	1			T14	2		T15	3		T16	29
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T113	1		T197	1		T111	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T118	10		T109	8		T115	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T106	1		T108	1		T201	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T33	3		T118	14		T161	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T19	6		T164	1		T202	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T107	8		T90	15		T270	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T18	2		T105	1		T97	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T32	1		T104	1		T110	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T13	7		T19	3		T106	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T20	1		T22	7		T113	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T32	17		T99	1		T100	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T97	1		T239	6		T333	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T20	1		T101	1		T214	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16945	1			T18	98		T22	13		T32	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T124	1		T208	4		T190	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T100	7		T164	13		T103	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T13	2		T198	5		T197	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T19	4		T21	5		T114	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T162	8		T165	18		T289	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T32	7		T89	1		T98	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T32	5		T122	3		T136	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	989	1			T17	20		T18	1		T95	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T113	1		T197	4		T111	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T118	2		T109	7		T115	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T201	12		T208	11		T214	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T33	5		T118	5		T161	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T19	9		T164	7		T121	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T107	5		T90	13		T103	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T97	12		T203	9		T245	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T32	11		T104	1		T110	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T13	9		T161	3		T129	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T20	14		T22	6		T136	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T32	9		T100	17		T136	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T97	1		T239	8		T333	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T20	9		T214	17		T215	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T5	2		T6	1		T27	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T124	1		T208	9		T190	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T22	7		T254	1		T186	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T166	10		T131	12		T319	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T22	8		T320	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T208	4		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T22	5		T104	7		T105	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T13	4		T198	1		T197	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T19	1		T106	1		T98	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T88	7		T162	1		T165	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T21	3		T32	8		T85	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T32	13		T96	17		T108	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T18	5		T135	3		T213	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T113	1		T197	1		T111	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1234	1			T14	2		T15	3		T16	29
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T108	1		T201	3		T124	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T33	3		T118	14		T161	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T19	6		T106	1		T164	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T107	8		T270	1		T212	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T18	2		T101	1		T232	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T32	1		T104	1		T90	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T13	7		T19	3		T105	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T20	1		T97	1		T113	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T20	1		T32	17		T99	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16832	1			T18	98		T32	14		T28	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T22	6		T254	2		T186	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T131	11		T200	6		T215	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T22	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T208	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T22	10		T100	7		T164	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T13	2		T198	5		T197	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T19	4		T98	13		T164	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T162	8		T165	18		T140	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T21	5		T32	7		T85	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T32	5		T248	13		T289	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T18	1		T162	2		T124	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T113	1		T197	4		T111	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	943	1			T17	20		T95	20		T274	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T201	12		T208	11		T225	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T33	5		T118	5		T161	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T19	9		T164	7		T121	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T107	5		T123	10		T226	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T203	9		T321	14		T275	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T32	11		T104	1		T90	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T13	9		T97	12		T129	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T20	14		T97	1		T110	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T20	9		T32	9		T100	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T5	2		T6	1		T27	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T105	1		T113	1		T99	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T13	3		T88	5		T198	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T19	5		T21	6		T106	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T159	1		T162	9		T165	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T32	8		T89	5		T31	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T32	6		T96	1		T108	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1326	1			T14	2		T15	1		T16	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T113	2		T197	5		T111	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T118	3		T109	8		T115	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T106	1		T108	1		T201	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T33	6		T118	7		T161	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T19	10		T164	8		T202	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T107	6		T90	14		T270	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T18	2		T105	1		T97	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T32	12		T104	2		T110	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T13	10		T19	1		T106	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T20	15		T22	7		T113	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T32	10		T99	1		T100	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T97	2		T239	9		T333	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T20	10		T101	1		T214	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17065	1			T5	2		T6	1		T27	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T124	2		T208	10		T190	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T100	10		T103	5		T204	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T13	3		T88	2		T102	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T21	2		T98	3		T145	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T165	12		T210	10		T120	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T32	7		T89	1		T31	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T32	12		T96	16		T135	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	928	1			T15	2		T16	26		T18	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T111	9		T210	9		T209	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T118	9		T109	7		T211	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T201	1		T124	8		T208	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T33	2		T118	12		T251	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T19	5		T117	3		T137	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T107	7		T90	14		T212	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T97	9		T255	1		T245	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T110	15		T100	10		T202	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T13	6		T19	2		T129	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T22	6		T113	12		T136	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T32	16		T100	13		T136	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T239	5		T334	4		T335	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T214	14		T277	11		T215	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T22	11		T104	6		T218	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T208	3		T190	1		T224	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T22	7		T254	3		T186	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T166	1		T131	12		T319	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T22	8		T320	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T208	10		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T22	11		T104	1		T105	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T13	3		T198	6		T197	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T19	5		T106	1		T98	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T88	5		T162	9		T165	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T21	6		T32	8		T85	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T32	6		T96	1		T108	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T18	4		T135	1		T213	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T113	2		T197	5		T111	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1267	1			T14	2		T15	1		T16	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T108	1		T201	14		T124	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T33	6		T118	7		T161	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T19	10		T106	1		T164	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T107	6		T270	1		T212	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T18	2		T101	1		T232	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T32	12		T104	2		T90	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T13	10		T19	1		T105	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T20	15		T97	2		T113	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	357	1			T20	10		T32	10		T99	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16979	1			T5	2		T6	1		T27	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T22	6		T239	5		T284	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T166	9		T131	11		T277	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T22	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T208	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T22	4		T104	6		T100	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T13	3		T102	13		T120	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T98	3		T103	5		T145	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T88	2		T165	12		T210	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T21	2		T32	7		T85	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T32	12		T96	16		T135	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T18	2		T135	2		T213	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T111	9		T122	7		T210	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	910	1			T15	2		T16	26		T256	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T201	1		T124	8		T208	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T33	2		T118	12		T251	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T19	5		T117	3		T214	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T107	7		T212	9		T166	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T137	7		T130	10		T238	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T90	14		T110	9		T202	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T13	6		T19	2		T97	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T113	12		T110	6		T100	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T32	16		T100	13		T136	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21597

1

T5

2

T6

1

T27

2

auto[1]

auto[0]

3396

1

T13

9

T15

2

T16

26