Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T108	1		T90	14		T99	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T32	12		T113	1		T98	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T18	4		T32	8		T106	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1333	1			T15	1		T16	3		T17	23
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T14	1		T88	5		T108	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T22	11		T89	5		T118	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T115	14		T136	2		T223	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T19	15		T22	8		T118	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T85	14		T106	1		T198	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T96	1		T98	12		T99	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T20	15		T22	7		T32	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T204	12		T224	5		T225	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T105	1		T226	7		T214	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T118	3		T135	1		T110	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T105	1		T107	6		T97	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T100	26		T102	19		T212	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T18	2		T33	6		T104	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T13	10		T19	1		T20	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T123	11		T147	15		T227	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T137	1		T222	1		T228	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17040	1			T5	2		T6	1		T27	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T13	3		T14	1		T111	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T90	14		T236	5		T168	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T98	3		T210	10		T103	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T18	2		T32	7		T137	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	927	1			T15	2		T16	26		T21	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T88	2		T119	3		T211	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T22	4		T89	1		T118	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T204	4		T130	10		T238	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T19	5		T22	7		T118	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T85	1		T239	5		T240	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T96	16		T98	8		T100	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T22	6		T32	12		T109	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T204	12		T224	4		T241	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T214	7		T129	12		T131	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T118	9		T135	2		T110	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T107	7		T97	9		T110	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T100	23		T102	13		T212	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T33	2		T104	6		T31	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T13	6		T19	2		T32	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T147	10		T242	2		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T137	17		T243	6		T230	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T236	6		T241	14		T154	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T13	3		T111	9		T201	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T31	1		T127	1		T231	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T164	5		T195	9		T127	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T221	1		T157	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T108	1		T99	1		T159	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T13	3		T14	1		T32	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T32	8		T106	1		T90	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T113	1		T101	1		T161	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T18	4		T88	5		T97	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T21	6		T22	11		T89	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T14	1		T136	2		T223	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T19	15		T22	8		T136	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T85	14		T106	1		T115	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T96	1		T118	4		T98	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T20	15		T22	7		T109	24
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T162	9		T224	11		T185	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T32	6		T105	1		T232	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T118	3		T135	1		T110	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T107	6		T97	13		T110	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T100	18		T212	1		T121	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T18	2		T33	6		T104	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1331	1			T13	10		T15	1		T16	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16979	1			T5	2		T6	1		T27	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T31	6		T209	11		T234	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T195	2		T137	17		T235	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T157	16		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T236	11		T168	3		T241	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T13	3		T98	3		T111	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T32	7		T90	14		T137	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T113	12		T102	2		T103	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T18	2		T88	2		T119	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T21	2		T22	4		T89	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T204	4		T130	10		T238	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T19	5		T22	7		T136	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T85	1		T239	5		T240	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T96	16		T118	2		T98	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T22	6		T109	20		T135	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T224	11		T241	9		T244	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T32	12		T214	7		T245	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T118	9		T135	2		T110	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T107	7		T97	9		T110	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T100	13		T212	9		T117	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T33	2		T104	6		T210	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	917	1			T13	6		T15	2		T16	26

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21597

1

T5

2

T6

1

T27

2

auto[1]

auto[0]

3396

1

T13

9

T15

2

T16

26