Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24993

1

T5

2

T6

1

T27

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20006

1

T5

2

T6

1

T27

2

auto[ADC_CTRL_FILTER_COND_OUT]

4987

1

T13

22

T14

1

T15

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19540

1

T5

2

T6

1

T27

2

auto[1]

5453

1

T13

16

T14

1

T15

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21262

1

T13

11

T14

2

T15

3

auto[1]

3731

1

T5

2

T6

1

T27

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	19	1			T127	1		T243	7		T157	11
values[0]	29	1			T261	1		T262	15		T221	1
values[1]	597	1			T13	6		T14	1		T32	12
values[2]	583	1			T32	15		T106	1		T113	13
values[3]	776	1			T18	6		T21	8		T22	15
values[4]	719	1			T14	1		T19	20		T22	15
values[5]	480	1			T85	15		T96	17		T118	6
values[6]	539	1			T20	15		T22	13		T106	1
values[7]	735	1			T32	18		T105	1		T118	12
values[8]	563	1			T107	13		T110	19		T100	31
values[9]	2974	1			T13	16		T15	3		T16	29
minimum	16979	1			T5	2		T6	1		T27	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	690	1			T13	6		T14	1		T32	12
values[1]	2531	1			T15	3		T16	29		T17	23
values[2]	744	1			T14	1		T22	15		T88	7
values[3]	708	1			T19	20		T22	15		T118	6
values[4]	538	1			T20	15		T85	15		T106	1
values[5]	611	1			T22	13		T32	18		T109	29
values[6]	657	1			T105	1		T118	12		T135	3
values[7]	604	1			T105	1		T107	13		T97	22
values[8]	717	1			T13	16		T18	2		T19	3
values[9]	197	1			T113	2		T164	5		T123	11
minimum	16996	1			T5	2		T6	1		T27	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21597

1

T5

2

T6

1

T27

2

auto[1]

3396

1

T13

9

T15

2

T16

26

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T108	1		T90	15		T99	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T13	4		T14	1		T32	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T18	5		T32	8		T106	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1265	1			T15	3		T16	29		T17	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T14	1		T88	7		T108	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T22	5		T89	5		T136	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T115	1		T136	1		T223	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T19	7		T22	8		T118	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T20	1		T85	5		T106	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T96	17		T98	9		T99	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T22	7		T32	13		T109	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T165	13		T204	13		T224	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T105	1		T161	1		T226	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T118	10		T135	3		T110	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T105	1		T107	8		T97	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T100	25		T102	14		T212	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T18	2		T33	3		T104	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T13	7		T19	3		T20	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T123	1		T233	1		T251	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T113	1		T164	1		T233	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16840	1			T18	98		T32	14		T28	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T263	1		T264	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T90	13		T123	13		T208	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T13	2		T32	11		T98	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T18	1		T32	7		T97	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1004	1			T17	20		T21	5		T95	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T197	10		T119	6		T190	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T22	10		T89	1		T136	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T115	13		T136	1		T204	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T19	13		T22	7		T118	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T20	14		T85	10		T109	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T98	11		T162	8		T124	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T22	6		T32	5		T109	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T165	18		T204	11		T224	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T161	7		T226	6		T214	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T118	2		T110	16		T115	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T107	5		T97	12		T110	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T100	24		T102	18		T121	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T33	5		T104	1		T197	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T13	9		T20	9		T32	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T123	10		T233	11		T251	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T113	1		T164	4		T233	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T5	2		T6	1		T27	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T263	1		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T127	1		T157	11		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T243	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T221	1		T265	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T261	1		T262	8		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T108	1		T99	1		T159	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T13	4		T14	1		T32	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T32	8		T106	1		T90	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T113	13		T101	1		T161	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T18	5		T88	7		T97	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T21	3		T22	5		T89	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T14	1		T136	1		T223	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T19	7		T22	8		T136	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T85	5		T198	1		T115	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T96	17		T118	3		T98	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T20	1		T22	7		T106	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T100	11		T162	1		T266	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T32	13		T105	1		T232	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T118	10		T135	3		T110	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T107	8		T110	10		T101	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T100	14		T212	10		T121	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	340	1			T18	2		T33	3		T104	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1340	1			T13	7		T15	3		T16	29
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16832	1			T18	98		T32	14		T28	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T265	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T262	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T123	13		T208	11		T236	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T13	2		T32	11		T98	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T32	7		T90	13		T164	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T161	3		T165	2		T103	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T18	1		T97	1		T197	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T21	5		T22	10		T89	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T136	1		T204	4		T140	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T19	13		T22	7		T136	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T85	10		T198	5		T115	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T118	3		T98	11		T123	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T20	14		T22	6		T109	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T162	8		T224	5		T185	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T32	5		T226	6		T214	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T118	2		T110	16		T115	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T107	5		T110	9		T226	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T100	17		T121	9		T117	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T33	5		T104	1		T97	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1039	1			T13	9		T17	20		T20	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T5	2		T6	1		T27	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T108	1		T90	14		T99	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T13	3		T14	1		T32	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T18	4		T32	8		T106	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1334	1			T15	1		T16	3		T17	23
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T14	1		T88	5		T108	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T22	11		T89	5		T136	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T115	14		T136	2		T223	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T19	15		T22	8		T118	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T20	15		T85	14		T106	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T96	1		T98	12		T99	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T22	7		T32	6		T109	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T165	19		T204	12		T224	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T105	1		T161	8		T226	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T118	3		T135	1		T110	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T105	1		T107	6		T97	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T100	26		T102	19		T212	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T18	2		T33	6		T104	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T13	10		T19	1		T20	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T123	11		T233	12		T251	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T113	2		T164	5		T233	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16987	1			T5	2		T6	1		T27	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T263	2		T264	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T90	14		T208	11		T236	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T13	3		T98	3		T111	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T18	2		T32	7		T137	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	935	1			T15	2		T16	26		T21	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T88	2		T119	3		T211	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T22	4		T89	1		T136	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T204	4		T130	10		T238	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T19	5		T22	7		T118	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T85	1		T109	7		T213	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T96	16		T98	8		T100	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T22	6		T32	12		T109	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T165	12		T204	12		T224	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T214	7		T129	12		T131	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T118	9		T135	2		T110	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T107	7		T97	9		T110	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T100	23		T102	13		T212	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T33	2		T104	6		T31	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T13	6		T19	2		T32	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T251	10		T147	10		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T233	2		T235	14		T267	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T236	6		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T127	1		T157	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T243	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T221	1		T265	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T261	1		T262	8		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T108	1		T99	1		T159	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T13	3		T14	1		T32	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T32	8		T106	1		T90	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T113	1		T101	1		T161	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T18	4		T88	5		T97	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T21	6		T22	11		T89	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T14	1		T136	2		T223	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T19	15		T22	8		T136	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T85	14		T198	6		T115	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T96	1		T118	4		T98	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T20	15		T22	7		T106	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T100	1		T162	9		T266	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T32	6		T105	1		T232	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T118	3		T135	1		T110	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T107	6		T110	10		T101	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T100	18		T212	1		T121	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	326	1			T18	2		T33	6		T104	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1393	1			T13	10		T15	1		T16	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16979	1			T5	2		T6	1		T27	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T157	10		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T243	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T262	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T208	11		T268	8		T236	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T13	3		T98	3		T111	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T32	7		T90	14		T137	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T113	12		T102	2		T103	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T18	2		T88	2		T119	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T21	2		T22	4		T89	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T204	4		T130	10		T238	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T19	5		T22	7		T136	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T85	1		T239	5		T240	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T96	16		T118	2		T98	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T22	6		T109	20		T135	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T100	10		T224	7		T244	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T32	12		T214	7		T269	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T118	9		T135	2		T110	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T107	7		T110	9		T102	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T100	13		T212	9		T117	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T33	2		T104	6		T97	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	986	1			T13	6		T15	2		T16	26

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21597

1

T5

2

T6

1

T27

2

auto[1]

auto[0]

3396

1

T13

9

T15

2

T16

26