Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24993

1

T5

2

T6

1

T27

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21783

1

T5

2

T6

1

T27

2

auto[ADC_CTRL_FILTER_COND_OUT]

3210

1

T13

22

T14

1

T18

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19401

1

T5

2

T6

1

T27

2

auto[1]

5592

1

T14

1

T15

3

T16

29

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21262

1

T13

11

T14

2

T15

3

auto[1]

3731

1

T5

2

T6

1

T27

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	544	1			T18	6		T29	2		T30	7
values[0]	39	1			T22	15		T118	12		T136	2
values[1]	647	1			T33	8		T104	2		T107	13
values[2]	2598	1			T13	16		T15	3		T16	29
values[3]	732	1			T197	11		T122	2		T102	32
values[4]	441	1			T18	2		T32	12		T106	1
values[5]	614	1			T118	13		T108	1		T197	5
values[6]	702	1			T14	1		T18	6		T19	5
values[7]	446	1			T20	15		T97	2		T113	1
values[8]	680	1			T14	1		T32	18		T89	6
values[9]	1037	1			T13	6		T19	18		T21	8
minimum	16513	1			T5	2		T6	1		T27	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	856	1			T22	15		T33	8		T107	13
values[1]	2609	1			T13	16		T15	3		T16	29
values[2]	711	1			T115	7		T122	2		T164	5
values[3]	407	1			T18	2		T32	12		T106	1
values[4]	727	1			T32	15		T118	19		T197	5
values[5]	522	1			T14	1		T18	6		T19	5
values[6]	531	1			T89	6		T97	24		T31	7
values[7]	704	1			T14	1		T20	15		T32	18
values[8]	821	1			T19	18		T21	8		T22	28
values[9]	114	1			T13	6		T32	26		T135	5
minimum	16991	1			T5	2		T6	1		T27	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21597

1

T5

2

T6

1

T27

2

auto[1]

3396

1

T13

9

T15

2

T16

26

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T107	8		T90	15		T110	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T22	5		T33	3		T96	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1285	1			T15	3		T16	29		T17	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T13	7		T20	1		T105	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T115	1		T122	1		T102	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T164	1		T120	12		T209	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T18	2		T32	1		T108	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T106	1		T164	1		T125	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T99	1		T100	11		T102	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T32	8		T118	14		T197	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T19	1		T106	1		T270	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T14	1		T18	5		T104	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T89	5		T97	1		T213	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T97	10		T31	7		T110	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T14	1		T20	1		T32	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T159	1		T101	1		T103	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T21	3		T22	15		T109	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T19	9		T85	5		T113	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T32	17		T135	5		T229	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T13	4		T165	1		T271	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16832	1			T18	98		T32	14		T28	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T118	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T107	5		T90	13		T110	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T22	10		T33	5		T198	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	952	1			T17	20		T95	20		T104	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T13	9		T20	9		T113	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T115	6		T122	1		T102	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T164	4		T233	11		T186	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T32	11		T98	11		T190	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T164	7		T125	17		T233	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T100	7		T226	17		T125	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T32	7		T118	5		T197	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T19	4		T162	8		T117	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T18	1		T110	16		T214	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T89	1		T97	1		T164	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T97	12		T110	9		T226	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T20	14		T32	5		T114	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T103	5		T248	7		T250	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T21	5		T22	13		T109	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T19	9		T85	10		T115	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T32	9		T229	1		T241	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T13	2		T165	2		T258	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T5	2		T6	1		T27	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T118	2		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	488	1			T18	6		T29	2		T30	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T254	1		T272	1		T188	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T136	1		T139	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T22	5		T118	10		T224	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T104	1		T107	8		T90	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T33	3		T96	17		T108	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1250	1			T15	3		T16	29		T17	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T13	7		T20	1		T105	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T122	1		T102	14		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T197	1		T120	12		T209	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T18	2		T32	1		T115	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T106	1		T164	2		T233	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T108	1		T98	9		T99	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T118	11		T197	1		T159	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T19	1		T106	1		T213	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T14	1		T18	5		T32	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T20	1		T97	1		T164	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T113	1		T31	7		T110	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T14	1		T32	13		T89	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T97	10		T103	8		T207	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T21	3		T22	15		T32	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T13	4		T19	9		T85	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16366	1			T18	92		T32	14		T28	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T254	11		T188	9		T273	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T136	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T22	10		T118	2		T224	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T104	1		T107	5		T90	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T33	5		T198	5		T115	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	921	1			T17	20		T95	20		T274	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T13	9		T20	9		T113	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T122	1		T102	18		T249	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T197	10		T233	11		T186	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T32	11		T115	6		T204	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T164	11		T233	2		T275	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T98	11		T190	1		T125	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T118	2		T197	4		T121	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T19	4		T100	7		T162	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T18	1		T32	7		T118	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T20	14		T97	1		T164	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T110	9		T226	6		T251	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T32	5		T89	1		T103	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T97	12		T103	5		T207	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T21	5		T22	13		T32	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T13	2		T19	9		T85	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T5	2		T6	1		T27	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T107	6		T90	14		T110	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T22	11		T33	6		T96	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1290	1			T15	1		T16	3		T17	23
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T13	10		T20	10		T105	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T115	7		T122	2		T102	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T164	5		T120	1		T209	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T18	2		T32	12		T108	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T106	1		T164	8		T125	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T99	1		T100	8		T102	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T32	8		T118	7		T197	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T19	5		T106	1		T270	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T14	1		T18	4		T104	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T89	5		T97	2		T213	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T97	13		T31	1		T110	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T14	1		T20	15		T32	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T159	1		T101	1		T103	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T21	6		T22	15		T109	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T19	11		T85	14		T113	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T32	10		T135	1		T229	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T13	3		T165	3		T271	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16979	1			T5	2		T6	1		T27	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T118	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T107	7		T90	14		T110	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T22	4		T33	2		T96	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	947	1			T15	2		T16	26		T88	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T13	6		T109	7		T135	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T102	13		T238	8		T168	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T120	11		T209	2		T166	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T98	8		T190	1		T204	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T233	2		T211	7		T146	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T100	10		T102	2		T212	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T32	7		T118	12		T100	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T117	9		T166	3		T269	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T18	2		T104	6		T110	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T89	1		T213	4		T119	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T97	9		T31	6		T110	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T32	12		T103	2		T207	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T103	5		T126	15		T131	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T21	2		T22	13		T109	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T19	7		T85	1		T113	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T32	16		T135	4		T241	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T13	3		T271	7		T258	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T118	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	468	1			T18	6		T29	2		T30	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T254	12		T272	1		T188	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T136	2		T139	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T22	11		T118	3		T224	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T104	2		T107	6		T90	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T33	6		T96	1		T108	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1246	1			T15	1		T16	3		T17	23
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T13	10		T20	10		T105	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T122	2		T102	19		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T197	11		T120	1		T209	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T18	2		T32	12		T115	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T106	1		T164	13		T233	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T108	1		T98	12		T99	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T118	3		T197	5		T159	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T19	5		T106	1		T213	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T14	1		T18	4		T32	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T20	15		T97	2		T164	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T113	1		T31	1		T110	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T14	1		T32	6		T89	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T97	13		T103	8		T207	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T21	6		T22	15		T32	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T13	3		T19	11		T85	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16513	1			T5	2		T6	1		T27	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T210	9		T238	11		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T188	7		T273	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T22	4		T118	9		T224	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T107	7		T90	14		T110	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T33	2		T96	16		T165	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	925	1			T15	2		T16	26		T88	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T13	6		T109	7		T135	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T102	13		T210	10		T204	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T120	11		T209	2		T166	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T204	10		T257	8		T238	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T233	2		T255	12		T275	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T98	8		T212	9		T190	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T118	10		T214	7		T209	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T213	4		T100	10		T102	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T18	2		T32	7		T104	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T119	3		T124	8		T276	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T31	6		T110	9		T251	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T32	12		T89	1		T103	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T97	9		T103	5		T207	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T21	2		T22	13		T32	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T13	3		T19	7		T85	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21597

1

T5

2

T6

1

T27

2

auto[1]

auto[0]

3396

1

T13

9

T15

2

T16

26