Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24993

1

T5

2

T6

1

T27

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21937

1

T5

2

T6

1

T27

2

auto[ADC_CTRL_FILTER_COND_OUT]

3056

1

T14

1

T18

6

T19

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19690

1

T5

2

T6

1

T27

2

auto[1]

5303

1

T13

16

T15

3

T16

29

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21262

1

T13

11

T14

2

T15

3

auto[1]

3731

1

T5

2

T6

1

T27

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	20	1			T117	12		T199	6		T216	2
values[0]	69	1			T159	1		T138	11		T277	12
values[1]	505	1			T13	16		T22	13		T31	7
values[2]	782	1			T18	6		T21	8		T32	18
values[3]	560	1			T14	1		T19	3		T89	6
values[4]	779	1			T22	15		T105	2		T198	6
values[5]	2613	1			T15	3		T16	29		T17	23
values[6]	499	1			T14	1		T20	10		T113	1
values[7]	575	1			T32	53		T85	15		T106	1
values[8]	460	1			T33	8		T106	1		T113	2
values[9]	1152	1			T13	6		T18	2		T19	20
minimum	16979	1			T5	2		T6	1		T27	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	831	1			T13	16		T22	13		T31	7
values[1]	677	1			T14	1		T18	6		T21	8
values[2]	643	1			T19	3		T118	13		T98	20
values[3]	2644	1			T15	3		T16	29		T17	23
values[4]	614	1			T14	1		T107	13		T88	7
values[5]	556	1			T20	10		T32	41		T85	15
values[6]	512	1			T33	8		T32	12		T99	1
values[7]	571	1			T106	1		T113	2		T108	1
values[8]	797	1			T13	6		T18	2		T19	20
values[9]	161	1			T104	2		T125	18		T196	15
minimum	16987	1			T5	2		T6	1		T27	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21597

1

T5

2

T6

1

T27

2

auto[1]

3396

1

T13

9

T15

2

T16

26

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T13	7		T22	7		T197	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T31	7		T109	22		T100	25
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T21	3		T90	15		T197	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T14	1		T18	5		T32	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T118	11		T102	3		T165	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T19	3		T98	9		T111	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1231	1			T15	3		T16	29		T17	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T105	1		T96	17		T198	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T14	1		T107	8		T113	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T88	7		T115	1		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T32	17		T85	5		T108	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T20	1		T32	8		T106	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T99	1		T212	10		T203	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T33	3		T32	1		T159	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T106	1		T113	1		T108	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T135	3		T110	7		T162	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T13	4		T18	2		T19	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T20	1		T104	7		T135	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T125	1		T140	1		T199	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T104	1		T196	10		T186	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16832	1			T18	98		T32	14		T28	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T278	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T13	9		T22	6		T197	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T109	22		T100	17		T164	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T21	5		T90	13		T197	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T18	1		T32	5		T89	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T118	2		T165	2		T121	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T98	11		T111	7		T201	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	987	1			T17	20		T22	17		T95	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T198	5		T100	7		T161	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T107	5		T115	13		T122	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T115	2		T136	1		T202	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T32	9		T85	10		T136	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T20	9		T32	7		T117	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T203	4		T244	1		T279	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T33	5		T32	11		T204	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T113	1		T114	9		T98	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T110	6		T162	8		T123	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T13	2		T19	13		T97	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T20	14		T161	12		T164	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T125	17		T140	9		T199	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T104	1		T196	5		T241	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T5	2		T6	1		T27	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T117	10		T199	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T216	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T277	12		T280	14		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T159	1		T138	1		T194	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T13	7		T22	7		T231	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T31	7		T109	22		T100	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T21	3		T90	15		T197	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T18	5		T32	13		T99	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T118	11		T102	3		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T14	1		T19	3		T89	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T22	5		T105	1		T115	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T105	1		T198	1		T98	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1251	1			T15	3		T16	29		T17	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T88	7		T96	17		T161	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T14	1		T108	1		T136	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T20	1		T113	1		T115	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T32	17		T85	5		T206	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T32	9		T106	1		T159	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T106	1		T113	1		T108	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T33	3		T135	3		T110	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	335	1			T13	4		T18	2		T19	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T20	1		T104	8		T135	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16832	1			T18	98		T32	14		T28	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T117	2		T199	5		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T280	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T138	10		T194	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T13	9		T22	6		T281	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T109	22		T164	7		T275	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T21	5		T90	13		T197	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T18	1		T32	5		T100	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T118	2		T121	14		T233	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T89	1		T207	2		T225	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T22	10		T115	6		T165	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T198	5		T98	11		T111	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	968	1			T17	20		T22	7		T95	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T161	3		T103	7		T125	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T136	10		T165	18		T208	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T20	9		T115	2		T136	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T32	9		T85	10		T162	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T32	18		T117	8		T124	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T113	1		T98	13		T208	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T33	5		T110	6		T123	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	334	1			T13	2		T19	13		T97	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T20	14		T104	1		T161	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T5	2		T6	1		T27	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T13	10		T22	7		T197	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T31	1		T109	24		T100	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T21	6		T90	14		T197	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T14	1		T18	4		T32	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T118	3		T102	1		T165	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T19	1		T98	12		T111	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1310	1			T15	1		T16	3		T17	23
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T105	1		T96	1		T198	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T14	1		T107	6		T113	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T88	5		T115	3		T136	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T32	10		T85	14		T108	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T20	10		T32	8		T106	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T99	1		T212	1		T203	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T33	6		T32	12		T159	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T106	1		T113	2		T108	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T135	1		T110	7		T162	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T13	3		T18	2		T19	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T20	15		T104	1		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T125	18		T140	10		T199	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T104	2		T196	12		T186	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16979	1			T5	2		T6	1		T27	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T278	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T13	6		T22	6		T102	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T31	6		T109	20		T100	23
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T21	2		T90	14		T110	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T18	2		T32	12		T89	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T118	10		T102	2		T209	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T19	2		T98	8		T111	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	908	1			T15	2		T16	26		T22	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T96	16		T100	10		T103	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T107	7		T113	12		T122	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T88	2		T202	6		T211	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T32	16		T85	1		T136	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T32	7		T117	3		T124	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T212	9		T219	11		T244	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T33	2		T204	4		T211	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T98	3		T213	4		T120	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T135	2		T110	6		T214	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T13	3		T19	5		T97	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T104	6		T135	4		T195	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T282	8		T283	10		T284	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T196	3		T216	1		T241	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T278	7		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T117	3		T199	6		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T216	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T277	1		T280	17		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T159	1		T138	11		T194	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T13	10		T22	7		T231	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T31	1		T109	24		T100	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T21	6		T90	14		T197	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T18	4		T32	6		T99	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T118	3		T102	1		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T14	1		T19	1		T89	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T22	11		T105	1		T115	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T105	1		T198	6		T98	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1295	1			T15	1		T16	3		T17	23
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T88	5		T96	1		T161	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T14	1		T108	1		T136	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T20	10		T113	1		T115	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T32	10		T85	14		T206	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T32	20		T106	1		T159	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T106	1		T113	2		T108	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T33	6		T135	1		T110	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	407	1			T13	3		T18	2		T19	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T20	15		T104	3		T135	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16979	1			T5	2		T6	1		T27	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T117	9		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T216	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T277	11		T280	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T285	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T13	6		T22	6		T120	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T31	6		T109	20		T100	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T21	2		T90	14		T110	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T18	2		T32	12		T100	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T118	10		T102	2		T209	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T19	2		T89	1		T207	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T22	4		T214	14		T204	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T98	8		T111	9		T100	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	924	1			T15	2		T16	26		T22	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T88	2		T96	16		T103	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T136	11		T165	12		T210	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T202	6		T211	7		T130	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T32	16		T85	1		T131	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T32	7		T117	3		T124	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T98	3		T213	4		T212	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T33	2		T135	2		T110	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T13	3		T19	5		T97	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T104	6		T135	4		T195	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21597

1

T5

2

T6

1

T27

2

auto[1]

auto[0]

3396

1

T13

9

T15

2

T16

26