Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24993

1

T5

2

T6

1

T27

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21850

1

T5

2

T6

1

T27

2

auto[ADC_CTRL_FILTER_COND_OUT]

3143

1

T13

6

T14

1

T18

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19343

1

T5

2

T6

1

T27

2

auto[1]

5650

1

T13

22

T14

1

T15

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21262

1

T13

11

T14

2

T15

3

auto[1]

3731

1

T5

2

T6

1

T27

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	30	1			T286	7		T217	10		T287	1
values[0]	103	1			T231	1		T126	14		T246	27
values[1]	476	1			T32	33		T118	12		T113	13
values[2]	544	1			T104	7		T106	1		T115	14
values[3]	639	1			T14	1		T18	2		T20	10
values[4]	2512	1			T15	3		T16	29		T17	23
values[5]	677	1			T22	15		T32	26		T89	6
values[6]	685	1			T22	15		T104	2		T118	6
values[7]	477	1			T13	16		T97	22		T122	2
values[8]	630	1			T14	1		T21	8		T33	8
values[9]	1241	1			T13	6		T18	6		T19	8
minimum	16979	1			T5	2		T6	1		T27	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	725	1			T32	33		T118	12		T113	13
values[1]	477	1			T18	2		T20	10		T104	7
values[2]	735	1			T14	1		T97	2		T31	7
values[3]	2532	1			T15	3		T16	29		T17	23
values[4]	626	1			T32	26		T89	6		T109	29
values[5]	697	1			T22	15		T104	2		T97	22
values[6]	445	1			T13	16		T108	1		T122	2
values[7]	606	1			T19	5		T21	8		T33	8
values[8]	903	1			T13	6		T14	1		T19	3
values[9]	224	1			T18	6		T197	11		T115	7
minimum	17023	1			T5	2		T6	1		T27	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21597

1

T5

2

T6

1

T27

2

auto[1]

3396

1

T13

9

T15

2

T16

26

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T32	13		T118	10		T113	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T32	8		T108	1		T161	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T18	2		T104	7		T99	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T20	1		T106	1		T115	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T14	1		T97	1		T100	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T31	7		T98	13		T110	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1142	1			T15	3		T16	29		T17	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T19	6		T22	15		T105	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T32	17		T89	5		T206	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T109	14		T114	1		T197	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T22	5		T104	1		T97	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T113	1		T109	8		T111	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T13	7		T108	1		T136	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T122	1		T164	1		T210	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T19	1		T21	3		T105	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T33	3		T106	1		T118	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T32	1		T198	1		T124	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T13	4		T14	1		T19	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T209	3		T248	1		T266	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T18	5		T197	1		T115	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16832	1			T18	98		T32	14		T28	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T103	8		T288	18		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T32	5		T118	2		T103	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T32	7		T161	12		T249	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T162	2		T164	7		T123	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T20	9		T115	13		T226	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T97	1		T100	17		T125	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T98	24		T110	16		T202	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	926	1			T17	20		T20	14		T95	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T19	9		T22	13		T100	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T32	9		T89	1		T289	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T109	15		T114	9		T197	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T22	10		T104	1		T97	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T109	7		T111	7		T161	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T13	9		T136	10		T165	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T122	1		T164	13		T207	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T19	4		T21	5		T107	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T33	5		T118	2		T110	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T32	11		T198	5		T124	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T13	2		T85	10		T90	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T248	13		T250	13		T221	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T18	1		T197	10		T115	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T5	2		T6	1		T27	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T103	5		T288	13		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T290	2		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T286	5		T217	10		T287	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T231	1		T284	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T126	3		T246	18		T288	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T32	13		T118	10		T113	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T32	8		T108	1		T161	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T104	7		T164	1		T102	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T106	1		T115	1		T159	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T14	1		T18	2		T97	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T20	1		T98	4		T226	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1181	1			T15	3		T16	29		T17	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T19	6		T22	7		T105	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T32	17		T89	5		T206	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T22	8		T109	14		T114	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T22	5		T104	1		T118	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T113	1		T109	8		T111	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T13	7		T97	10		T136	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T122	1		T165	13		T210	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T21	3		T106	1		T96	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T14	1		T33	3		T106	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	333	1			T19	1		T32	1		T105	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	341	1			T13	4		T18	5		T19	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16832	1			T18	98		T32	14		T28	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T290	1		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T286	2		T258	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T126	11		T246	9		T288	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T32	5		T118	2		T103	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T32	7		T161	12		T103	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T164	7		T123	13		T226	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T115	13		T204	11		T224	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T97	1		T100	17		T162	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T20	9		T98	13		T226	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	936	1			T17	20		T20	14		T95	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T19	9		T22	6		T98	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T32	9		T89	1		T121	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T22	7		T109	15		T114	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T22	10		T104	1		T118	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T109	7		T111	7		T161	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T13	9		T97	12		T136	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T122	1		T165	18		T207	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T21	5		T117	2		T254	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T33	5		T110	9		T164	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T19	4		T32	11		T107	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T13	2		T18	1		T85	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T5	2		T6	1		T27	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T32	6		T118	3		T113	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T32	8		T108	1		T161	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T18	2		T104	1		T99	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T20	10		T106	1		T115	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T14	1		T97	2		T100	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T31	1		T98	26		T110	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1242	1			T15	1		T16	3		T17	23
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T19	10		T22	15		T105	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T32	10		T89	5		T206	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T109	16		T114	10		T197	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T22	11		T104	2		T97	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T113	1		T109	8		T111	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T13	10		T108	1		T136	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T122	2		T164	14		T210	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T19	5		T21	6		T105	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T33	6		T106	1		T118	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T32	12		T198	6		T124	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T13	3		T14	1		T19	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T209	1		T248	14		T266	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T18	4		T197	11		T115	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16979	1			T5	2		T6	1		T27	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T103	8		T288	14		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T32	12		T118	9		T113	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T32	7		T190	1		T255	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T104	6		T102	2		T214	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T124	8		T209	11		T129	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T100	13		T255	17		T211	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T31	6		T98	11		T110	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	826	1			T15	2		T16	26		T256	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T19	5		T22	13		T100	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T32	16		T89	1		T289	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T109	13		T122	7		T212	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T22	4		T97	9		T118	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T109	7		T111	9		T165	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T13	6		T136	11		T281	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T210	9		T207	14		T145	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T21	2		T107	7		T96	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T33	2		T118	10		T135	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T208	3		T137	7		T257	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T13	3		T19	2		T85	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T209	2		T132	1		T253	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T18	2		T291	1		T258	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T103	5		T288	17		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T290	3		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T286	5		T217	1		T287	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T231	1		T284	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T126	12		T246	10		T288	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T32	6		T118	3		T113	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T32	8		T108	1		T161	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T104	1		T164	8		T102	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T106	1		T115	14		T159	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T14	1		T18	2		T97	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T20	10		T98	14		T226	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1265	1			T15	1		T16	3		T17	23
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T19	10		T22	7		T105	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T32	10		T89	5		T206	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T22	8		T109	16		T114	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T22	11		T104	2		T118	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T113	1		T109	8		T111	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T13	10		T97	13		T136	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T122	2		T165	19		T210	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T21	6		T106	1		T96	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T14	1		T33	6		T106	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	381	1			T19	5		T32	12		T105	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	353	1			T13	3		T18	4		T19	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16979	1			T5	2		T6	1		T27	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T286	2		T217	9		T258	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T284	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T126	2		T246	17		T288	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T32	12		T118	9		T113	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T32	7		T103	5		T190	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T104	6		T102	2		T208	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T124	8		T209	11		T204	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T100	13		T255	17		T211	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T98	3		T251	10		T137	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	852	1			T15	2		T16	26		T256	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T19	5		T22	6		T31	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T32	16		T89	1		T260	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T22	7		T109	13		T122	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T22	4		T118	2		T100	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T109	7		T111	9		T212	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T13	6		T97	9		T136	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T165	12		T210	9		T207	27
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T21	2		T96	16		T210	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T33	2		T110	9		T195	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T107	7		T208	3		T209	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T13	3		T18	2		T19	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21597

1

T5

2

T6

1

T27

2

auto[1]

auto[0]

3396

1

T13

9

T15

2

T16

26