Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24993

1

T5

2

T6

1

T27

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21759

1

T5

2

T6

1

T27

2

auto[ADC_CTRL_FILTER_COND_OUT]

3234

1

T13

16

T14

1

T18

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19623

1

T5

2

T6

1

T27

2

auto[1]

5370

1

T14

1

T15

3

T16

29

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21262

1

T13

11

T14

2

T15

3

auto[1]

3731

1

T5

2

T6

1

T27

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	244	1			T22	13		T115	3		T212	10
values[0]	18	1			T207	17		T292	1		-	-
values[1]	704	1			T18	6		T106	2		T107	13
values[2]	563	1			T20	15		T21	8		T32	18
values[3]	517	1			T13	16		T33	8		T108	1
values[4]	560	1			T13	6		T88	7		T118	6
values[5]	530	1			T14	1		T32	53		T197	16
values[6]	706	1			T19	15		T22	15		T85	15
values[7]	703	1			T105	1		T106	1		T113	2
values[8]	641	1			T19	8		T97	2		T109	29
values[9]	2828	1			T14	1		T15	3		T16	29
minimum	16979	1			T5	2		T6	1		T27	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	614	1			T18	6		T106	1		T107	13
values[1]	575	1			T20	15		T21	8		T33	8
values[2]	569	1			T13	22		T108	1		T198	6
values[3]	506	1			T88	7		T118	6		T113	14
values[4]	587	1			T14	1		T19	15		T22	15
values[5]	709	1			T85	15		T113	2		T31	7
values[6]	2512	1			T15	3		T16	29		T17	23
values[7]	697	1			T14	1		T19	3		T97	2
values[8]	911	1			T18	2		T22	28		T104	2
values[9]	101	1			T20	10		T96	17		T293	1
minimum	17212	1			T5	2		T6	1		T27	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21597

1

T5

2

T6

1

T27

2

auto[1]

3396

1

T13

9

T15

2

T16

26

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T106	1		T107	8		T118	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T18	5		T99	1		T116	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T33	3		T32	13		T98	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T20	1		T21	3		T111	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T13	4		T108	1		T135	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T13	7		T198	1		T197	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T88	7		T98	4		T115	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T118	3		T113	14		T197	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T14	1		T32	18		T104	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T19	6		T22	5		T32	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T85	5		T31	7		T232	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T113	1		T108	1		T213	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1254	1			T15	3		T16	29		T17	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T105	1		T109	8		T115	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T19	3		T97	1		T135	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T14	1		T109	14		T90	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T22	7		T104	1		T105	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T18	2		T22	8		T115	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T294	1		T295	3		T296	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T20	1		T96	17		T293	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16931	1			T18	98		T32	14		T28	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T118	10		T162	1		T116	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T107	5		T118	2		T114	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T18	1		T116	1		T117	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T33	5		T32	5		T98	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T20	14		T21	5		T111	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T13	2		T123	10		T203	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T13	9		T198	5		T110	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T98	13		T115	13		T122	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T118	3		T197	4		T110	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T32	20		T197	10		T207	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T19	9		T22	10		T32	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T85	10		T219	8		T297	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T113	1		T100	17		T136	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	968	1			T17	20		T19	4		T95	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T109	7		T115	6		T226	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T97	1		T162	8		T165	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T109	15		T90	13		T164	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T22	6		T104	1		T161	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T22	7		T115	2		T165	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T295	6		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T20	9		T204	4		T230	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T5	2		T6	1		T27	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T118	2		T162	2		T254	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T22	7		T212	10		T226	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T115	1		T204	11		T225	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T207	15		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T292	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T106	2		T107	8		T97	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T18	5		T118	10		T99	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T32	13		T118	11		T103	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T20	1		T21	3		T111	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T33	3		T108	1		T135	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T13	7		T198	1		T197	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	4		T88	7		T115	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T118	3		T113	14		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T14	1		T32	18		T197	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T32	8		T197	1		T110	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T85	5		T104	7		T31	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T19	6		T22	5		T89	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T106	1		T110	7		T101	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T105	1		T113	1		T109	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T19	4		T97	1		T135	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T109	14		T90	15		T164	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1357	1			T15	3		T16	29		T17	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T14	1		T18	2		T20	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16832	1			T18	98		T32	14		T28	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T22	6		T226	17		T233	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T115	2		T204	4		T225	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T207	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T107	5		T97	12		T114	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T18	1		T118	2		T162	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T32	5		T118	2		T103	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T20	14		T21	5		T111	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T33	5		T98	11		T298	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T13	9		T198	5		T110	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T13	2		T115	13		T122	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T118	3		T164	20		T251	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T32	20		T197	10		T98	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T32	7		T197	4		T110	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T85	10		T126	11		T299	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T19	9		T22	10		T89	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T110	6		T117	8		T214	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T113	1		T109	7		T115	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T19	4		T97	1		T165	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T109	15		T90	13		T164	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1047	1			T17	20		T95	20		T104	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T20	9		T22	7		T165	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T5	2		T6	1		T27	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T106	1		T107	6		T118	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T18	4		T99	1		T116	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T33	6		T32	6		T98	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T20	15		T21	6		T111	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T13	3		T108	1		T135	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T13	10		T198	6		T197	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T88	5		T98	14		T115	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T118	4		T113	2		T197	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T14	1		T32	22		T104	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T19	10		T22	11		T32	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T85	14		T31	1		T232	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T113	2		T108	1		T213	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1315	1			T15	1		T16	3		T17	23
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T105	1		T109	8		T115	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T19	1		T97	2		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T14	1		T109	16		T90	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T22	7		T104	2		T105	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T18	2		T22	8		T115	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T294	1		T295	7		T296	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T20	10		T96	1		T293	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17037	1			T5	2		T6	1		T27	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T118	3		T162	3		T116	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T107	7		T118	10		T214	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T18	2		T117	9		T124	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T33	2		T32	12		T98	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T21	2		T111	9		T210	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T13	3		T135	2		T130	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T13	6		T110	13		T122	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T88	2		T98	3		T103	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T118	2		T113	12		T110	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T32	16		T104	6		T207	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T19	5		T22	4		T32	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T85	1		T31	6		T209	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T213	4		T100	13		T136	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	907	1			T15	2		T16	26		T256	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T109	7		T137	24		T224	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T19	2		T135	4		T120	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T109	13		T90	14		T102	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T22	6		T212	9		T119	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T22	7		T165	12		T195	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T295	2		T296	14		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T96	16		T204	10		T285	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T97	9		T100	10		T210	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T118	9		T237	13		T149	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T22	7		T212	1		T226	18
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T115	3		T204	5		T225	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T207	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T292	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T106	2		T107	6		T97	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T18	4		T118	3		T99	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T32	6		T118	3		T103	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T20	15		T21	6		T111	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T33	6		T108	1		T135	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T13	10		T198	6		T197	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T13	3		T88	5		T115	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T118	4		T113	2		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T14	1		T32	22		T197	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T32	8		T197	5		T110	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T85	14		T104	1		T31	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T19	10		T22	11		T89	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T106	1		T110	7		T101	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T105	1		T113	2		T109	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T19	6		T97	2		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T109	16		T90	14		T164	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1407	1			T15	1		T16	3		T17	23
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T14	1		T18	2		T20	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16979	1			T5	2		T6	1		T27	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T22	6		T212	9		T233	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T204	10		T236	5		T146	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T207	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T107	7		T97	9		T100	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T18	2		T118	9		T117	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T32	12		T118	10		T103	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T21	2		T111	9		T210	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T33	2		T135	2		T98	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T13	6		T110	13		T122	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T13	3		T88	2		T103	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T118	2		T113	12		T251	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T32	16		T98	3		T120	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T32	7		T110	9		T100	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T85	1		T104	6		T31	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T19	5		T22	4		T89	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T110	6		T117	3		T214	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T109	7		T136	11		T137	24
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T19	2		T135	4		T120	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T109	13		T90	14		T102	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	997	1			T15	2		T16	26		T256	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T22	7		T96	16		T165	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21597

1

T5

2

T6

1

T27

2

auto[1]

auto[0]

3396

1

T13

9

T15

2

T16

26