Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24993

1

T5

2

T6

1

T27

2

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21776

1

T5

2

T6

1

T27

2

auto[ADC_CTRL_FILTER_COND_OUT]

3217

1

T13

16

T14

1

T18

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19517

1

T5

2

T6

1

T27

2

auto[1]

5476

1

T13

6

T14

1

T15

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21262

1

T13

11

T14

2

T15

3

auto[1]

3731

1

T5

2

T6

1

T27

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	734	1			T18	6		T19	18		T32	26
values[0]	47	1			T118	12		T136	2		T123	14
values[1]	680	1			T22	15		T33	8		T107	13
values[2]	2549	1			T15	3		T16	29		T17	23
values[3]	757	1			T13	16		T88	7		T135	3
values[4]	400	1			T18	2		T32	12		T106	1
values[5]	611	1			T118	13		T197	5		T98	20
values[6]	684	1			T14	1		T18	6		T19	5
values[7]	445	1			T97	2		T113	1		T31	7
values[8]	736	1			T14	1		T20	15		T32	18
values[9]	837	1			T13	6		T21	8		T22	28
minimum	16513	1			T5	2		T6	1		T27	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	587	1			T22	15		T33	8		T107	13
values[1]	2574	1			T13	16		T15	3		T16	29
values[2]	771	1			T135	3		T197	11		T115	7
values[3]	392	1			T18	2		T32	12		T106	1
values[4]	715	1			T32	15		T106	1		T118	19
values[5]	549	1			T14	1		T18	6		T19	5
values[6]	523	1			T89	6		T97	24		T31	7
values[7]	733	1			T14	1		T20	15		T32	18
values[8]	832	1			T13	6		T19	18		T21	8
values[9]	75	1			T32	26		T165	3		T241	16
minimum	17242	1			T5	2		T6	1		T27	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21597

1

T5

2

T6

1

T27

2

auto[1]

3396

1

T13

9

T15

2

T16

26

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T33	3		T107	8		T110	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T22	5		T118	10		T108	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1278	1			T15	3		T16	29		T17	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T13	7		T20	1		T105	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T115	1		T164	1		T102	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T135	3		T197	1		T122	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T32	1		T106	1		T108	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T18	2		T164	1		T125	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T106	1		T118	11		T100	25
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T32	8		T118	3		T197	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T19	1		T105	1		T213	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T14	1		T18	5		T104	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T89	5		T97	10		T127	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T97	1		T31	7		T110	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T14	1		T20	1		T114	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T32	13		T99	1		T252	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T13	4		T22	8		T109	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T19	9		T21	3		T22	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T32	17		T165	1		T300	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T241	7		T271	8		T258	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16918	1			T18	98		T32	14		T28	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T198	1		T136	1		T201	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T33	5		T107	5		T110	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T22	10		T118	2		T115	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	992	1			T17	20		T95	20		T104	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T13	9		T20	9		T113	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T115	6		T164	4		T102	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T197	10		T122	1		T245	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T32	11		T98	11		T190	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T164	7		T125	17		T275	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T118	2		T100	24		T299	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T32	7		T118	3		T197	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T19	4		T162	8		T117	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T18	1		T110	16		T226	34
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T89	1		T97	12		T119	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T97	1		T110	9		T164	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T20	14		T114	9		T161	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T32	5		T123	10		T207	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T13	2		T22	7		T109	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T19	9		T21	5		T22	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T32	9		T165	2		T300	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T241	9		T258	2		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T5	2		T6	1		T27	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T198	5		T136	1		T125	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	522	1			T18	6		T32	17		T29	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T19	9		T85	5		T113	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T123	1		T265	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T118	10		T136	1		T266	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T33	3		T107	8		T96	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T22	5		T108	1		T198	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1274	1			T15	3		T16	29		T17	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T20	1		T105	1		T113	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T102	14		T127	1		T249	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T13	7		T88	7		T135	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T32	1		T106	1		T108	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T18	2		T164	1		T255	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T118	11		T98	9		T212	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T197	1		T99	1		T159	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T19	1		T105	1		T106	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T14	1		T18	5		T32	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T127	1		T119	10		T116	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T97	1		T113	1		T31	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T14	1		T20	1		T89	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T32	13		T99	1		T252	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T13	4		T22	8		T109	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T21	3		T22	7		T115	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16366	1			T18	92		T32	14		T28	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T32	9		T136	10		T162	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T19	9		T85	10		T121	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T123	13		T265	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T118	2		T136	1		T301	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T33	5		T107	5		T90	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T22	10		T198	5		T115	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	984	1			T17	20		T95	20		T104	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T20	9		T113	1		T109	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T102	18		T249	6		T233	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T13	9		T197	10		T122	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T32	11		T115	6		T164	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T164	7		T239	5		T262	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T118	2		T98	11		T190	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T197	4		T121	14		T214	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T19	4		T100	24		T162	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T18	1		T32	7		T118	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T119	6		T140	9		T169	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T97	1		T110	9		T164	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T20	14		T89	1		T97	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T32	5		T123	10		T207	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T13	2		T22	7		T109	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T21	5		T22	6		T115	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T5	2		T6	1		T27	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T33	6		T107	6		T110	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T22	11		T118	3		T108	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1328	1			T15	1		T16	3		T17	23
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T13	10		T20	10		T105	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T115	7		T164	5		T102	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T135	1		T197	11		T122	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T32	12		T106	1		T108	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T18	2		T164	8		T125	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T106	1		T118	3		T100	26
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T32	8		T118	4		T197	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T19	5		T105	1		T213	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T14	1		T18	4		T104	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T89	5		T97	13		T127	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T97	2		T31	1		T110	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T14	1		T20	15		T114	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T32	6		T99	1		T252	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T13	3		T22	8		T109	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T19	11		T21	6		T22	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T32	10		T165	3		T300	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T241	10		T271	1		T258	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17073	1			T5	2		T6	1		T27	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T198	6		T136	2		T201	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T33	2		T107	7		T110	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T22	4		T118	9		T120	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	942	1			T15	2		T16	26		T256	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T13	6		T88	2		T109	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T102	13		T196	3		T238	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T135	2		T120	11		T209	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T98	8		T190	1		T233	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T255	12		T211	7		T238	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T118	10		T100	23		T212	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T32	7		T118	2		T214	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T213	4		T117	9		T166	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T18	2		T104	6		T110	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T89	1		T97	9		T119	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T31	6		T110	9		T207	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T103	7		T208	3		T276	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T32	12		T207	14		T126	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T13	3		T22	7		T109	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T19	7		T21	2		T22	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T32	16		T300	2		T302	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T241	6		T271	7		T258	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T96	16		T90	14		T165	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T224	11		T218	2		T303	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	534	1			T18	6		T32	10		T29	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T19	11		T85	14		T113	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T123	14		T265	14		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T118	3		T136	2		T266	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T33	6		T107	6		T96	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T22	11		T108	1		T198	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1319	1			T15	1		T16	3		T17	23
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T20	10		T105	1		T113	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T102	19		T127	1		T249	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T13	10		T88	5		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T32	12		T106	1		T108	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T18	2		T164	8		T255	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T118	3		T98	12		T212	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T197	5		T99	1		T159	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T19	5		T105	1		T106	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T14	1		T18	4		T32	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T127	1		T119	13		T116	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T97	2		T113	1		T31	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T14	1		T20	15		T89	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T32	6		T99	1		T252	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T13	3		T22	8		T109	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T21	6		T22	7		T115	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16513	1			T5	2		T6	1		T27	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T32	16		T135	4		T136	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T19	7		T85	1		T113	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T118	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T33	2		T107	7		T96	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T22	4		T120	13		T255	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	939	1			T15	2		T16	26		T256	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T109	7		T98	3		T145	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T102	13		T196	3		T168	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T13	6		T88	2		T135	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T233	2		T204	10		T257	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T255	12		T239	4		T304	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T118	10		T98	8		T212	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T214	7		T211	7		T235	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T213	4		T100	23		T117	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T18	2		T32	7		T104	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T119	3		T124	8		T169	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T31	6		T110	9		T251	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T89	1		T97	9		T103	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T32	12		T207	13		T268	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T13	3		T22	7		T109	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T21	2		T22	6		T117	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21597

1

T5

2

T6

1

T27

2

auto[1]

auto[0]

3396

1

T13

9

T15

2

T16

26