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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.66 98.98 95.70 100.00 100.00 98.18 98.64 92.14


Total test records in report: 886
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T771 /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.1319021904 Jan 07 01:06:27 PM PST 24 Jan 07 01:17:15 PM PST 24 496084841302 ps
T772 /workspace/coverage/default/24.adc_ctrl_poweron_counter.31713086 Jan 07 01:07:18 PM PST 24 Jan 07 01:07:23 PM PST 24 5146486911 ps
T313 /workspace/coverage/default/39.adc_ctrl_clock_gating.1501757816 Jan 07 01:07:38 PM PST 24 Jan 07 01:10:47 PM PST 24 330580420336 ps
T247 /workspace/coverage/default/23.adc_ctrl_filters_polled.1204599131 Jan 07 01:06:59 PM PST 24 Jan 07 01:08:37 PM PST 24 161313231551 ps
T773 /workspace/coverage/default/46.adc_ctrl_stress_all.2486880078 Jan 07 01:08:17 PM PST 24 Jan 07 01:08:21 PM PST 24 7667278304 ps
T300 /workspace/coverage/default/21.adc_ctrl_filters_both.4153934431 Jan 07 01:06:59 PM PST 24 Jan 07 01:24:39 PM PST 24 496212446829 ps
T774 /workspace/coverage/default/46.adc_ctrl_alert_test.3002100336 Jan 07 01:08:12 PM PST 24 Jan 07 01:08:16 PM PST 24 408475101 ps
T775 /workspace/coverage/default/40.adc_ctrl_fsm_reset.3258712135 Jan 07 01:07:50 PM PST 24 Jan 07 01:15:21 PM PST 24 106187015359 ps
T776 /workspace/coverage/default/4.adc_ctrl_fsm_reset.957740241 Jan 07 01:06:20 PM PST 24 Jan 07 01:15:02 PM PST 24 102865244001 ps
T777 /workspace/coverage/default/14.adc_ctrl_poweron_counter.3155613936 Jan 07 01:06:43 PM PST 24 Jan 07 01:07:01 PM PST 24 3134768279 ps
T778 /workspace/coverage/default/36.adc_ctrl_alert_test.3803757118 Jan 07 01:07:33 PM PST 24 Jan 07 01:07:38 PM PST 24 435865738 ps
T779 /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.2384816548 Jan 07 01:08:26 PM PST 24 Jan 07 01:10:29 PM PST 24 106979193042 ps
T780 /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.1179671510 Jan 07 01:08:12 PM PST 24 Jan 07 01:11:43 PM PST 24 334545294670 ps
T781 /workspace/coverage/default/12.adc_ctrl_smoke.4092836150 Jan 07 01:06:22 PM PST 24 Jan 07 01:06:31 PM PST 24 5960280926 ps
T782 /workspace/coverage/default/26.adc_ctrl_filters_polled.1681108810 Jan 07 01:07:36 PM PST 24 Jan 07 01:09:15 PM PST 24 167254425707 ps
T783 /workspace/coverage/default/19.adc_ctrl_poweron_counter.156256573 Jan 07 01:06:35 PM PST 24 Jan 07 01:06:59 PM PST 24 4936305249 ps
T784 /workspace/coverage/default/15.adc_ctrl_alert_test.199396915 Jan 07 01:06:31 PM PST 24 Jan 07 01:06:52 PM PST 24 517098066 ps
T334 /workspace/coverage/default/49.adc_ctrl_filters_wakeup.1859914075 Jan 07 01:08:25 PM PST 24 Jan 07 01:21:02 PM PST 24 328035082493 ps
T785 /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.2132741968 Jan 07 01:06:18 PM PST 24 Jan 07 01:19:02 PM PST 24 331673787442 ps
T786 /workspace/coverage/default/8.adc_ctrl_filters_both.1100985031 Jan 07 01:06:28 PM PST 24 Jan 07 01:20:03 PM PST 24 343025611226 ps
T787 /workspace/coverage/default/17.adc_ctrl_smoke.421424013 Jan 07 01:08:03 PM PST 24 Jan 07 01:08:07 PM PST 24 6000250369 ps
T788 /workspace/coverage/default/21.adc_ctrl_alert_test.3983769500 Jan 07 01:07:08 PM PST 24 Jan 07 01:07:13 PM PST 24 429518330 ps
T789 /workspace/coverage/default/31.adc_ctrl_filters_both.930375726 Jan 07 01:07:45 PM PST 24 Jan 07 01:09:35 PM PST 24 165115138484 ps
T790 /workspace/coverage/default/26.adc_ctrl_filters_wakeup.3801929444 Jan 07 01:07:21 PM PST 24 Jan 07 01:10:46 PM PST 24 344002760203 ps
T791 /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.2678171558 Jan 07 01:06:33 PM PST 24 Jan 07 01:11:42 PM PST 24 490664276593 ps
T792 /workspace/coverage/default/18.adc_ctrl_filters_wakeup.1766622164 Jan 07 01:08:00 PM PST 24 Jan 07 01:11:14 PM PST 24 329953765953 ps
T285 /workspace/coverage/default/46.adc_ctrl_filters_wakeup.1090016478 Jan 07 01:08:12 PM PST 24 Jan 07 01:12:57 PM PST 24 493534268112 ps
T793 /workspace/coverage/default/36.adc_ctrl_lowpower_counter.3153577220 Jan 07 01:07:49 PM PST 24 Jan 07 01:08:51 PM PST 24 24295882940 ps
T794 /workspace/coverage/default/40.adc_ctrl_alert_test.4116540197 Jan 07 01:07:54 PM PST 24 Jan 07 01:08:02 PM PST 24 489483884 ps
T795 /workspace/coverage/default/8.adc_ctrl_filters_polled.1115088830 Jan 07 01:06:19 PM PST 24 Jan 07 01:08:00 PM PST 24 167646354079 ps
T796 /workspace/coverage/default/37.adc_ctrl_alert_test.4106943100 Jan 07 01:07:37 PM PST 24 Jan 07 01:07:42 PM PST 24 493484360 ps
T797 /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.2029143896 Jan 07 01:07:42 PM PST 24 Jan 07 01:14:00 PM PST 24 166956815941 ps
T798 /workspace/coverage/default/1.adc_ctrl_stress_all.2065832784 Jan 07 01:05:55 PM PST 24 Jan 07 01:06:01 PM PST 24 4097990660 ps
T799 /workspace/coverage/default/29.adc_ctrl_poweron_counter.3079931672 Jan 07 01:07:22 PM PST 24 Jan 07 01:07:31 PM PST 24 3733186255 ps
T800 /workspace/coverage/default/33.adc_ctrl_smoke.3808363852 Jan 07 01:07:33 PM PST 24 Jan 07 01:07:38 PM PST 24 5828765316 ps
T801 /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.4112391119 Jan 07 01:05:47 PM PST 24 Jan 07 01:06:13 PM PST 24 19188077732 ps
T802 /workspace/coverage/default/12.adc_ctrl_alert_test.2446799278 Jan 07 01:06:43 PM PST 24 Jan 07 01:07:00 PM PST 24 485864000 ps
T803 /workspace/coverage/default/38.adc_ctrl_smoke.1117410480 Jan 07 01:07:35 PM PST 24 Jan 07 01:07:45 PM PST 24 5994249535 ps
T804 /workspace/coverage/default/6.adc_ctrl_lowpower_counter.132653772 Jan 07 01:06:19 PM PST 24 Jan 07 01:07:18 PM PST 24 46331217316 ps
T805 /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.757933386 Jan 07 01:08:11 PM PST 24 Jan 07 01:11:31 PM PST 24 163852446350 ps
T806 /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.576088117 Jan 07 01:07:09 PM PST 24 Jan 07 01:21:36 PM PST 24 496541869776 ps
T807 /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.514537488 Jan 07 01:06:24 PM PST 24 Jan 07 01:11:20 PM PST 24 491525119520 ps
T808 /workspace/coverage/default/25.adc_ctrl_alert_test.2921208431 Jan 07 01:07:32 PM PST 24 Jan 07 01:07:34 PM PST 24 453037464 ps
T809 /workspace/coverage/default/9.adc_ctrl_stress_all.202503727 Jan 07 01:06:32 PM PST 24 Jan 07 01:13:13 PM PST 24 113816231404 ps
T332 /workspace/coverage/default/16.adc_ctrl_filters_both.3169150506 Jan 07 01:06:29 PM PST 24 Jan 07 01:20:13 PM PST 24 323054211945 ps
T810 /workspace/coverage/default/44.adc_ctrl_filters_polled.4002204360 Jan 07 01:08:10 PM PST 24 Jan 07 01:21:40 PM PST 24 325219000516 ps
T811 /workspace/coverage/default/46.adc_ctrl_filters_interrupt.2944701567 Jan 07 01:08:10 PM PST 24 Jan 07 01:10:26 PM PST 24 326209774019 ps
T812 /workspace/coverage/default/32.adc_ctrl_filters_wakeup.1569859199 Jan 07 01:07:32 PM PST 24 Jan 07 01:10:45 PM PST 24 328031250503 ps
T813 /workspace/coverage/default/39.adc_ctrl_poweron_counter.1572095076 Jan 07 01:07:36 PM PST 24 Jan 07 01:07:41 PM PST 24 3344246761 ps
T814 /workspace/coverage/default/15.adc_ctrl_lowpower_counter.1511634718 Jan 07 01:08:02 PM PST 24 Jan 07 01:08:27 PM PST 24 28972388795 ps
T815 /workspace/coverage/default/27.adc_ctrl_filters_interrupt.2732520362 Jan 07 01:07:16 PM PST 24 Jan 07 01:20:26 PM PST 24 326052483318 ps
T816 /workspace/coverage/default/26.adc_ctrl_smoke.1713225461 Jan 07 01:07:35 PM PST 24 Jan 07 01:07:51 PM PST 24 5709748450 ps
T817 /workspace/coverage/default/31.adc_ctrl_poweron_counter.2495975136 Jan 07 01:07:38 PM PST 24 Jan 07 01:07:45 PM PST 24 4448160641 ps
T818 /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.2722216408 Jan 07 01:06:38 PM PST 24 Jan 07 01:11:35 PM PST 24 489062636244 ps
T819 /workspace/coverage/default/24.adc_ctrl_filters_interrupt.2102506110 Jan 07 01:07:02 PM PST 24 Jan 07 01:10:29 PM PST 24 164394594103 ps
T42 /workspace/coverage/default/0.adc_ctrl_sec_cm.1567879798 Jan 07 01:06:23 PM PST 24 Jan 07 01:06:42 PM PST 24 7973386374 ps
T820 /workspace/coverage/default/22.adc_ctrl_filters_both.307190137 Jan 07 01:07:10 PM PST 24 Jan 07 01:14:41 PM PST 24 327421446850 ps
T821 /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.3603207466 Jan 07 01:06:26 PM PST 24 Jan 07 01:09:14 PM PST 24 162966664283 ps
T320 /workspace/coverage/default/29.adc_ctrl_filters_polled.371451415 Jan 07 01:07:17 PM PST 24 Jan 07 01:10:41 PM PST 24 327934685326 ps
T822 /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.1549605776 Jan 07 01:06:34 PM PST 24 Jan 07 01:08:26 PM PST 24 159285237288 ps
T328 /workspace/coverage/default/35.adc_ctrl_filters_wakeup.1372637249 Jan 07 01:07:48 PM PST 24 Jan 07 01:11:17 PM PST 24 328698913562 ps
T823 /workspace/coverage/default/30.adc_ctrl_lowpower_counter.1807025630 Jan 07 01:07:36 PM PST 24 Jan 07 01:08:01 PM PST 24 32350364637 ps
T824 /workspace/coverage/default/10.adc_ctrl_alert_test.1629601965 Jan 07 01:06:23 PM PST 24 Jan 07 01:06:25 PM PST 24 538045411 ps
T825 /workspace/coverage/default/33.adc_ctrl_fsm_reset.2154267863 Jan 07 01:07:28 PM PST 24 Jan 07 01:14:37 PM PST 24 82081373877 ps
T826 /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.2126558590 Jan 07 01:08:17 PM PST 24 Jan 07 01:15:02 PM PST 24 167301027924 ps
T827 /workspace/coverage/default/27.adc_ctrl_lowpower_counter.3881298761 Jan 07 01:07:23 PM PST 24 Jan 07 01:08:08 PM PST 24 36105696492 ps
T230 /workspace/coverage/default/41.adc_ctrl_filters_both.692785748 Jan 07 01:07:53 PM PST 24 Jan 07 01:10:50 PM PST 24 320771759857 ps
T828 /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.464010834 Jan 07 01:06:07 PM PST 24 Jan 07 01:07:13 PM PST 24 167846578532 ps
T829 /workspace/coverage/default/17.adc_ctrl_lowpower_counter.1175137415 Jan 07 01:06:46 PM PST 24 Jan 07 01:07:12 PM PST 24 33114773395 ps
T830 /workspace/coverage/default/33.adc_ctrl_lowpower_counter.2425187823 Jan 07 01:07:30 PM PST 24 Jan 07 01:08:43 PM PST 24 28936793641 ps
T831 /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.2530174062 Jan 07 01:07:21 PM PST 24 Jan 07 01:07:42 PM PST 24 34582310790 ps
T832 /workspace/coverage/default/37.adc_ctrl_smoke.3376916583 Jan 07 01:07:21 PM PST 24 Jan 07 01:07:30 PM PST 24 6139654229 ps
T833 /workspace/coverage/default/5.adc_ctrl_filters_interrupt.1729168330 Jan 07 01:05:54 PM PST 24 Jan 07 01:07:38 PM PST 24 162376398169 ps
T329 /workspace/coverage/default/27.adc_ctrl_filters_both.848886932 Jan 07 01:07:15 PM PST 24 Jan 07 01:11:24 PM PST 24 488981168109 ps
T834 /workspace/coverage/default/7.adc_ctrl_filters_both.1381461968 Jan 07 01:06:05 PM PST 24 Jan 07 01:12:33 PM PST 24 165914824594 ps
T835 /workspace/coverage/default/42.adc_ctrl_filters_polled.3887260755 Jan 07 01:07:53 PM PST 24 Jan 07 01:25:11 PM PST 24 491094836126 ps
T836 /workspace/coverage/default/35.adc_ctrl_filters_polled.563900161 Jan 07 01:07:44 PM PST 24 Jan 07 01:14:05 PM PST 24 166042894925 ps
T43 /workspace/coverage/default/1.adc_ctrl_sec_cm.3862959235 Jan 07 01:05:59 PM PST 24 Jan 07 01:06:07 PM PST 24 7707961629 ps
T837 /workspace/coverage/default/15.adc_ctrl_poweron_counter.3037608454 Jan 07 01:06:33 PM PST 24 Jan 07 01:06:53 PM PST 24 3528672306 ps
T838 /workspace/coverage/default/46.adc_ctrl_filters_polled.3839300130 Jan 07 01:08:14 PM PST 24 Jan 07 01:14:44 PM PST 24 336892287138 ps
T839 /workspace/coverage/default/11.adc_ctrl_smoke.2983451038 Jan 07 01:06:24 PM PST 24 Jan 07 01:06:39 PM PST 24 5743290113 ps
T335 /workspace/coverage/default/17.adc_ctrl_filters_both.3212999815 Jan 07 01:06:33 PM PST 24 Jan 07 01:16:03 PM PST 24 322066560643 ps
T302 /workspace/coverage/default/38.adc_ctrl_clock_gating.3335663002 Jan 07 01:07:38 PM PST 24 Jan 07 01:20:11 PM PST 24 336711499291 ps
T840 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.1340685450 Jan 07 12:38:11 PM PST 24 Jan 07 12:39:25 PM PST 24 433140642 ps
T841 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1288179024 Jan 07 12:38:24 PM PST 24 Jan 07 12:40:23 PM PST 24 420859784 ps
T842 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3308014996 Jan 07 12:38:30 PM PST 24 Jan 07 12:40:53 PM PST 24 25919990430 ps
T843 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.716551274 Jan 07 12:37:52 PM PST 24 Jan 07 12:39:08 PM PST 24 353175755 ps
T844 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3383122588 Jan 07 12:38:15 PM PST 24 Jan 07 12:39:48 PM PST 24 526475982 ps
T845 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3034648741 Jan 07 12:38:37 PM PST 24 Jan 07 12:40:22 PM PST 24 4582198081 ps
T846 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1440564591 Jan 07 12:37:54 PM PST 24 Jan 07 12:39:40 PM PST 24 403429308 ps
T847 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.682173056 Jan 07 12:38:22 PM PST 24 Jan 07 12:39:25 PM PST 24 476970773 ps
T848 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.819433963 Jan 07 12:38:18 PM PST 24 Jan 07 12:39:58 PM PST 24 453749815 ps
T849 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3852449477 Jan 07 12:38:46 PM PST 24 Jan 07 12:39:59 PM PST 24 332673652 ps
T79 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.1751431890 Jan 07 12:38:17 PM PST 24 Jan 07 12:40:40 PM PST 24 50420344572 ps
T850 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2592153646 Jan 07 12:37:52 PM PST 24 Jan 07 12:39:20 PM PST 24 4831497269 ps
T851 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.3262054924 Jan 07 12:38:16 PM PST 24 Jan 07 12:39:37 PM PST 24 366032034 ps
T80 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.3344131293 Jan 07 12:37:38 PM PST 24 Jan 07 12:39:12 PM PST 24 568499867 ps
T852 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.175715266 Jan 07 12:38:43 PM PST 24 Jan 07 12:40:18 PM PST 24 4084341264 ps
T853 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1863188991 Jan 07 12:37:56 PM PST 24 Jan 07 12:39:12 PM PST 24 468233254 ps
T854 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.406680408 Jan 07 12:38:21 PM PST 24 Jan 07 12:40:33 PM PST 24 316758847 ps
T855 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.227439069 Jan 07 12:38:20 PM PST 24 Jan 07 12:39:30 PM PST 24 300117676 ps
T81 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.447085257 Jan 07 12:38:37 PM PST 24 Jan 07 12:40:13 PM PST 24 451840069 ps
T856 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2614497682 Jan 07 12:38:50 PM PST 24 Jan 07 12:40:23 PM PST 24 379213872 ps
T87 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2916494187 Jan 07 12:38:23 PM PST 24 Jan 07 12:39:30 PM PST 24 498242594 ps
T857 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.4243330402 Jan 07 12:37:50 PM PST 24 Jan 07 12:39:07 PM PST 24 440707260 ps
T858 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3974470260 Jan 07 12:37:54 PM PST 24 Jan 07 12:39:29 PM PST 24 8486340000 ps
T859 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.913013645 Jan 07 12:38:07 PM PST 24 Jan 07 12:39:09 PM PST 24 395044550 ps
T860 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3479376026 Jan 07 12:38:32 PM PST 24 Jan 07 12:39:37 PM PST 24 4266725531 ps
T861 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.4090687180 Jan 07 12:37:51 PM PST 24 Jan 07 12:39:14 PM PST 24 520910697 ps
T862 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.4202239514 Jan 07 12:38:09 PM PST 24 Jan 07 12:39:17 PM PST 24 1199275511 ps
T863 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3506553000 Jan 07 12:38:07 PM PST 24 Jan 07 12:39:21 PM PST 24 462726055 ps
T864 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2755038784 Jan 07 12:38:03 PM PST 24 Jan 07 12:39:13 PM PST 24 333144486 ps
T865 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.1512608279 Jan 07 12:38:28 PM PST 24 Jan 07 12:39:31 PM PST 24 482913343 ps
T866 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.2451460226 Jan 07 12:37:59 PM PST 24 Jan 07 12:39:41 PM PST 24 399642783 ps
T867 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3356036125 Jan 07 12:37:58 PM PST 24 Jan 07 12:39:03 PM PST 24 4528698419 ps
T868 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.238265797 Jan 07 12:38:04 PM PST 24 Jan 07 12:39:15 PM PST 24 2476896259 ps
T337 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1723113316 Jan 07 12:38:25 PM PST 24 Jan 07 12:40:01 PM PST 24 8332080828 ps
T869 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.4274702859 Jan 07 12:38:42 PM PST 24 Jan 07 12:40:28 PM PST 24 993047716 ps
T870 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.813252302 Jan 07 12:38:37 PM PST 24 Jan 07 12:40:10 PM PST 24 501215675 ps
T871 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.976256005 Jan 07 12:38:04 PM PST 24 Jan 07 12:39:21 PM PST 24 509656372 ps
T872 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3653426353 Jan 07 12:38:06 PM PST 24 Jan 07 12:39:32 PM PST 24 4633866841 ps
T873 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1563612415 Jan 07 12:38:15 PM PST 24 Jan 07 12:39:49 PM PST 24 525740875 ps
T874 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.208142534 Jan 07 12:38:41 PM PST 24 Jan 07 12:40:00 PM PST 24 531462353 ps
T875 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.500631088 Jan 07 12:38:28 PM PST 24 Jan 07 12:39:56 PM PST 24 651708827 ps
T876 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.371299301 Jan 07 12:38:19 PM PST 24 Jan 07 12:39:24 PM PST 24 505128920 ps
T877 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2195659059 Jan 07 12:38:27 PM PST 24 Jan 07 12:39:36 PM PST 24 411593960 ps
T878 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.4237959169 Jan 07 12:38:12 PM PST 24 Jan 07 12:40:13 PM PST 24 3536150822 ps
T82 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.584325601 Jan 07 12:37:51 PM PST 24 Jan 07 12:39:06 PM PST 24 403336020 ps
T879 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.1477140930 Jan 07 12:38:27 PM PST 24 Jan 07 12:39:40 PM PST 24 474162464 ps
T880 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2132539694 Jan 07 12:38:39 PM PST 24 Jan 07 12:40:29 PM PST 24 454521837 ps
T881 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1097498825 Jan 07 12:38:02 PM PST 24 Jan 07 12:39:34 PM PST 24 608788153 ps
T882 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.621623818 Jan 07 12:38:56 PM PST 24 Jan 07 12:40:29 PM PST 24 398965866 ps
T883 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3470773725 Jan 07 12:38:25 PM PST 24 Jan 07 12:39:38 PM PST 24 429735334 ps
T884 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2229416629 Jan 07 12:38:05 PM PST 24 Jan 07 12:39:13 PM PST 24 429483882 ps
T885 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2027266233 Jan 07 12:38:32 PM PST 24 Jan 07 12:39:44 PM PST 24 4543437133 ps
T886 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.1383058482 Jan 07 12:38:23 PM PST 24 Jan 07 12:39:26 PM PST 24 472138426 ps

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3980121677
Short name T10
Test name
Test status
Simulation time 7661793596 ps
CPU time 14.94 seconds
Started Jan 07 12:37:49 PM PST 24
Finished Jan 07 12:39:26 PM PST 24
Peak memory 200752 kb
Host smart-98b7f1f2-f4c7-41be-a783-6f5c8f856686
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980121677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.3980121677
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3801805457
Short name T5
Test name
Test status
Simulation time 432325346 ps
CPU time 1.1 seconds
Started Jan 07 12:38:10 PM PST 24
Finished Jan 07 12:39:54 PM PST 24
Peak memory 200152 kb
Host smart-93571995-4622-42b9-a540-89d715712649
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801805457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.3801805457
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.521006997
Short name T22
Test name
Test status
Simulation time 495524260753 ps
CPU time 261.56 seconds
Started Jan 07 01:07:34 PM PST 24
Finished Jan 07 01:11:58 PM PST 24
Peak memory 200888 kb
Host smart-5e2b430a-7d5e-4bfd-b874-7602bdb938bd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521006997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gati
ng.521006997
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.1105510257
Short name T32
Test name
Test status
Simulation time 693285412083 ps
CPU time 1658.65 seconds
Started Jan 07 01:07:39 PM PST 24
Finished Jan 07 01:35:21 PM PST 24
Peak memory 200932 kb
Host smart-caa3f6db-103c-4657-852e-bd7def712d1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105510257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.1105510257
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.45380571
Short name T18
Test name
Test status
Simulation time 201465957553 ps
CPU time 241.36 seconds
Started Jan 07 01:07:39 PM PST 24
Finished Jan 07 01:11:43 PM PST 24
Peak memory 209676 kb
Host smart-b66ce589-9a83-4be3-9f94-5f61cdbe5b53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45380571 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.45380571
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.339567059
Short name T110
Test name
Test status
Simulation time 498579101155 ps
CPU time 190.7 seconds
Started Jan 07 01:07:12 PM PST 24
Finished Jan 07 01:10:25 PM PST 24
Peak memory 200808 kb
Host smart-a70c2cdc-de0b-4daa-a65c-645bdda82cca
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339567059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gati
ng.339567059
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2185505455
Short name T7
Test name
Test status
Simulation time 2195945393 ps
CPU time 2.98 seconds
Started Jan 07 12:38:02 PM PST 24
Finished Jan 07 12:39:22 PM PST 24
Peak memory 200532 kb
Host smart-6362b69b-276a-4db6-b428-c2a5b75e6df9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185505455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.2185505455
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.1707446647
Short name T19
Test name
Test status
Simulation time 521174891632 ps
CPU time 312.11 seconds
Started Jan 07 01:06:56 PM PST 24
Finished Jan 07 01:12:18 PM PST 24
Peak memory 200936 kb
Host smart-1f334239-28e8-4999-a9a5-9db1c8fe44df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707446647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.1707446647
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.1461497327
Short name T100
Test name
Test status
Simulation time 495413178000 ps
CPU time 1200.96 seconds
Started Jan 07 01:06:23 PM PST 24
Finished Jan 07 01:26:25 PM PST 24
Peak memory 200940 kb
Host smart-f5efe45d-c826-4453-bde7-d39a55ead0ee
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461497327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.1461497327
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.948899407
Short name T204
Test name
Test status
Simulation time 489212384777 ps
CPU time 377.15 seconds
Started Jan 07 01:07:26 PM PST 24
Finished Jan 07 01:13:45 PM PST 24
Peak memory 200964 kb
Host smart-05d8a8d3-ec96-4e5e-ab77-1f85d86a6eea
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948899407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gati
ng.948899407
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.1536386370
Short name T109
Test name
Test status
Simulation time 331855342607 ps
CPU time 132.73 seconds
Started Jan 07 01:08:10 PM PST 24
Finished Jan 07 01:10:25 PM PST 24
Peak memory 200936 kb
Host smart-2dcbd7ba-d0c6-4cb5-b441-8daf2aab54b9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536386370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.1536386370
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.3416943836
Short name T233
Test name
Test status
Simulation time 327927153787 ps
CPU time 401.68 seconds
Started Jan 07 01:07:00 PM PST 24
Finished Jan 07 01:13:50 PM PST 24
Peak memory 200916 kb
Host smart-e940c09e-c57c-4409-b306-b63ec119bf7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416943836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.3416943836
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.711946446
Short name T208
Test name
Test status
Simulation time 439490029558 ps
CPU time 724.63 seconds
Started Jan 07 01:08:10 PM PST 24
Finished Jan 07 01:20:17 PM PST 24
Peak memory 209572 kb
Host smart-0c05c835-d7cb-4899-a295-e78e15b37eaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711946446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all.
711946446
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1950034162
Short name T52
Test name
Test status
Simulation time 411922627 ps
CPU time 3.23 seconds
Started Jan 07 12:38:19 PM PST 24
Finished Jan 07 12:39:28 PM PST 24
Peak memory 200760 kb
Host smart-3480ad8f-e321-4600-90d3-5911337c24b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950034162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.1950034162
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.1035740389
Short name T118
Test name
Test status
Simulation time 527062408180 ps
CPU time 557.32 seconds
Started Jan 07 01:08:27 PM PST 24
Finished Jan 07 01:17:46 PM PST 24
Peak memory 200928 kb
Host smart-c9e19e8f-cf45-4eba-b3f4-35d4b1b594ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035740389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.1035740389
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.2244918771
Short name T88
Test name
Test status
Simulation time 284655240053 ps
CPU time 112.82 seconds
Started Jan 07 01:06:40 PM PST 24
Finished Jan 07 01:08:47 PM PST 24
Peak memory 210452 kb
Host smart-e7281ed0-8356-4af6-aec6-9af9c11df97c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244918771 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.2244918771
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.1101914463
Short name T140
Test name
Test status
Simulation time 485573030073 ps
CPU time 301.24 seconds
Started Jan 07 01:06:28 PM PST 24
Finished Jan 07 01:11:42 PM PST 24
Peak memory 200928 kb
Host smart-3c740870-4880-4f6c-a716-1794ac18a50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101914463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.1101914463
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.3035865841
Short name T104
Test name
Test status
Simulation time 327933326475 ps
CPU time 364.82 seconds
Started Jan 07 01:07:31 PM PST 24
Finished Jan 07 01:13:38 PM PST 24
Peak memory 200788 kb
Host smart-20fa7c2e-bf27-4143-a260-a3b261cc1ebb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035865841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.3035865841
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.3245185034
Short name T239
Test name
Test status
Simulation time 280136185203 ps
CPU time 65.66 seconds
Started Jan 07 01:07:49 PM PST 24
Finished Jan 07 01:09:03 PM PST 24
Peak memory 209708 kb
Host smart-fd904687-8d76-4a7c-bf36-7ec9ae001385
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245185034 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.3245185034
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.3368059470
Short name T210
Test name
Test status
Simulation time 326708535009 ps
CPU time 388.69 seconds
Started Jan 07 01:07:36 PM PST 24
Finished Jan 07 01:14:08 PM PST 24
Peak memory 200932 kb
Host smart-61cc5232-b1cc-484d-8459-7edcaf36a809
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368059470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.3368059470
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.3264535196
Short name T103
Test name
Test status
Simulation time 322488495650 ps
CPU time 220.79 seconds
Started Jan 07 01:08:10 PM PST 24
Finished Jan 07 01:11:53 PM PST 24
Peak memory 209508 kb
Host smart-b3d95bdd-d188-4e26-b2d7-3fb99ac2bc6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264535196 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.3264535196
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.1713016711
Short name T66
Test name
Test status
Simulation time 622177828 ps
CPU time 2.03 seconds
Started Jan 07 12:38:26 PM PST 24
Finished Jan 07 12:39:42 PM PST 24
Peak memory 200508 kb
Host smart-0bc4780b-3f5d-41fc-b8ab-0975f8127d39
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713016711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.1713016711
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.336822452
Short name T241
Test name
Test status
Simulation time 494234399376 ps
CPU time 1121.34 seconds
Started Jan 07 01:06:11 PM PST 24
Finished Jan 07 01:24:54 PM PST 24
Peak memory 200876 kb
Host smart-b6e45c70-f994-4d7f-b7af-36f132bc90a4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336822452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gatin
g.336822452
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.2005585790
Short name T120
Test name
Test status
Simulation time 329894408354 ps
CPU time 112.4 seconds
Started Jan 07 01:06:25 PM PST 24
Finished Jan 07 01:08:20 PM PST 24
Peak memory 200852 kb
Host smart-6e07e809-e648-4325-8a12-5cbf5eeda2c4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005585790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.2005585790
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.3207500586
Short name T39
Test name
Test status
Simulation time 8823548116 ps
CPU time 3.81 seconds
Started Jan 07 01:06:15 PM PST 24
Finished Jan 07 01:06:20 PM PST 24
Peak memory 216144 kb
Host smart-5a795329-2782-41d8-9fdb-27c40d250d7d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207500586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.3207500586
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.4266869454
Short name T136
Test name
Test status
Simulation time 503373395608 ps
CPU time 783.18 seconds
Started Jan 07 01:08:11 PM PST 24
Finished Jan 07 01:21:17 PM PST 24
Peak memory 200956 kb
Host smart-459e0b17-1ce2-4711-90b6-47d3518c8da3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266869454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.4266869454
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.887741687
Short name T16
Test name
Test status
Simulation time 492326305584 ps
CPU time 305.19 seconds
Started Jan 07 01:07:28 PM PST 24
Finished Jan 07 01:12:35 PM PST 24
Peak memory 200908 kb
Host smart-1d326da8-16e7-4c53-bba2-84039090e632
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887741687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
adc_ctrl_filters_wakeup_fixed.887741687
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.2967805281
Short name T123
Test name
Test status
Simulation time 492337668100 ps
CPU time 117.76 seconds
Started Jan 07 01:07:43 PM PST 24
Finished Jan 07 01:09:44 PM PST 24
Peak memory 200900 kb
Host smart-41288865-d4f9-497b-952c-93455a682f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967805281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.2967805281
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.3003039741
Short name T288
Test name
Test status
Simulation time 338783654064 ps
CPU time 731.62 seconds
Started Jan 07 01:07:23 PM PST 24
Finished Jan 07 01:19:38 PM PST 24
Peak memory 200956 kb
Host smart-72c35724-25bc-41f8-8b88-4d909db55b31
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003039741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.3003039741
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.3029336785
Short name T295
Test name
Test status
Simulation time 492343256749 ps
CPU time 432.76 seconds
Started Jan 07 01:06:39 PM PST 24
Finished Jan 07 01:14:06 PM PST 24
Peak memory 200652 kb
Host smart-f0fbe9a6-ea04-40f6-8d16-6eba555528f0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029336785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.3029336785
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.3210128336
Short name T221
Test name
Test status
Simulation time 332049582024 ps
CPU time 213.74 seconds
Started Jan 07 01:06:12 PM PST 24
Finished Jan 07 01:09:47 PM PST 24
Peak memory 200948 kb
Host smart-11fe42db-f362-472d-a5a2-f3eae4f1a01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210128336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.3210128336
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.2410591018
Short name T125
Test name
Test status
Simulation time 487502483877 ps
CPU time 338.26 seconds
Started Jan 07 01:06:19 PM PST 24
Finished Jan 07 01:11:58 PM PST 24
Peak memory 200964 kb
Host smart-2e8b9185-007b-4147-bf87-227486c372f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410591018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.2410591018
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.2958113687
Short name T31
Test name
Test status
Simulation time 348594138300 ps
CPU time 561.2 seconds
Started Jan 07 01:08:02 PM PST 24
Finished Jan 07 01:17:25 PM PST 24
Peak memory 209048 kb
Host smart-0a6ab56f-752e-485a-91b4-b13bc5ac739d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958113687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.2958113687
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.1663478519
Short name T137
Test name
Test status
Simulation time 505283200588 ps
CPU time 186.25 seconds
Started Jan 07 01:05:56 PM PST 24
Finished Jan 07 01:09:06 PM PST 24
Peak memory 200940 kb
Host smart-0e3adb8b-684c-46b7-a46a-9690c003f118
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663478519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.1663478519
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.1658122324
Short name T277
Test name
Test status
Simulation time 164615649349 ps
CPU time 378.81 seconds
Started Jan 07 01:07:50 PM PST 24
Finished Jan 07 01:14:16 PM PST 24
Peak memory 200868 kb
Host smart-6bba8114-cbb0-44b1-a1c3-e9f5fe25de57
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658122324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.1658122324
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.299516802
Short name T263
Test name
Test status
Simulation time 91990313376 ps
CPU time 211.36 seconds
Started Jan 07 01:06:27 PM PST 24
Finished Jan 07 01:10:02 PM PST 24
Peak memory 209176 kb
Host smart-9d8dd64a-ce1b-4527-965d-e55fbbf45d4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299516802 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.299516802
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.1083934895
Short name T117
Test name
Test status
Simulation time 325771550856 ps
CPU time 425.64 seconds
Started Jan 07 01:07:38 PM PST 24
Finished Jan 07 01:14:47 PM PST 24
Peak memory 200876 kb
Host smart-e67d251b-afcc-4ec8-8203-55eaa91551fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083934895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.1083934895
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.17540786
Short name T124
Test name
Test status
Simulation time 492286729019 ps
CPU time 113.71 seconds
Started Jan 07 01:08:17 PM PST 24
Finished Jan 07 01:10:13 PM PST 24
Peak memory 200804 kb
Host smart-ce3f7bae-5c1b-4006-b216-032286b3d2d2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17540786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gatin
g.17540786
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.986197334
Short name T195
Test name
Test status
Simulation time 78907274078 ps
CPU time 80.85 seconds
Started Jan 07 01:07:51 PM PST 24
Finished Jan 07 01:09:18 PM PST 24
Peak memory 200908 kb
Host smart-44521317-a22f-4f0c-ab8e-4a149d7aeadc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986197334 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.986197334
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.3100161156
Short name T194
Test name
Test status
Simulation time 497508762914 ps
CPU time 299.92 seconds
Started Jan 07 01:06:17 PM PST 24
Finished Jan 07 01:11:18 PM PST 24
Peak memory 200888 kb
Host smart-dc9cbad0-d282-4996-9705-c086b2096e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100161156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.3100161156
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.841774990
Short name T325
Test name
Test status
Simulation time 332389529286 ps
CPU time 188.51 seconds
Started Jan 07 01:06:32 PM PST 24
Finished Jan 07 01:09:59 PM PST 24
Peak memory 200876 kb
Host smart-4e25e628-8cc4-4536-b072-e56478e6650b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841774990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gati
ng.841774990
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.2036541049
Short name T258
Test name
Test status
Simulation time 494567535265 ps
CPU time 762.76 seconds
Started Jan 07 01:07:39 PM PST 24
Finished Jan 07 01:20:25 PM PST 24
Peak memory 200844 kb
Host smart-bd0cbee3-77ed-4d50-97a2-67090a3df7b5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036541049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.2036541049
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.4180653132
Short name T324
Test name
Test status
Simulation time 90736219703 ps
CPU time 154.67 seconds
Started Jan 07 01:07:53 PM PST 24
Finished Jan 07 01:10:34 PM PST 24
Peak memory 209648 kb
Host smart-7fba7158-0f9d-411d-b056-c95e11a02020
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180653132 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.4180653132
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.2371476774
Short name T318
Test name
Test status
Simulation time 341551601784 ps
CPU time 193.63 seconds
Started Jan 07 01:06:23 PM PST 24
Finished Jan 07 01:09:38 PM PST 24
Peak memory 200788 kb
Host smart-c63073e1-0abd-44b3-854b-03e3fb25d82f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371476774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
2371476774
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.237323355
Short name T126
Test name
Test status
Simulation time 322996025980 ps
CPU time 409.66 seconds
Started Jan 07 01:06:40 PM PST 24
Finished Jan 07 01:13:43 PM PST 24
Peak memory 200988 kb
Host smart-9a403bf8-341b-4c69-b7e9-fda50bc17503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237323355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.237323355
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.2875374625
Short name T188
Test name
Test status
Simulation time 573474279069 ps
CPU time 747.39 seconds
Started Jan 07 01:06:56 PM PST 24
Finished Jan 07 01:19:34 PM PST 24
Peak memory 209652 kb
Host smart-d6476621-e06a-4de9-bcfe-f58133137ed8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875374625 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.2875374625
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.1139527058
Short name T201
Test name
Test status
Simulation time 275340270034 ps
CPU time 290.8 seconds
Started Jan 07 01:07:34 PM PST 24
Finished Jan 07 01:12:29 PM PST 24
Peak memory 209540 kb
Host smart-7dffeb4a-c327-4d48-8f63-0203096d79c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139527058 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.1139527058
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.1680644821
Short name T131
Test name
Test status
Simulation time 496859803617 ps
CPU time 293.87 seconds
Started Jan 07 01:06:26 PM PST 24
Finished Jan 07 01:11:24 PM PST 24
Peak memory 200800 kb
Host smart-205e9807-eb7e-4ebe-8318-0e3a6782b817
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680644821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.1680644821
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.3898011203
Short name T154
Test name
Test status
Simulation time 488694364938 ps
CPU time 299.12 seconds
Started Jan 07 01:08:13 PM PST 24
Finished Jan 07 01:13:16 PM PST 24
Peak memory 200944 kb
Host smart-70773a21-70a9-4535-af35-57b11452476d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898011203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.3898011203
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3255618663
Short name T4
Test name
Test status
Simulation time 26690577711 ps
CPU time 7.72 seconds
Started Jan 07 12:38:20 PM PST 24
Finished Jan 07 12:39:52 PM PST 24
Peak memory 200732 kb
Host smart-4659d5cd-fd33-4c1f-90f5-4d8c5df1957c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255618663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.3255618663
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.483412519
Short name T306
Test name
Test status
Simulation time 495489033558 ps
CPU time 616.61 seconds
Started Jan 07 01:06:14 PM PST 24
Finished Jan 07 01:16:32 PM PST 24
Peak memory 200896 kb
Host smart-ee869250-f8a9-42fc-89b4-f2f5a8206446
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483412519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_
wakeup.483412519
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.1344366645
Short name T157
Test name
Test status
Simulation time 334573139154 ps
CPU time 190.65 seconds
Started Jan 07 01:06:33 PM PST 24
Finished Jan 07 01:10:01 PM PST 24
Peak memory 200968 kb
Host smart-df0f1d7d-1506-4e4a-bc58-a8c408728cd6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344366645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.1344366645
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.1908009659
Short name T317
Test name
Test status
Simulation time 691797149412 ps
CPU time 423.25 seconds
Started Jan 07 01:07:01 PM PST 24
Finished Jan 07 01:14:12 PM PST 24
Peak memory 209536 kb
Host smart-d62cc270-6f6c-43e1-b9cc-b7330302a6e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908009659 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.1908009659
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.1585367296
Short name T207
Test name
Test status
Simulation time 333173742096 ps
CPU time 109.46 seconds
Started Jan 07 01:07:37 PM PST 24
Finished Jan 07 01:09:30 PM PST 24
Peak memory 200800 kb
Host smart-f4f1570e-3a71-419b-b91b-c597bac6ad4c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585367296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.1585367296
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3144517592
Short name T86
Test name
Test status
Simulation time 534509886 ps
CPU time 3.01 seconds
Started Jan 07 12:38:32 PM PST 24
Finished Jan 07 12:39:49 PM PST 24
Peak memory 216864 kb
Host smart-bdf79ab6-3c26-422b-9d21-10e4f365e409
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144517592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.3144517592
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2184336140
Short name T174
Test name
Test status
Simulation time 396939391 ps
CPU time 0.85 seconds
Started Jan 07 12:37:51 PM PST 24
Finished Jan 07 12:38:56 PM PST 24
Peak memory 200144 kb
Host smart-6570f5c9-6285-4e3f-9685-554897e81243
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184336140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.2184336140
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.3468268069
Short name T190
Test name
Test status
Simulation time 122841887621 ps
CPU time 409.28 seconds
Started Jan 07 01:07:01 PM PST 24
Finished Jan 07 01:13:58 PM PST 24
Peak memory 209576 kb
Host smart-be7a4a06-7703-4a11-be3e-bc0002df65d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468268069 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.3468268069
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.848886932
Short name T329
Test name
Test status
Simulation time 488981168109 ps
CPU time 247.34 seconds
Started Jan 07 01:07:15 PM PST 24
Finished Jan 07 01:11:24 PM PST 24
Peak memory 200968 kb
Host smart-0f14e8f0-8b7c-4da2-8dc5-005deea565be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848886932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.848886932
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.1069498180
Short name T262
Test name
Test status
Simulation time 325560832782 ps
CPU time 56.84 seconds
Started Jan 07 01:07:47 PM PST 24
Finished Jan 07 01:08:54 PM PST 24
Peak memory 200812 kb
Host smart-394e2fa4-1dd5-477b-bff7-80a5c16b36d7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069498180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.1069498180
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.96532299
Short name T322
Test name
Test status
Simulation time 330831813504 ps
CPU time 363.46 seconds
Started Jan 07 01:06:31 PM PST 24
Finished Jan 07 01:12:54 PM PST 24
Peak memory 201020 kb
Host smart-1e8266b9-f743-4f2d-8032-469ce39d4e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96532299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.96532299
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.8602083
Short name T236
Test name
Test status
Simulation time 322681969723 ps
CPU time 199.17 seconds
Started Jan 07 01:07:35 PM PST 24
Finished Jan 07 01:10:58 PM PST 24
Peak memory 200828 kb
Host smart-15313db1-3400-49b8-aa29-99a030f66dda
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8602083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gat
ing_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gating.8602083
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.1825611518
Short name T284
Test name
Test status
Simulation time 494640338569 ps
CPU time 1182.09 seconds
Started Jan 07 01:07:34 PM PST 24
Finished Jan 07 01:27:19 PM PST 24
Peak memory 200968 kb
Host smart-aa2af85e-ad56-490a-8ea0-f5c3a5a91dd1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825611518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.1825611518
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.2393753435
Short name T327
Test name
Test status
Simulation time 496686166032 ps
CPU time 1236.75 seconds
Started Jan 07 01:08:23 PM PST 24
Finished Jan 07 01:29:01 PM PST 24
Peak memory 201016 kb
Host smart-48df85b5-4b72-448a-84c4-1a4198a07b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393753435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.2393753435
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.1711858501
Short name T448
Test name
Test status
Simulation time 433643797 ps
CPU time 1.64 seconds
Started Jan 07 01:05:55 PM PST 24
Finished Jan 07 01:06:00 PM PST 24
Peak memory 200668 kb
Host smart-facc31f3-2e80-45c9-a485-757c19284ef8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711858501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.1711858501
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.3305725870
Short name T274
Test name
Test status
Simulation time 336422470893 ps
CPU time 94.91 seconds
Started Jan 07 01:06:25 PM PST 24
Finished Jan 07 01:08:04 PM PST 24
Peak memory 200964 kb
Host smart-d95b0423-876a-48c3-9fc2-e3c105d73f3f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305725870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.3305725870
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.508924149
Short name T251
Test name
Test status
Simulation time 229608829887 ps
CPU time 484.86 seconds
Started Jan 07 01:06:30 PM PST 24
Finished Jan 07 01:14:54 PM PST 24
Peak memory 201216 kb
Host smart-50eea19b-d412-4269-af05-ec30bae4ea91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508924149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all.
508924149
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.2702223678
Short name T216
Test name
Test status
Simulation time 165592449663 ps
CPU time 92.48 seconds
Started Jan 07 01:06:36 PM PST 24
Finished Jan 07 01:08:23 PM PST 24
Peak memory 200892 kb
Host smart-848e329b-c6aa-439e-bcc7-4450eedc4e06
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702223678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.2702223678
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.1111947660
Short name T278
Test name
Test status
Simulation time 327510294346 ps
CPU time 189.92 seconds
Started Jan 07 01:07:01 PM PST 24
Finished Jan 07 01:10:18 PM PST 24
Peak memory 200816 kb
Host smart-212545b5-3660-4122-922d-9f0f61ecea94
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111947660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.1111947660
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.1974026739
Short name T152
Test name
Test status
Simulation time 94102988354 ps
CPU time 494.55 seconds
Started Jan 07 01:06:10 PM PST 24
Finished Jan 07 01:14:26 PM PST 24
Peak memory 201356 kb
Host smart-207bc97d-59c4-49c2-a73e-bc95ce2f0e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974026739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.1974026739
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.1721793639
Short name T290
Test name
Test status
Simulation time 85712703165 ps
CPU time 48.43 seconds
Started Jan 07 01:06:20 PM PST 24
Finished Jan 07 01:07:09 PM PST 24
Peak memory 201000 kb
Host smart-e54dffbe-2576-4677-8eb1-535ef4c26661
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721793639 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.1721793639
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.3765682060
Short name T122
Test name
Test status
Simulation time 310192391736 ps
CPU time 194.49 seconds
Started Jan 07 01:07:47 PM PST 24
Finished Jan 07 01:11:11 PM PST 24
Peak memory 201400 kb
Host smart-7634bf1e-6fc6-4918-acac-6ce64a72a762
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765682060 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.3765682060
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.2015075122
Short name T243
Test name
Test status
Simulation time 328386926022 ps
CPU time 186.39 seconds
Started Jan 07 01:07:36 PM PST 24
Finished Jan 07 01:10:46 PM PST 24
Peak memory 200856 kb
Host smart-76e77c0d-ba50-46a8-9602-7d31fbb82166
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015075122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.2015075122
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.692785748
Short name T230
Test name
Test status
Simulation time 320771759857 ps
CPU time 172.72 seconds
Started Jan 07 01:07:53 PM PST 24
Finished Jan 07 01:10:50 PM PST 24
Peak memory 200788 kb
Host smart-4686a02e-760d-4fc3-8e35-85fb67d8877d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692785748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.692785748
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.2967260017
Short name T189
Test name
Test status
Simulation time 123235043104 ps
CPU time 641.88 seconds
Started Jan 07 01:06:32 PM PST 24
Finished Jan 07 01:17:33 PM PST 24
Peak memory 201336 kb
Host smart-18330587-05a2-425e-a883-f3e42d22aef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967260017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.2967260017
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.3169150506
Short name T332
Test name
Test status
Simulation time 323054211945 ps
CPU time 802.49 seconds
Started Jan 07 01:06:29 PM PST 24
Finished Jan 07 01:20:13 PM PST 24
Peak memory 200716 kb
Host smart-e0129986-1d7b-43b9-8857-3d42a53ab265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169150506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.3169150506
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.1059460251
Short name T292
Test name
Test status
Simulation time 493849745765 ps
CPU time 281.87 seconds
Started Jan 07 01:06:48 PM PST 24
Finished Jan 07 01:11:44 PM PST 24
Peak memory 200928 kb
Host smart-bc5c660f-8370-4991-bd96-d2b410ef74a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059460251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.1059460251
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.1923974737
Short name T180
Test name
Test status
Simulation time 105014780182 ps
CPU time 461.39 seconds
Started Jan 07 01:07:00 PM PST 24
Finished Jan 07 01:14:49 PM PST 24
Peak memory 201384 kb
Host smart-3522921a-317e-4ae8-b141-cd6be3239950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923974737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.1923974737
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.2376477888
Short name T26
Test name
Test status
Simulation time 8782824770 ps
CPU time 7.78 seconds
Started Jan 07 12:38:07 PM PST 24
Finished Jan 07 12:39:15 PM PST 24
Peak memory 200820 kb
Host smart-363271c0-a711-4768-b3d6-6cbbb4916a1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376477888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.2376477888
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.377496080
Short name T12
Test name
Test status
Simulation time 4296864357 ps
CPU time 3.78 seconds
Started Jan 07 12:38:31 PM PST 24
Finished Jan 07 12:39:51 PM PST 24
Peak memory 200684 kb
Host smart-3bf5326c-9371-4ca2-b285-531469d2bd60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377496080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_in
tg_err.377496080
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.4134829173
Short name T215
Test name
Test status
Simulation time 497289879334 ps
CPU time 607.51 seconds
Started Jan 07 01:06:23 PM PST 24
Finished Jan 07 01:16:32 PM PST 24
Peak memory 200984 kb
Host smart-17cb7aec-5ef7-4e04-bbe0-53ed505454e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134829173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.4134829173
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.2412421133
Short name T192
Test name
Test status
Simulation time 539190040970 ps
CPU time 1653.65 seconds
Started Jan 07 01:06:10 PM PST 24
Finished Jan 07 01:33:45 PM PST 24
Peak memory 209564 kb
Host smart-ad215c94-0ddc-461f-803b-8d92ac84ebaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412421133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.2412421133
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.2882671410
Short name T244
Test name
Test status
Simulation time 532016349754 ps
CPU time 450.9 seconds
Started Jan 07 01:06:18 PM PST 24
Finished Jan 07 01:13:50 PM PST 24
Peak memory 209576 kb
Host smart-b2e2fa34-5bc6-45f5-83db-18436faaf509
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882671410 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.2882671410
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.248583403
Short name T339
Test name
Test status
Simulation time 51439936431 ps
CPU time 134.1 seconds
Started Jan 07 01:06:19 PM PST 24
Finished Jan 07 01:08:34 PM PST 24
Peak memory 216712 kb
Host smart-38f6fb36-ae64-4ed3-ac0d-9bbaeb58cf02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248583403 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.248583403
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.2959851104
Short name T265
Test name
Test status
Simulation time 488205298133 ps
CPU time 586.48 seconds
Started Jan 07 01:06:30 PM PST 24
Finished Jan 07 01:16:35 PM PST 24
Peak memory 200972 kb
Host smart-c2ac5b18-1eb1-4050-a911-555e7d1c97f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959851104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.2959851104
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.4234640837
Short name T218
Test name
Test status
Simulation time 493861005451 ps
CPU time 1110.88 seconds
Started Jan 07 01:06:43 PM PST 24
Finished Jan 07 01:25:30 PM PST 24
Peak memory 200368 kb
Host smart-c33e67f4-ee55-47da-aa0d-8f8185c5805a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234640837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.4234640837
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.2076187637
Short name T242
Test name
Test status
Simulation time 485622456613 ps
CPU time 265.47 seconds
Started Jan 07 01:06:36 PM PST 24
Finished Jan 07 01:11:17 PM PST 24
Peak memory 200848 kb
Host smart-4aa45396-d4b9-4df8-a46e-7a6077cf2576
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076187637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.2076187637
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.2380140266
Short name T343
Test name
Test status
Simulation time 114408959870 ps
CPU time 413.49 seconds
Started Jan 07 01:06:58 PM PST 24
Finished Jan 07 01:14:01 PM PST 24
Peak memory 201220 kb
Host smart-647c5579-3cb4-4dfa-8f45-d7f384a1752e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380140266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.2380140266
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.1292603479
Short name T280
Test name
Test status
Simulation time 162210623900 ps
CPU time 133.44 seconds
Started Jan 07 01:07:34 PM PST 24
Finished Jan 07 01:09:50 PM PST 24
Peak memory 210232 kb
Host smart-c7ec9934-3a31-4028-a812-664580409e1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292603479 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.1292603479
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.1628809397
Short name T96
Test name
Test status
Simulation time 168579200723 ps
CPU time 397.86 seconds
Started Jan 07 01:07:18 PM PST 24
Finished Jan 07 01:13:57 PM PST 24
Peak memory 200876 kb
Host smart-dc3e9bc0-13dd-4700-81c7-b9161cfe0128
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628809397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.1628809397
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.231378360
Short name T177
Test name
Test status
Simulation time 127231773177 ps
CPU time 493.27 seconds
Started Jan 07 01:07:45 PM PST 24
Finished Jan 07 01:16:05 PM PST 24
Peak memory 201340 kb
Host smart-cdaab4e3-f356-42be-b421-f7b4cdd2a5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231378360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.231378360
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.1090016478
Short name T285
Test name
Test status
Simulation time 493534268112 ps
CPU time 282.27 seconds
Started Jan 07 01:08:12 PM PST 24
Finished Jan 07 01:12:57 PM PST 24
Peak memory 200936 kb
Host smart-b30e7313-cfab-47da-9149-bcc4ac224a9c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090016478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.1090016478
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2854843430
Short name T347
Test name
Test status
Simulation time 440928773 ps
CPU time 1.21 seconds
Started Jan 07 12:38:28 PM PST 24
Finished Jan 07 12:39:44 PM PST 24
Peak memory 200492 kb
Host smart-65b29a14-8aa0-40c6-9a78-77f286d2bc2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854843430 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.2854843430
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.3344131293
Short name T80
Test name
Test status
Simulation time 568499867 ps
CPU time 2 seconds
Started Jan 07 12:37:38 PM PST 24
Finished Jan 07 12:39:12 PM PST 24
Peak memory 200432 kb
Host smart-05fd9af7-8f76-4249-aab8-45fd6047a2ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344131293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.3344131293
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.3779612279
Short name T351
Test name
Test status
Simulation time 470999931 ps
CPU time 1.19 seconds
Started Jan 07 12:38:03 PM PST 24
Finished Jan 07 12:39:33 PM PST 24
Peak memory 200124 kb
Host smart-0475b721-c7e1-4603-9319-2c46820e481f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779612279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.3779612279
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2592153646
Short name T850
Test name
Test status
Simulation time 4831497269 ps
CPU time 3.06 seconds
Started Jan 07 12:37:52 PM PST 24
Finished Jan 07 12:39:20 PM PST 24
Peak memory 200724 kb
Host smart-3414264e-d421-4297-8648-18d99947a6f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592153646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.2592153646
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3740481498
Short name T57
Test name
Test status
Simulation time 564969963 ps
CPU time 1.44 seconds
Started Jan 07 12:37:46 PM PST 24
Finished Jan 07 12:39:18 PM PST 24
Peak memory 200704 kb
Host smart-f16055d7-0621-429b-af96-eb4ab088a64f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740481498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.3740481498
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2976398967
Short name T374
Test name
Test status
Simulation time 8511293146 ps
CPU time 9.13 seconds
Started Jan 07 12:37:57 PM PST 24
Finished Jan 07 12:39:28 PM PST 24
Peak memory 200760 kb
Host smart-b7917418-5923-49da-ac0a-4a03d21a5eda
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976398967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.2976398967
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.4277722858
Short name T67
Test name
Test status
Simulation time 388013929 ps
CPU time 2.11 seconds
Started Jan 07 12:37:57 PM PST 24
Finished Jan 07 12:39:01 PM PST 24
Peak memory 200628 kb
Host smart-082fedda-3e8f-439d-a255-62c9e6b9bef4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277722858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.4277722858
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.1751431890
Short name T79
Test name
Test status
Simulation time 50420344572 ps
CPU time 81.64 seconds
Started Jan 07 12:38:17 PM PST 24
Finished Jan 07 12:40:40 PM PST 24
Peak memory 200644 kb
Host smart-141e26a8-f604-4478-8fc5-97f7b39d7cde
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751431890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.1751431890
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.4021901225
Short name T70
Test name
Test status
Simulation time 1186232594 ps
CPU time 3.53 seconds
Started Jan 07 12:38:10 PM PST 24
Finished Jan 07 12:39:15 PM PST 24
Peak memory 200496 kb
Host smart-71aa1490-6079-409d-8520-3ccc1fc5dbdd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021901225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.4021901225
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1863188991
Short name T853
Test name
Test status
Simulation time 468233254 ps
CPU time 0.84 seconds
Started Jan 07 12:37:56 PM PST 24
Finished Jan 07 12:39:12 PM PST 24
Peak memory 200508 kb
Host smart-828574f5-6bce-43b6-ab9f-5f755ad077cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863188991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.1863188991
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.2451460226
Short name T866
Test name
Test status
Simulation time 399642783 ps
CPU time 0.81 seconds
Started Jan 07 12:37:59 PM PST 24
Finished Jan 07 12:39:41 PM PST 24
Peak memory 200192 kb
Host smart-67101e94-d8a5-42e7-9d49-2cf4ce7c11cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451460226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.2451460226
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3035536767
Short name T68
Test name
Test status
Simulation time 2810660352 ps
CPU time 3.26 seconds
Started Jan 07 12:38:20 PM PST 24
Finished Jan 07 12:39:56 PM PST 24
Peak memory 200552 kb
Host smart-1e4a3d1d-c3d8-4337-88f8-64ed81c42b36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035536767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.3035536767
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.4090687180
Short name T861
Test name
Test status
Simulation time 520910697 ps
CPU time 2.68 seconds
Started Jan 07 12:37:51 PM PST 24
Finished Jan 07 12:39:14 PM PST 24
Peak memory 200648 kb
Host smart-b1aa6c6c-e409-4cdf-b2b6-a6556720051f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090687180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.4090687180
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1097498825
Short name T881
Test name
Test status
Simulation time 608788153 ps
CPU time 1.19 seconds
Started Jan 07 12:38:02 PM PST 24
Finished Jan 07 12:39:34 PM PST 24
Peak memory 200516 kb
Host smart-9bef95f0-2f70-4469-91ae-08f9f6603a6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097498825 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.1097498825
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.584325601
Short name T82
Test name
Test status
Simulation time 403336020 ps
CPU time 1.57 seconds
Started Jan 07 12:37:51 PM PST 24
Finished Jan 07 12:39:06 PM PST 24
Peak memory 200472 kb
Host smart-3fe1697f-90c6-4823-b337-af8e81fbefda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584325601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.584325601
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.3814859928
Short name T363
Test name
Test status
Simulation time 505232231 ps
CPU time 0.83 seconds
Started Jan 07 12:38:57 PM PST 24
Finished Jan 07 12:40:08 PM PST 24
Peak memory 200284 kb
Host smart-c500845a-cf5d-4979-9107-9433d457185a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814859928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.3814859928
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.4237959169
Short name T878
Test name
Test status
Simulation time 3536150822 ps
CPU time 3.17 seconds
Started Jan 07 12:38:12 PM PST 24
Finished Jan 07 12:40:13 PM PST 24
Peak memory 200852 kb
Host smart-271efa40-e5b8-4ea0-9180-78b77647024a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237959169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.4237959169
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2614497682
Short name T856
Test name
Test status
Simulation time 379213872 ps
CPU time 2.64 seconds
Started Jan 07 12:38:50 PM PST 24
Finished Jan 07 12:40:23 PM PST 24
Peak memory 200788 kb
Host smart-c4fa7441-26df-4e23-9f79-40566e82ad54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614497682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.2614497682
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1797165326
Short name T83
Test name
Test status
Simulation time 492421675 ps
CPU time 0.92 seconds
Started Jan 07 12:38:17 PM PST 24
Finished Jan 07 12:39:41 PM PST 24
Peak memory 200436 kb
Host smart-fc9d68bb-bdee-4e22-8225-3814b85c60b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797165326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.1797165326
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.349556151
Short name T367
Test name
Test status
Simulation time 491987947 ps
CPU time 0.93 seconds
Started Jan 07 12:37:56 PM PST 24
Finished Jan 07 12:39:08 PM PST 24
Peak memory 200248 kb
Host smart-7464b7b0-ffdb-4cb2-aa0e-56103d86eed9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349556151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.349556151
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3819178692
Short name T370
Test name
Test status
Simulation time 5478622328 ps
CPU time 6.55 seconds
Started Jan 07 12:38:38 PM PST 24
Finished Jan 07 12:39:46 PM PST 24
Peak memory 200704 kb
Host smart-25063179-56bb-4c65-a1b8-47d13dcf4bfc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819178692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.3819178692
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2229416629
Short name T884
Test name
Test status
Simulation time 429483882 ps
CPU time 2.17 seconds
Started Jan 07 12:38:05 PM PST 24
Finished Jan 07 12:39:13 PM PST 24
Peak memory 200692 kb
Host smart-e6a3da27-42ad-47f1-9077-f096451ecba9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229416629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.2229416629
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1723113316
Short name T337
Test name
Test status
Simulation time 8332080828 ps
CPU time 22.42 seconds
Started Jan 07 12:38:25 PM PST 24
Finished Jan 07 12:40:01 PM PST 24
Peak memory 200692 kb
Host smart-935f6c8b-b1e6-482d-96de-b8fb55121653
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723113316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.1723113316
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.400065297
Short name T172
Test name
Test status
Simulation time 320642169 ps
CPU time 1.45 seconds
Started Jan 07 12:38:14 PM PST 24
Finished Jan 07 12:40:14 PM PST 24
Peak memory 200504 kb
Host smart-f8e3b7bb-b04e-4f56-b244-718c0dde2196
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400065297 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.400065297
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1771082310
Short name T25
Test name
Test status
Simulation time 506681788 ps
CPU time 1.91 seconds
Started Jan 07 12:38:18 PM PST 24
Finished Jan 07 12:39:18 PM PST 24
Peak memory 200424 kb
Host smart-690a9743-5ab3-4406-bc08-bc43d4383e21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771082310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.1771082310
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.2409211319
Short name T348
Test name
Test status
Simulation time 476310046 ps
CPU time 0.88 seconds
Started Jan 07 12:38:29 PM PST 24
Finished Jan 07 12:39:43 PM PST 24
Peak memory 200184 kb
Host smart-6a9c5163-65c8-442e-aaae-cad07bbb9a17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409211319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.2409211319
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3974470260
Short name T858
Test name
Test status
Simulation time 8486340000 ps
CPU time 21.75 seconds
Started Jan 07 12:37:54 PM PST 24
Finished Jan 07 12:39:29 PM PST 24
Peak memory 200748 kb
Host smart-92db1280-13d4-4c66-88e3-4ea5b3f2e8f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974470260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.3974470260
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3372178826
Short name T173
Test name
Test status
Simulation time 375690368 ps
CPU time 1.03 seconds
Started Jan 07 12:38:01 PM PST 24
Finished Jan 07 12:39:19 PM PST 24
Peak memory 200488 kb
Host smart-695e1550-2762-4cdd-bed2-a8a093686981
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372178826 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.3372178826
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2755038784
Short name T864
Test name
Test status
Simulation time 333144486 ps
CPU time 1.42 seconds
Started Jan 07 12:38:03 PM PST 24
Finished Jan 07 12:39:13 PM PST 24
Peak memory 200504 kb
Host smart-bf7b717c-8e27-426a-96b2-fefb4ce843c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755038784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.2755038784
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.976256005
Short name T871
Test name
Test status
Simulation time 509656372 ps
CPU time 1.63 seconds
Started Jan 07 12:38:04 PM PST 24
Finished Jan 07 12:39:21 PM PST 24
Peak memory 200412 kb
Host smart-2da9d8b2-5d29-4e3f-897c-d93bb6c020df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976256005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.976256005
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3461898514
Short name T372
Test name
Test status
Simulation time 4195113457 ps
CPU time 16.59 seconds
Started Jan 07 12:37:57 PM PST 24
Finished Jan 07 12:39:16 PM PST 24
Peak memory 200768 kb
Host smart-3c46602e-0d0b-4887-b431-85aebc194988
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461898514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.3461898514
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3653426353
Short name T872
Test name
Test status
Simulation time 4633866841 ps
CPU time 4.37 seconds
Started Jan 07 12:38:06 PM PST 24
Finished Jan 07 12:39:32 PM PST 24
Peak memory 200596 kb
Host smart-0c2bfa46-e372-4369-b61e-6eb0cb16012a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653426353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.3653426353
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3301509006
Short name T350
Test name
Test status
Simulation time 422553138 ps
CPU time 1.15 seconds
Started Jan 07 12:38:09 PM PST 24
Finished Jan 07 12:39:23 PM PST 24
Peak memory 200516 kb
Host smart-1ec4456e-a2d1-4893-8245-ce40a94f020f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301509006 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.3301509006
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.505760904
Short name T3
Test name
Test status
Simulation time 526930654 ps
CPU time 0.75 seconds
Started Jan 07 12:38:05 PM PST 24
Finished Jan 07 12:39:47 PM PST 24
Peak memory 200452 kb
Host smart-d8ea19b4-fbb8-40d7-9d1f-6a556fb2ac56
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505760904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.505760904
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.116390234
Short name T24
Test name
Test status
Simulation time 4768915187 ps
CPU time 2.88 seconds
Started Jan 07 12:38:08 PM PST 24
Finished Jan 07 12:39:22 PM PST 24
Peak memory 200716 kb
Host smart-de665f0e-3d49-42d4-aa44-1a75abf41a3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116390234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_c
trl_same_csr_outstanding.116390234
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1042308449
Short name T60
Test name
Test status
Simulation time 383539397 ps
CPU time 1.65 seconds
Started Jan 07 12:38:06 PM PST 24
Finished Jan 07 12:39:18 PM PST 24
Peak memory 200688 kb
Host smart-4b951368-765c-449a-9b21-eea284a9ae04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042308449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.1042308449
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2027266233
Short name T885
Test name
Test status
Simulation time 4543437133 ps
CPU time 4.03 seconds
Started Jan 07 12:38:32 PM PST 24
Finished Jan 07 12:39:44 PM PST 24
Peak memory 200660 kb
Host smart-41934cde-9021-4b4d-8f56-77f0fa176558
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027266233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.2027266233
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3792260276
Short name T64
Test name
Test status
Simulation time 564476973 ps
CPU time 2.17 seconds
Started Jan 07 12:37:46 PM PST 24
Finished Jan 07 12:39:00 PM PST 24
Peak memory 200576 kb
Host smart-fb5c223d-36ee-4279-84d3-1cfe74777336
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792260276 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.3792260276
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3307766511
Short name T356
Test name
Test status
Simulation time 503734030 ps
CPU time 0.77 seconds
Started Jan 07 12:38:37 PM PST 24
Finished Jan 07 12:40:16 PM PST 24
Peak memory 200368 kb
Host smart-ef04a095-8bc3-4b2f-b11f-b131e8319b9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307766511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.3307766511
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1365244777
Short name T84
Test name
Test status
Simulation time 4759120468 ps
CPU time 6.19 seconds
Started Jan 07 12:38:43 PM PST 24
Finished Jan 07 12:40:21 PM PST 24
Peak memory 200688 kb
Host smart-018a90c5-a5c1-4fcb-9b37-26b1792c1b6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365244777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.1365244777
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1676386562
Short name T55
Test name
Test status
Simulation time 562319975 ps
CPU time 2.44 seconds
Started Jan 07 12:38:03 PM PST 24
Finished Jan 07 12:39:17 PM PST 24
Peak memory 200664 kb
Host smart-9cd48c46-c01b-4c3d-a330-930671b5d30c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676386562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.1676386562
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3356036125
Short name T867
Test name
Test status
Simulation time 4528698419 ps
CPU time 3.83 seconds
Started Jan 07 12:37:58 PM PST 24
Finished Jan 07 12:39:03 PM PST 24
Peak memory 200760 kb
Host smart-d5aedac3-2584-4e83-9794-73819a409288
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356036125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.3356036125
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.913013645
Short name T859
Test name
Test status
Simulation time 395044550 ps
CPU time 1.74 seconds
Started Jan 07 12:38:07 PM PST 24
Finished Jan 07 12:39:09 PM PST 24
Peak memory 200508 kb
Host smart-a76c6306-fd20-4298-b4a6-ee7d7ee66307
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913013645 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.913013645
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.156125687
Short name T71
Test name
Test status
Simulation time 508515075 ps
CPU time 1.78 seconds
Started Jan 07 12:38:10 PM PST 24
Finished Jan 07 12:39:35 PM PST 24
Peak memory 200460 kb
Host smart-0e088393-b9b2-4c3b-b4b4-532a22cc3aae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156125687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.156125687
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1904460265
Short name T11
Test name
Test status
Simulation time 2820723859 ps
CPU time 2.35 seconds
Started Jan 07 12:38:40 PM PST 24
Finished Jan 07 12:39:45 PM PST 24
Peak memory 200532 kb
Host smart-86f78771-5015-4b48-932e-162ff0c7b3a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904460265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.1904460265
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.175715266
Short name T852
Test name
Test status
Simulation time 4084341264 ps
CPU time 10.83 seconds
Started Jan 07 12:38:43 PM PST 24
Finished Jan 07 12:40:18 PM PST 24
Peak memory 200692 kb
Host smart-8beefc95-1ee8-4337-92cd-c0482b870950
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175715266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_in
tg_err.175715266
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.2412506360
Short name T171
Test name
Test status
Simulation time 415926360 ps
CPU time 1.59 seconds
Started Jan 07 12:38:24 PM PST 24
Finished Jan 07 12:39:39 PM PST 24
Peak memory 200544 kb
Host smart-d47d357e-825b-4ed4-ba70-0e6407fe24ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412506360 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.2412506360
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.621623818
Short name T882
Test name
Test status
Simulation time 398965866 ps
CPU time 1.5 seconds
Started Jan 07 12:38:56 PM PST 24
Finished Jan 07 12:40:29 PM PST 24
Peak memory 200420 kb
Host smart-de9c3344-71f0-40eb-81d1-e28da6d762ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621623818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.621623818
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.152377130
Short name T77
Test name
Test status
Simulation time 558359182 ps
CPU time 0.67 seconds
Started Jan 07 12:38:40 PM PST 24
Finished Jan 07 12:40:19 PM PST 24
Peak memory 200120 kb
Host smart-a62dff4f-2187-496a-9766-7b0f8c7c12e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152377130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.152377130
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.238265797
Short name T868
Test name
Test status
Simulation time 2476896259 ps
CPU time 3.89 seconds
Started Jan 07 12:38:04 PM PST 24
Finished Jan 07 12:39:15 PM PST 24
Peak memory 200504 kb
Host smart-51bd163c-4118-4997-8557-1ca6965f8ef6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238265797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_c
trl_same_csr_outstanding.238265797
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.277925884
Short name T35
Test name
Test status
Simulation time 536796460 ps
CPU time 2.37 seconds
Started Jan 07 12:38:58 PM PST 24
Finished Jan 07 12:40:21 PM PST 24
Peak memory 200708 kb
Host smart-db2e0643-79ee-4f78-8ebb-011eac239d9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277925884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.277925884
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2779568956
Short name T58
Test name
Test status
Simulation time 8792530981 ps
CPU time 21.66 seconds
Started Jan 07 12:38:29 PM PST 24
Finished Jan 07 12:40:04 PM PST 24
Peak memory 200696 kb
Host smart-bdcb6a25-1e55-4211-b96a-f28a6e222cf9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779568956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.2779568956
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.843628275
Short name T34
Test name
Test status
Simulation time 583383046 ps
CPU time 1.03 seconds
Started Jan 07 12:38:12 PM PST 24
Finished Jan 07 12:39:47 PM PST 24
Peak memory 200544 kb
Host smart-dd797654-b660-4f7e-bf02-a766a5021c9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843628275 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.843628275
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.4186627506
Short name T69
Test name
Test status
Simulation time 450444977 ps
CPU time 1.65 seconds
Started Jan 07 12:38:32 PM PST 24
Finished Jan 07 12:39:34 PM PST 24
Peak memory 200432 kb
Host smart-7c130a88-9d2f-4918-b28b-c3791bcd908f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186627506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.4186627506
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.1340685450
Short name T840
Test name
Test status
Simulation time 433140642 ps
CPU time 0.68 seconds
Started Jan 07 12:38:11 PM PST 24
Finished Jan 07 12:39:25 PM PST 24
Peak memory 200408 kb
Host smart-39353610-1d61-40e2-a417-7c5581267d2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340685450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.1340685450
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1563612415
Short name T873
Test name
Test status
Simulation time 525740875 ps
CPU time 2.58 seconds
Started Jan 07 12:38:15 PM PST 24
Finished Jan 07 12:39:49 PM PST 24
Peak memory 200680 kb
Host smart-cccf6bbf-007e-496b-99c9-da0d846ee95c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563612415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.1563612415
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2122047903
Short name T8
Test name
Test status
Simulation time 323808411 ps
CPU time 1.41 seconds
Started Jan 07 12:38:43 PM PST 24
Finished Jan 07 12:40:02 PM PST 24
Peak memory 200480 kb
Host smart-8c2b180c-ac10-4bd4-8dbd-1de23db47a11
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122047903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.2122047903
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.208142534
Short name T874
Test name
Test status
Simulation time 531462353 ps
CPU time 1.81 seconds
Started Jan 07 12:38:41 PM PST 24
Finished Jan 07 12:40:00 PM PST 24
Peak memory 200400 kb
Host smart-5d7c6921-d01a-478f-a49f-48192a2edf58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208142534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.208142534
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.862048946
Short name T78
Test name
Test status
Simulation time 2314085382 ps
CPU time 3.02 seconds
Started Jan 07 12:38:25 PM PST 24
Finished Jan 07 12:39:50 PM PST 24
Peak memory 200512 kb
Host smart-c4f0ec6e-fea1-4062-a478-45ebab66cfe6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862048946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_c
trl_same_csr_outstanding.862048946
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3347191304
Short name T53
Test name
Test status
Simulation time 8794524153 ps
CPU time 7.23 seconds
Started Jan 07 12:38:30 PM PST 24
Finished Jan 07 12:39:54 PM PST 24
Peak memory 200696 kb
Host smart-869f2541-d952-4ddc-a15c-6a12552a7904
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347191304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.3347191304
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.4274702859
Short name T869
Test name
Test status
Simulation time 993047716 ps
CPU time 1.74 seconds
Started Jan 07 12:38:42 PM PST 24
Finished Jan 07 12:40:28 PM PST 24
Peak memory 200656 kb
Host smart-de79e3c7-0acc-4734-8298-fb75ec4c5fd6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274702859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.4274702859
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3938781568
Short name T1
Test name
Test status
Simulation time 27049104253 ps
CPU time 6.94 seconds
Started Jan 07 12:37:48 PM PST 24
Finished Jan 07 12:39:12 PM PST 24
Peak memory 200748 kb
Host smart-505bb779-c071-45f5-8c46-c722e416beba
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938781568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.3938781568
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.500631088
Short name T875
Test name
Test status
Simulation time 651708827 ps
CPU time 1.06 seconds
Started Jan 07 12:38:28 PM PST 24
Finished Jan 07 12:39:56 PM PST 24
Peak memory 200524 kb
Host smart-75b38d42-1dba-4086-97f8-650907560865
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500631088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_re
set.500631088
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2954853484
Short name T354
Test name
Test status
Simulation time 402487363 ps
CPU time 1.75 seconds
Started Jan 07 12:37:56 PM PST 24
Finished Jan 07 12:39:01 PM PST 24
Peak memory 200524 kb
Host smart-fca85cd1-29e5-4841-b6d9-077e4aca5c03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954853484 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.2954853484
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.4249765991
Short name T361
Test name
Test status
Simulation time 461953511 ps
CPU time 0.9 seconds
Started Jan 07 12:38:18 PM PST 24
Finished Jan 07 12:39:25 PM PST 24
Peak memory 200396 kb
Host smart-ad37a7d3-ec04-47e6-a238-7fb3fc9a10d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249765991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.4249765991
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3034648741
Short name T845
Test name
Test status
Simulation time 4582198081 ps
CPU time 1.74 seconds
Started Jan 07 12:38:37 PM PST 24
Finished Jan 07 12:40:22 PM PST 24
Peak memory 200764 kb
Host smart-af0f3003-98c2-437c-aa7c-52ac1310b089
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034648741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.3034648741
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2916494187
Short name T87
Test name
Test status
Simulation time 498242594 ps
CPU time 2.63 seconds
Started Jan 07 12:38:23 PM PST 24
Finished Jan 07 12:39:30 PM PST 24
Peak memory 200676 kb
Host smart-9c531e9c-b904-4f74-b6a2-5a30bc8f5184
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916494187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.2916494187
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.477153024
Short name T62
Test name
Test status
Simulation time 358652368 ps
CPU time 1.39 seconds
Started Jan 07 12:38:36 PM PST 24
Finished Jan 07 12:39:48 PM PST 24
Peak memory 200116 kb
Host smart-0b969155-a1a9-4215-a108-acdab4565cc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477153024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.477153024
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.227439069
Short name T855
Test name
Test status
Simulation time 300117676 ps
CPU time 0.94 seconds
Started Jan 07 12:38:20 PM PST 24
Finished Jan 07 12:39:30 PM PST 24
Peak memory 200284 kb
Host smart-ac339f3f-e4ff-4d79-91b1-3468ca484b7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227439069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.227439069
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1650180868
Short name T75
Test name
Test status
Simulation time 427966296 ps
CPU time 1.28 seconds
Started Jan 07 12:37:55 PM PST 24
Finished Jan 07 12:39:03 PM PST 24
Peak memory 200176 kb
Host smart-a8931d2f-1a8b-48e0-bab6-d68a793fba28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650180868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.1650180868
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3470773725
Short name T883
Test name
Test status
Simulation time 429735334 ps
CPU time 0.79 seconds
Started Jan 07 12:38:25 PM PST 24
Finished Jan 07 12:39:38 PM PST 24
Peak memory 200168 kb
Host smart-bfe7676b-3a63-46a9-ae16-9aca8040c20d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470773725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.3470773725
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.1934642999
Short name T359
Test name
Test status
Simulation time 513396835 ps
CPU time 1.19 seconds
Started Jan 07 12:38:32 PM PST 24
Finished Jan 07 12:40:05 PM PST 24
Peak memory 200176 kb
Host smart-970c27f4-6717-4468-807a-760cc8399552
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934642999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.1934642999
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3410421132
Short name T346
Test name
Test status
Simulation time 382354275 ps
CPU time 1.07 seconds
Started Jan 07 12:38:20 PM PST 24
Finished Jan 07 12:39:35 PM PST 24
Peak memory 200216 kb
Host smart-f140d0ac-d530-40de-84df-0d947439750e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410421132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.3410421132
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.4267336585
Short name T368
Test name
Test status
Simulation time 516748495 ps
CPU time 0.83 seconds
Started Jan 07 12:38:40 PM PST 24
Finished Jan 07 12:40:13 PM PST 24
Peak memory 200384 kb
Host smart-e51d87e3-b01d-48a0-b7aa-2cd624b47bb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267336585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.4267336585
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2719549972
Short name T74
Test name
Test status
Simulation time 809866638 ps
CPU time 3.29 seconds
Started Jan 07 12:37:59 PM PST 24
Finished Jan 07 12:39:25 PM PST 24
Peak memory 200432 kb
Host smart-49e0d153-47a8-4b98-a04e-df9930e269ef
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719549972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.2719549972
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3308014996
Short name T842
Test name
Test status
Simulation time 25919990430 ps
CPU time 84.06 seconds
Started Jan 07 12:38:30 PM PST 24
Finished Jan 07 12:40:53 PM PST 24
Peak memory 200824 kb
Host smart-3de9fe3a-9d3a-455a-b4b9-a7cc51c29b7c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308014996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.3308014996
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.4202239514
Short name T862
Test name
Test status
Simulation time 1199275511 ps
CPU time 1.34 seconds
Started Jan 07 12:38:09 PM PST 24
Finished Jan 07 12:39:17 PM PST 24
Peak memory 200560 kb
Host smart-6e2aca8f-4099-4a1f-8a8a-78cb9d5c62b8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202239514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.4202239514
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3383122588
Short name T844
Test name
Test status
Simulation time 526475982 ps
CPU time 1.03 seconds
Started Jan 07 12:38:15 PM PST 24
Finished Jan 07 12:39:48 PM PST 24
Peak memory 200536 kb
Host smart-c62bf553-9f79-4ea5-9ef6-e2f8685d6e50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383122588 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.3383122588
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.447085257
Short name T81
Test name
Test status
Simulation time 451840069 ps
CPU time 0.96 seconds
Started Jan 07 12:38:37 PM PST 24
Finished Jan 07 12:40:13 PM PST 24
Peak memory 200356 kb
Host smart-0b60535c-2f09-4e95-aa53-ee12b0a862e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447085257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.447085257
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.1512608279
Short name T865
Test name
Test status
Simulation time 482913343 ps
CPU time 1.69 seconds
Started Jan 07 12:38:28 PM PST 24
Finished Jan 07 12:39:31 PM PST 24
Peak memory 200080 kb
Host smart-5645a8aa-eb31-4175-a5ec-64b81bbdef4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512608279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.1512608279
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.958782876
Short name T23
Test name
Test status
Simulation time 2484533963 ps
CPU time 1.46 seconds
Started Jan 07 12:38:02 PM PST 24
Finished Jan 07 12:39:10 PM PST 24
Peak memory 200460 kb
Host smart-278765d3-9f98-41b5-9a41-d359e2ae085d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958782876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ct
rl_same_csr_outstanding.958782876
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1632360597
Short name T76
Test name
Test status
Simulation time 404773430 ps
CPU time 1.59 seconds
Started Jan 07 12:38:16 PM PST 24
Finished Jan 07 12:39:26 PM PST 24
Peak memory 200184 kb
Host smart-be2e3054-d619-4da3-8f96-4f2c97f93aed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632360597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.1632360597
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.371299301
Short name T876
Test name
Test status
Simulation time 505128920 ps
CPU time 1.71 seconds
Started Jan 07 12:38:19 PM PST 24
Finished Jan 07 12:39:24 PM PST 24
Peak memory 200176 kb
Host smart-aa7fe4f6-0f7e-4132-99cc-0990020d7109
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371299301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.371299301
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1570176597
Short name T27
Test name
Test status
Simulation time 357213260 ps
CPU time 0.99 seconds
Started Jan 07 12:38:43 PM PST 24
Finished Jan 07 12:39:59 PM PST 24
Peak memory 200212 kb
Host smart-0931df8e-105f-40a9-a75f-5129afccde8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570176597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.1570176597
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.682173056
Short name T847
Test name
Test status
Simulation time 476970773 ps
CPU time 0.87 seconds
Started Jan 07 12:38:22 PM PST 24
Finished Jan 07 12:39:25 PM PST 24
Peak memory 200228 kb
Host smart-de012eb2-b9d8-4641-8c08-b183ab93b5c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682173056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.682173056
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.2260863144
Short name T63
Test name
Test status
Simulation time 613869645 ps
CPU time 0.74 seconds
Started Jan 07 12:38:14 PM PST 24
Finished Jan 07 12:39:26 PM PST 24
Peak memory 200080 kb
Host smart-03624434-e1e6-44f7-a728-3a0405262e78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260863144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.2260863144
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3852449477
Short name T849
Test name
Test status
Simulation time 332673652 ps
CPU time 0.96 seconds
Started Jan 07 12:38:46 PM PST 24
Finished Jan 07 12:39:59 PM PST 24
Peak memory 200380 kb
Host smart-5b360c9f-0f90-441a-8c94-a51ce38eb311
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852449477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.3852449477
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.2844025429
Short name T358
Test name
Test status
Simulation time 527077733 ps
CPU time 0.82 seconds
Started Jan 07 12:38:35 PM PST 24
Finished Jan 07 12:39:39 PM PST 24
Peak memory 200268 kb
Host smart-0dd545b1-2916-4c84-9313-fee14f74d318
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844025429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.2844025429
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1398325565
Short name T375
Test name
Test status
Simulation time 381391623 ps
CPU time 1.44 seconds
Started Jan 07 12:38:37 PM PST 24
Finished Jan 07 12:40:33 PM PST 24
Peak memory 200128 kb
Host smart-aacfe2b0-88fe-4946-9bd8-932d8c134d70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398325565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.1398325565
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.819433963
Short name T848
Test name
Test status
Simulation time 453749815 ps
CPU time 0.89 seconds
Started Jan 07 12:38:18 PM PST 24
Finished Jan 07 12:39:58 PM PST 24
Peak memory 200372 kb
Host smart-1b3c757f-0859-43b4-bfd4-a7e4885263db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819433963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.819433963
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.3093074232
Short name T373
Test name
Test status
Simulation time 785411176 ps
CPU time 2.39 seconds
Started Jan 07 12:38:20 PM PST 24
Finished Jan 07 12:39:55 PM PST 24
Peak memory 200692 kb
Host smart-6619c80a-bfcb-4af6-8df1-9b8279ab285b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093074232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.3093074232
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.942798328
Short name T73
Test name
Test status
Simulation time 1421148571 ps
CPU time 3.73 seconds
Started Jan 07 12:38:28 PM PST 24
Finished Jan 07 12:40:01 PM PST 24
Peak memory 200680 kb
Host smart-983775e1-cff3-4d37-badf-a2555cc27264
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942798328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_b
ash.942798328
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1410104294
Short name T357
Test name
Test status
Simulation time 720356458 ps
CPU time 2.34 seconds
Started Jan 07 12:38:06 PM PST 24
Finished Jan 07 12:39:13 PM PST 24
Peak memory 200480 kb
Host smart-c4bff52f-bf5f-448b-bfd6-69fbc223f122
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410104294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.1410104294
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.1477140930
Short name T879
Test name
Test status
Simulation time 474162464 ps
CPU time 1.33 seconds
Started Jan 07 12:38:27 PM PST 24
Finished Jan 07 12:39:40 PM PST 24
Peak memory 200520 kb
Host smart-25fd9e40-369a-41ff-ae0d-ac00eca6c3c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477140930 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.1477140930
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3557310393
Short name T61
Test name
Test status
Simulation time 362397017 ps
CPU time 1.21 seconds
Started Jan 07 12:37:46 PM PST 24
Finished Jan 07 12:38:55 PM PST 24
Peak memory 200456 kb
Host smart-e1571421-cfd3-4aef-8d5b-753d4e217519
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557310393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.3557310393
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.852394017
Short name T345
Test name
Test status
Simulation time 367685515 ps
CPU time 0.82 seconds
Started Jan 07 12:38:17 PM PST 24
Finished Jan 07 12:39:20 PM PST 24
Peak memory 200376 kb
Host smart-0097e331-6490-457d-bfe0-f53bd083730d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852394017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.852394017
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.392956040
Short name T364
Test name
Test status
Simulation time 3571471296 ps
CPU time 8 seconds
Started Jan 07 12:38:29 PM PST 24
Finished Jan 07 12:39:59 PM PST 24
Peak memory 200848 kb
Host smart-02d2e291-c3d2-4b18-b689-23f1d77a1a50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392956040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ct
rl_same_csr_outstanding.392956040
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1153603791
Short name T369
Test name
Test status
Simulation time 493109677 ps
CPU time 1.52 seconds
Started Jan 07 12:38:23 PM PST 24
Finished Jan 07 12:39:23 PM PST 24
Peak memory 200416 kb
Host smart-34abc1d3-12dd-45f1-8815-d93d8280267e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153603791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.1153603791
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.1183147244
Short name T352
Test name
Test status
Simulation time 478748752 ps
CPU time 1.74 seconds
Started Jan 07 12:38:22 PM PST 24
Finished Jan 07 12:39:53 PM PST 24
Peak memory 200336 kb
Host smart-51397b10-bd36-4f26-922b-84257901fc10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183147244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.1183147244
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2530663647
Short name T362
Test name
Test status
Simulation time 448812813 ps
CPU time 0.84 seconds
Started Jan 07 12:38:14 PM PST 24
Finished Jan 07 12:40:23 PM PST 24
Peak memory 200132 kb
Host smart-cca3a09d-a011-4257-8311-48adf275793a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530663647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.2530663647
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2132539694
Short name T880
Test name
Test status
Simulation time 454521837 ps
CPU time 0.8 seconds
Started Jan 07 12:38:39 PM PST 24
Finished Jan 07 12:40:29 PM PST 24
Peak memory 200260 kb
Host smart-ec6c3d95-2342-4407-8332-a473d378c758
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132539694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.2132539694
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2149035039
Short name T349
Test name
Test status
Simulation time 489976918 ps
CPU time 1.64 seconds
Started Jan 07 12:38:09 PM PST 24
Finished Jan 07 12:39:17 PM PST 24
Peak memory 200456 kb
Host smart-e4c5b67a-667d-4511-8a56-0f99eab68ecf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149035039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.2149035039
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.1383058482
Short name T886
Test name
Test status
Simulation time 472138426 ps
CPU time 1.68 seconds
Started Jan 07 12:38:23 PM PST 24
Finished Jan 07 12:39:26 PM PST 24
Peak memory 200236 kb
Host smart-20c2bde0-eee5-439b-9a96-7050d20665eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383058482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.1383058482
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.1470512505
Short name T353
Test name
Test status
Simulation time 384285778 ps
CPU time 1.11 seconds
Started Jan 07 12:38:37 PM PST 24
Finished Jan 07 12:40:07 PM PST 24
Peak memory 200204 kb
Host smart-fd75f08d-0bcf-4034-9c9b-8aecff8e4774
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470512505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.1470512505
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2535386575
Short name T366
Test name
Test status
Simulation time 525711480 ps
CPU time 1.78 seconds
Started Jan 07 12:38:54 PM PST 24
Finished Jan 07 12:40:22 PM PST 24
Peak memory 200200 kb
Host smart-3fa262f9-9d0f-4eb5-8f71-aded4b2b9cfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535386575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.2535386575
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.3262054924
Short name T851
Test name
Test status
Simulation time 366032034 ps
CPU time 0.77 seconds
Started Jan 07 12:38:16 PM PST 24
Finished Jan 07 12:39:37 PM PST 24
Peak memory 200124 kb
Host smart-896803c9-4549-4bab-b39d-f1c8f88e5da6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262054924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.3262054924
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.69789561
Short name T65
Test name
Test status
Simulation time 282953750 ps
CPU time 1.28 seconds
Started Jan 07 12:38:13 PM PST 24
Finished Jan 07 12:39:52 PM PST 24
Peak memory 200140 kb
Host smart-143f6a3c-6002-46b7-b092-6c7c5e62050d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69789561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.69789561
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3085214201
Short name T170
Test name
Test status
Simulation time 432209999 ps
CPU time 0.98 seconds
Started Jan 07 12:38:45 PM PST 24
Finished Jan 07 12:40:32 PM PST 24
Peak memory 200512 kb
Host smart-d67a27e7-a2a8-4ea1-b64a-59d297f1f63b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085214201 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.3085214201
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.918883514
Short name T371
Test name
Test status
Simulation time 472761522 ps
CPU time 0.94 seconds
Started Jan 07 12:38:35 PM PST 24
Finished Jan 07 12:39:43 PM PST 24
Peak memory 200456 kb
Host smart-f1764cf0-07a5-4be6-b451-82445abc4054
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918883514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.918883514
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.813252302
Short name T870
Test name
Test status
Simulation time 501215675 ps
CPU time 0.67 seconds
Started Jan 07 12:38:37 PM PST 24
Finished Jan 07 12:40:10 PM PST 24
Peak memory 200180 kb
Host smart-f5e4e61a-c3b9-4843-bf71-3676e91cdf29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813252302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.813252302
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3479376026
Short name T860
Test name
Test status
Simulation time 4266725531 ps
CPU time 5.48 seconds
Started Jan 07 12:38:32 PM PST 24
Finished Jan 07 12:39:37 PM PST 24
Peak memory 200660 kb
Host smart-c5371e1c-9d7e-4f3b-af2b-fcf0f94e8fac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479376026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.3479376026
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.852637225
Short name T56
Test name
Test status
Simulation time 614748127 ps
CPU time 3.63 seconds
Started Jan 07 12:38:30 PM PST 24
Finished Jan 07 12:39:46 PM PST 24
Peak memory 200760 kb
Host smart-d6a39b38-fcfd-4163-bbb0-417c8ded8ac6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852637225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.852637225
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1349140291
Short name T9
Test name
Test status
Simulation time 7961084205 ps
CPU time 11.18 seconds
Started Jan 07 12:38:31 PM PST 24
Finished Jan 07 12:39:45 PM PST 24
Peak memory 200740 kb
Host smart-ddd14e28-c3f4-48f5-884d-b59571d4796a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349140291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.1349140291
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1288179024
Short name T841
Test name
Test status
Simulation time 420859784 ps
CPU time 0.99 seconds
Started Jan 07 12:38:24 PM PST 24
Finished Jan 07 12:40:23 PM PST 24
Peak memory 200640 kb
Host smart-86f39b8b-ab1e-47d3-8571-f61d8896d185
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288179024 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.1288179024
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.406680408
Short name T854
Test name
Test status
Simulation time 316758847 ps
CPU time 1.39 seconds
Started Jan 07 12:38:21 PM PST 24
Finished Jan 07 12:40:33 PM PST 24
Peak memory 200368 kb
Host smart-48da2788-e223-4583-bf0e-3606ad1a6657
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406680408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.406680408
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1288018378
Short name T336
Test name
Test status
Simulation time 4614219422 ps
CPU time 12.02 seconds
Started Jan 07 12:38:23 PM PST 24
Finished Jan 07 12:39:53 PM PST 24
Peak memory 200580 kb
Host smart-6fe948b9-bf09-4579-ac45-afb5efbfce21
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288018378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.1288018378
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.4243330402
Short name T857
Test name
Test status
Simulation time 440707260 ps
CPU time 1.72 seconds
Started Jan 07 12:37:50 PM PST 24
Finished Jan 07 12:39:07 PM PST 24
Peak memory 200552 kb
Host smart-6f3dcd0a-0cae-4c89-ae34-2f94b19de027
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243330402 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.4243330402
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1440564591
Short name T846
Test name
Test status
Simulation time 403429308 ps
CPU time 1.55 seconds
Started Jan 07 12:37:54 PM PST 24
Finished Jan 07 12:39:40 PM PST 24
Peak memory 200492 kb
Host smart-6196fec3-d28b-46f1-89e0-16b1e9ecf5cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440564591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.1440564591
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1607194510
Short name T365
Test name
Test status
Simulation time 3963938454 ps
CPU time 9.38 seconds
Started Jan 07 12:38:31 PM PST 24
Finished Jan 07 12:39:41 PM PST 24
Peak memory 200712 kb
Host smart-6b6e46bb-77cd-400a-8468-0c5a59417139
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607194510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.1607194510
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2195659059
Short name T877
Test name
Test status
Simulation time 411593960 ps
CPU time 2.69 seconds
Started Jan 07 12:38:27 PM PST 24
Finished Jan 07 12:39:36 PM PST 24
Peak memory 200800 kb
Host smart-10f38c4e-6e66-44ab-a3a4-2ef02216d581
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195659059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.2195659059
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.716551274
Short name T843
Test name
Test status
Simulation time 353175755 ps
CPU time 1.53 seconds
Started Jan 07 12:37:52 PM PST 24
Finished Jan 07 12:39:08 PM PST 24
Peak memory 200552 kb
Host smart-83a82af9-7988-4653-afb4-1a4723dfa8e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716551274 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.716551274
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.2206924209
Short name T6
Test name
Test status
Simulation time 379781162 ps
CPU time 1.1 seconds
Started Jan 07 12:38:30 PM PST 24
Finished Jan 07 12:39:44 PM PST 24
Peak memory 200212 kb
Host smart-aa12c9e1-f9f3-442d-9287-6cadef0a0124
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206924209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.2206924209
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1621086065
Short name T360
Test name
Test status
Simulation time 2432220276 ps
CPU time 8.18 seconds
Started Jan 07 12:38:10 PM PST 24
Finished Jan 07 12:39:42 PM PST 24
Peak memory 200624 kb
Host smart-f1e3004d-44cb-4299-a585-6dff54ff3c4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621086065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.1621086065
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.878505407
Short name T54
Test name
Test status
Simulation time 335954631 ps
CPU time 1.92 seconds
Started Jan 07 12:38:06 PM PST 24
Finished Jan 07 12:39:29 PM PST 24
Peak memory 200764 kb
Host smart-c1b23cc4-e269-45a2-bacf-433f9e25b466
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878505407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.878505407
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.86244942
Short name T59
Test name
Test status
Simulation time 4138559175 ps
CPU time 6.27 seconds
Started Jan 07 12:38:24 PM PST 24
Finished Jan 07 12:39:35 PM PST 24
Peak memory 200748 kb
Host smart-4b104d42-b7b6-4f2c-b996-2ccdfc5ac6de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86244942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_intg
_err.86244942
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1284635703
Short name T2
Test name
Test status
Simulation time 583688060 ps
CPU time 1.01 seconds
Started Jan 07 12:37:58 PM PST 24
Finished Jan 07 12:39:14 PM PST 24
Peak memory 200612 kb
Host smart-e88f3303-d158-4f34-adab-61c314f1df10
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284635703 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.1284635703
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.323543245
Short name T72
Test name
Test status
Simulation time 475005551 ps
CPU time 1.02 seconds
Started Jan 07 12:38:31 PM PST 24
Finished Jan 07 12:39:48 PM PST 24
Peak memory 200544 kb
Host smart-3cfb8be0-2af1-4a2d-9b92-4ab969ed4c08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323543245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.323543245
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.1093252156
Short name T355
Test name
Test status
Simulation time 295450661 ps
CPU time 1.02 seconds
Started Jan 07 12:38:07 PM PST 24
Finished Jan 07 12:39:57 PM PST 24
Peak memory 200116 kb
Host smart-43178aed-4458-455d-9ab2-f846230be597
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093252156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.1093252156
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3506553000
Short name T863
Test name
Test status
Simulation time 462726055 ps
CPU time 2.19 seconds
Started Jan 07 12:38:07 PM PST 24
Finished Jan 07 12:39:21 PM PST 24
Peak memory 209020 kb
Host smart-4284398d-f4af-44e1-ae79-26ddeb6dd18f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506553000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.3506553000
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.25819009
Short name T619
Test name
Test status
Simulation time 169961076258 ps
CPU time 5.5 seconds
Started Jan 07 01:06:14 PM PST 24
Finished Jan 07 01:06:21 PM PST 24
Peak memory 200772 kb
Host smart-1c2248a3-e4aa-47df-ba1e-00f7a52d296a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25819009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gating
.25819009
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.2795780917
Short name T726
Test name
Test status
Simulation time 327593311018 ps
CPU time 142.38 seconds
Started Jan 07 01:06:11 PM PST 24
Finished Jan 07 01:08:35 PM PST 24
Peak memory 200836 kb
Host smart-2dedb35a-3eda-4f29-b5a4-1a2f76073c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795780917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.2795780917
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.2161763869
Short name T321
Test name
Test status
Simulation time 167296126002 ps
CPU time 45.18 seconds
Started Jan 07 01:06:05 PM PST 24
Finished Jan 07 01:06:53 PM PST 24
Peak memory 200904 kb
Host smart-06687752-fcd0-4fb7-a2d7-0c7e19b4b035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161763869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.2161763869
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.464010834
Short name T828
Test name
Test status
Simulation time 167846578532 ps
CPU time 64.15 seconds
Started Jan 07 01:06:07 PM PST 24
Finished Jan 07 01:07:13 PM PST 24
Peak memory 200808 kb
Host smart-2a67ba64-dcce-41be-9458-9c33108bb531
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=464010834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt
_fixed.464010834
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.3370114365
Short name T305
Test name
Test status
Simulation time 489911953580 ps
CPU time 284.85 seconds
Started Jan 07 01:06:11 PM PST 24
Finished Jan 07 01:10:58 PM PST 24
Peak memory 200872 kb
Host smart-247c0b4e-a8a5-42cb-907d-adfc46027be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370114365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.3370114365
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.1198915663
Short name T467
Test name
Test status
Simulation time 167174313622 ps
CPU time 65.88 seconds
Started Jan 07 01:05:56 PM PST 24
Finished Jan 07 01:07:11 PM PST 24
Peak memory 200832 kb
Host smart-43393f6e-49d6-4399-ab2b-fed6cb212a01
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198915663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.1198915663
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.565015247
Short name T719
Test name
Test status
Simulation time 491731242410 ps
CPU time 575.11 seconds
Started Jan 07 01:05:57 PM PST 24
Finished Jan 07 01:15:35 PM PST 24
Peak memory 200760 kb
Host smart-0ecf61ae-de0a-4c35-ad77-70225b5ffab5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565015247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.a
dc_ctrl_filters_wakeup_fixed.565015247
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.3596273292
Short name T436
Test name
Test status
Simulation time 71927972322 ps
CPU time 290.3 seconds
Started Jan 07 01:05:58 PM PST 24
Finished Jan 07 01:10:56 PM PST 24
Peak memory 201268 kb
Host smart-bb76033b-a1c8-4b6d-a9d8-6ae2f1f8b211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596273292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.3596273292
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.3595417613
Short name T627
Test name
Test status
Simulation time 42535156328 ps
CPU time 50.01 seconds
Started Jan 07 01:05:55 PM PST 24
Finished Jan 07 01:06:50 PM PST 24
Peak memory 200760 kb
Host smart-81b7803d-6bf8-4179-b6d3-3193463608b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595417613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.3595417613
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.392123121
Short name T153
Test name
Test status
Simulation time 5322315107 ps
CPU time 1.61 seconds
Started Jan 07 01:06:05 PM PST 24
Finished Jan 07 01:06:09 PM PST 24
Peak memory 200672 kb
Host smart-b6d45679-3727-4551-880c-07359f891fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392123121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.392123121
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.1567879798
Short name T42
Test name
Test status
Simulation time 7973386374 ps
CPU time 18.51 seconds
Started Jan 07 01:06:23 PM PST 24
Finished Jan 07 01:06:42 PM PST 24
Peak memory 216172 kb
Host smart-62cb108a-c33f-4652-b670-c050efe1b377
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567879798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.1567879798
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.3440098070
Short name T699
Test name
Test status
Simulation time 5714095316 ps
CPU time 13.34 seconds
Started Jan 07 01:05:54 PM PST 24
Finished Jan 07 01:06:10 PM PST 24
Peak memory 200740 kb
Host smart-0a9c48a2-b26e-4cf4-a4a6-c76d8ce46f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440098070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.3440098070
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.3946392058
Short name T538
Test name
Test status
Simulation time 28290871386 ps
CPU time 33.91 seconds
Started Jan 07 01:06:05 PM PST 24
Finished Jan 07 01:06:42 PM PST 24
Peak memory 200624 kb
Host smart-2f4cb83e-4f57-462e-9d0e-496eddd70a5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946392058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
3946392058
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.4112391119
Short name T801
Test name
Test status
Simulation time 19188077732 ps
CPU time 24.64 seconds
Started Jan 07 01:05:47 PM PST 24
Finished Jan 07 01:06:13 PM PST 24
Peak memory 209552 kb
Host smart-2168cb3f-2d97-446e-a5dd-922d2669e9aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112391119 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.4112391119
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.391637835
Short name T693
Test name
Test status
Simulation time 347666762 ps
CPU time 1.35 seconds
Started Jan 07 01:06:09 PM PST 24
Finished Jan 07 01:06:12 PM PST 24
Peak memory 200624 kb
Host smart-b7362870-30fc-4e14-9eeb-a24fc030b538
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391637835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.391637835
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.1454939579
Short name T169
Test name
Test status
Simulation time 500750699227 ps
CPU time 108.33 seconds
Started Jan 07 01:06:07 PM PST 24
Finished Jan 07 01:07:57 PM PST 24
Peak memory 200888 kb
Host smart-417d8582-bd3e-4044-bd76-3d242496bde7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454939579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.1454939579
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.3819516417
Short name T235
Test name
Test status
Simulation time 161934628467 ps
CPU time 42.54 seconds
Started Jan 07 01:05:48 PM PST 24
Finished Jan 07 01:06:32 PM PST 24
Peak memory 200840 kb
Host smart-50da9cd3-4186-4cc5-aed7-2dc8611b77e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819516417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.3819516417
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.3285524823
Short name T138
Test name
Test status
Simulation time 167430694798 ps
CPU time 375.67 seconds
Started Jan 07 01:06:05 PM PST 24
Finished Jan 07 01:12:23 PM PST 24
Peak memory 200892 kb
Host smart-cbf6f762-0807-43f2-abe3-8e101477457b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285524823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.3285524823
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.1366021726
Short name T50
Test name
Test status
Simulation time 167561349372 ps
CPU time 88.29 seconds
Started Jan 07 01:06:22 PM PST 24
Finished Jan 07 01:07:51 PM PST 24
Peak memory 200844 kb
Host smart-1f7ee9f5-6332-40cc-89b8-cfa64c7b4aff
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366021726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.1366021726
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.2761070446
Short name T447
Test name
Test status
Simulation time 324498853781 ps
CPU time 142.18 seconds
Started Jan 07 01:05:50 PM PST 24
Finished Jan 07 01:08:14 PM PST 24
Peak memory 200972 kb
Host smart-3584d4df-e9d2-4b53-9485-4cba3e4bdff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761070446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.2761070446
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.1190180900
Short name T650
Test name
Test status
Simulation time 495458110384 ps
CPU time 299.54 seconds
Started Jan 07 01:05:43 PM PST 24
Finished Jan 07 01:10:44 PM PST 24
Peak memory 200908 kb
Host smart-bddde02f-3882-453c-8070-949a3077ca66
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190180900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.1190180900
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.2225923406
Short name T211
Test name
Test status
Simulation time 497455727850 ps
CPU time 1240.01 seconds
Started Jan 07 01:06:04 PM PST 24
Finished Jan 07 01:26:47 PM PST 24
Peak memory 200876 kb
Host smart-36e5eb94-3f03-41f5-a883-14428ef5f3f1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225923406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.2225923406
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.2483164854
Short name T659
Test name
Test status
Simulation time 325934667115 ps
CPU time 743.08 seconds
Started Jan 07 01:06:12 PM PST 24
Finished Jan 07 01:18:37 PM PST 24
Peak memory 200844 kb
Host smart-a1413d8a-8a69-43e0-8ab4-dd83c904a16a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483164854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.2483164854
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.2706333470
Short name T563
Test name
Test status
Simulation time 93409095929 ps
CPU time 342.3 seconds
Started Jan 07 01:06:06 PM PST 24
Finished Jan 07 01:11:51 PM PST 24
Peak memory 201252 kb
Host smart-c46fd92b-9cc4-40fa-8b5b-f27fc28facd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706333470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.2706333470
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.3171157725
Short name T46
Test name
Test status
Simulation time 42517569788 ps
CPU time 26.84 seconds
Started Jan 07 01:05:58 PM PST 24
Finished Jan 07 01:06:28 PM PST 24
Peak memory 200632 kb
Host smart-520853d6-42c5-4e3f-a779-0a12f7f8c137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171157725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.3171157725
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.1295321022
Short name T422
Test name
Test status
Simulation time 2639382709 ps
CPU time 7.51 seconds
Started Jan 07 01:06:13 PM PST 24
Finished Jan 07 01:06:22 PM PST 24
Peak memory 200648 kb
Host smart-82a45fb6-eea1-49e7-9188-426a8ff73069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295321022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.1295321022
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.3862959235
Short name T43
Test name
Test status
Simulation time 7707961629 ps
CPU time 5.24 seconds
Started Jan 07 01:05:59 PM PST 24
Finished Jan 07 01:06:07 PM PST 24
Peak memory 217196 kb
Host smart-c82e8961-8eb4-41d8-b790-e450c7f2413b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862959235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.3862959235
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.151616431
Short name T692
Test name
Test status
Simulation time 5805617688 ps
CPU time 13.51 seconds
Started Jan 07 01:05:52 PM PST 24
Finished Jan 07 01:06:07 PM PST 24
Peak memory 200700 kb
Host smart-5fcdd86a-f47d-4bb2-b829-1f3c7024d687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151616431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.151616431
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.2065832784
Short name T798
Test name
Test status
Simulation time 4097990660 ps
CPU time 2.27 seconds
Started Jan 07 01:05:55 PM PST 24
Finished Jan 07 01:06:01 PM PST 24
Peak memory 200760 kb
Host smart-30564e41-ed36-4c7e-8b65-201ae9b21119
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065832784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
2065832784
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.3427573365
Short name T181
Test name
Test status
Simulation time 330432510768 ps
CPU time 233.97 seconds
Started Jan 07 01:05:55 PM PST 24
Finished Jan 07 01:09:52 PM PST 24
Peak memory 209660 kb
Host smart-ea6880b3-1db3-45b0-8be9-04058cb7357b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427573365 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.3427573365
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.1629601965
Short name T824
Test name
Test status
Simulation time 538045411 ps
CPU time 0.98 seconds
Started Jan 07 01:06:23 PM PST 24
Finished Jan 07 01:06:25 PM PST 24
Peak memory 200672 kb
Host smart-ccb53405-623c-4c70-98b7-6388ffd1b45b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629601965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.1629601965
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.872456341
Short name T283
Test name
Test status
Simulation time 163004512780 ps
CPU time 167.13 seconds
Started Jan 07 01:06:21 PM PST 24
Finished Jan 07 01:09:09 PM PST 24
Peak memory 200892 kb
Host smart-7b1d1f16-a0ad-480f-b876-e8029be78466
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872456341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gati
ng.872456341
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.1319021904
Short name T771
Test name
Test status
Simulation time 496084841302 ps
CPU time 644.6 seconds
Started Jan 07 01:06:27 PM PST 24
Finished Jan 07 01:17:15 PM PST 24
Peak memory 200796 kb
Host smart-ff8d56d9-d221-4944-9ddb-e6aa633c9363
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319021904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.1319021904
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.2572674886
Short name T105
Test name
Test status
Simulation time 327390924994 ps
CPU time 206.54 seconds
Started Jan 07 01:06:13 PM PST 24
Finished Jan 07 01:09:41 PM PST 24
Peak memory 200876 kb
Host smart-9abb91c4-ef05-4598-899e-cf784541de72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572674886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.2572674886
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.514537488
Short name T807
Test name
Test status
Simulation time 491525119520 ps
CPU time 293.75 seconds
Started Jan 07 01:06:24 PM PST 24
Finished Jan 07 01:11:20 PM PST 24
Peak memory 200868 kb
Host smart-a2dacb43-e146-4fb3-9332-14619d348128
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=514537488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fixe
d.514537488
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.2578007310
Short name T209
Test name
Test status
Simulation time 333749083524 ps
CPU time 683.25 seconds
Started Jan 07 01:06:19 PM PST 24
Finished Jan 07 01:17:43 PM PST 24
Peak memory 200912 kb
Host smart-15c03113-1d1d-462f-80f4-e6fa6850bc8e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578007310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.2578007310
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.1752577369
Short name T568
Test name
Test status
Simulation time 162077906378 ps
CPU time 96.64 seconds
Started Jan 07 01:06:20 PM PST 24
Finished Jan 07 01:07:58 PM PST 24
Peak memory 200996 kb
Host smart-1116c593-f7a3-4c48-9294-d20e980323b3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752577369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.1752577369
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.1688071058
Short name T583
Test name
Test status
Simulation time 135339880498 ps
CPU time 388.83 seconds
Started Jan 07 01:06:33 PM PST 24
Finished Jan 07 01:13:20 PM PST 24
Peak memory 201300 kb
Host smart-f61e6047-affa-4656-9f45-0be1e8e457e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688071058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.1688071058
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.260879698
Short name T522
Test name
Test status
Simulation time 44900629389 ps
CPU time 54.7 seconds
Started Jan 07 01:06:24 PM PST 24
Finished Jan 07 01:07:21 PM PST 24
Peak memory 200744 kb
Host smart-d9361f80-a7d8-47ee-baa1-4407ceed1ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260879698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.260879698
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.3962479162
Short name T656
Test name
Test status
Simulation time 3149537825 ps
CPU time 2.4 seconds
Started Jan 07 01:06:19 PM PST 24
Finished Jan 07 01:06:23 PM PST 24
Peak memory 200740 kb
Host smart-843902dc-0e92-443c-b621-bf9b69b6bb11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962479162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.3962479162
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.3026305093
Short name T410
Test name
Test status
Simulation time 6062475276 ps
CPU time 2.17 seconds
Started Jan 07 01:06:20 PM PST 24
Finished Jan 07 01:06:24 PM PST 24
Peak memory 200696 kb
Host smart-a1a7785d-38ce-4ea9-b2d3-bc779ad31dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026305093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.3026305093
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.601563243
Short name T741
Test name
Test status
Simulation time 295731887 ps
CPU time 1.34 seconds
Started Jan 07 01:06:41 PM PST 24
Finished Jan 07 01:06:56 PM PST 24
Peak memory 200692 kb
Host smart-18afd5e8-9119-4d7f-92b4-0e5bd9a57657
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601563243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.601563243
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.2975522938
Short name T237
Test name
Test status
Simulation time 503209104134 ps
CPU time 351.84 seconds
Started Jan 07 01:06:22 PM PST 24
Finished Jan 07 01:12:15 PM PST 24
Peak memory 200936 kb
Host smart-adf292cf-2c97-4a73-8e2e-b8ad57faa253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975522938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.2975522938
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.3630809405
Short name T199
Test name
Test status
Simulation time 164888721460 ps
CPU time 95.4 seconds
Started Jan 07 01:06:20 PM PST 24
Finished Jan 07 01:07:57 PM PST 24
Peak memory 200760 kb
Host smart-555a88ea-a336-4a1f-bffa-fc1830098630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630809405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.3630809405
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.187117551
Short name T158
Test name
Test status
Simulation time 329642593532 ps
CPU time 123.25 seconds
Started Jan 07 01:06:21 PM PST 24
Finished Jan 07 01:08:25 PM PST 24
Peak memory 200816 kb
Host smart-c34011a9-b4d3-437c-9279-909431114646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187117551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.187117551
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.48791719
Short name T660
Test name
Test status
Simulation time 486568808300 ps
CPU time 530.07 seconds
Started Jan 07 01:06:17 PM PST 24
Finished Jan 07 01:15:08 PM PST 24
Peak memory 200864 kb
Host smart-f1153159-c39f-40b8-867d-f3f430767e90
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=48791719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fixed
.48791719
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.3158288219
Short name T452
Test name
Test status
Simulation time 168276140326 ps
CPU time 107.02 seconds
Started Jan 07 01:06:16 PM PST 24
Finished Jan 07 01:08:05 PM PST 24
Peak memory 200912 kb
Host smart-bb984113-51a7-4590-b831-0b807b128fd9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158288219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.3158288219
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.717268646
Short name T426
Test name
Test status
Simulation time 74589474303 ps
CPU time 415.32 seconds
Started Jan 07 01:06:20 PM PST 24
Finished Jan 07 01:13:17 PM PST 24
Peak memory 201376 kb
Host smart-d9dd0854-8f7f-4224-9846-d9d1c2c4c0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717268646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.717268646
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.374167847
Short name T506
Test name
Test status
Simulation time 35129635230 ps
CPU time 5.82 seconds
Started Jan 07 01:06:26 PM PST 24
Finished Jan 07 01:06:35 PM PST 24
Peak memory 200688 kb
Host smart-6ec5db7e-ca49-4599-a0dd-1f8ee8a2e74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374167847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.374167847
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.3453357513
Short name T483
Test name
Test status
Simulation time 3315859301 ps
CPU time 2.16 seconds
Started Jan 07 01:06:23 PM PST 24
Finished Jan 07 01:06:26 PM PST 24
Peak memory 200700 kb
Host smart-9f3ad701-efed-4b1e-9337-a07073d3bdda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453357513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.3453357513
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.2983451038
Short name T839
Test name
Test status
Simulation time 5743290113 ps
CPU time 12.81 seconds
Started Jan 07 01:06:24 PM PST 24
Finished Jan 07 01:06:39 PM PST 24
Peak memory 200692 kb
Host smart-2f52b91e-482e-4dfd-860a-cee755d86b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983451038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.2983451038
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.2446799278
Short name T802
Test name
Test status
Simulation time 485864000 ps
CPU time 1.25 seconds
Started Jan 07 01:06:43 PM PST 24
Finished Jan 07 01:07:00 PM PST 24
Peak memory 200560 kb
Host smart-b348dece-6fcb-4a73-a9f0-01c9fe00801e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446799278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.2446799278
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.1477893295
Short name T148
Test name
Test status
Simulation time 326007842747 ps
CPU time 207.82 seconds
Started Jan 07 01:06:39 PM PST 24
Finished Jan 07 01:10:21 PM PST 24
Peak memory 200760 kb
Host smart-9b947d89-1899-4b81-849a-6692452baf30
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477893295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.1477893295
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.1718018258
Short name T667
Test name
Test status
Simulation time 166436527861 ps
CPU time 129.05 seconds
Started Jan 07 01:06:28 PM PST 24
Finished Jan 07 01:08:49 PM PST 24
Peak memory 200896 kb
Host smart-8fe6de59-ac85-4c4b-8f47-e02d5f11f7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718018258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.1718018258
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.1771576794
Short name T755
Test name
Test status
Simulation time 161481598792 ps
CPU time 176.87 seconds
Started Jan 07 01:06:23 PM PST 24
Finished Jan 07 01:09:21 PM PST 24
Peak memory 200960 kb
Host smart-dfb5ebff-69b3-4fda-b140-77c45b459423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771576794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.1771576794
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.2334392218
Short name T429
Test name
Test status
Simulation time 166155632225 ps
CPU time 200.54 seconds
Started Jan 07 01:06:27 PM PST 24
Finished Jan 07 01:09:51 PM PST 24
Peak memory 200836 kb
Host smart-39351797-e0f8-4d60-96a0-f31c0e3195ba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334392218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.2334392218
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.3305327454
Short name T270
Test name
Test status
Simulation time 160612287965 ps
CPU time 344.4 seconds
Started Jan 07 01:06:14 PM PST 24
Finished Jan 07 01:12:00 PM PST 24
Peak memory 200920 kb
Host smart-d3bb9029-0252-43c2-b17f-a40c408b82b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305327454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.3305327454
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.655663164
Short name T628
Test name
Test status
Simulation time 499315696094 ps
CPU time 598.02 seconds
Started Jan 07 01:06:35 PM PST 24
Finished Jan 07 01:16:50 PM PST 24
Peak memory 200724 kb
Host smart-1cd06b93-3009-4808-aee4-9d6509366c5e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=655663164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fixe
d.655663164
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.2508963029
Short name T559
Test name
Test status
Simulation time 339083695076 ps
CPU time 202.58 seconds
Started Jan 07 01:06:27 PM PST 24
Finished Jan 07 01:09:53 PM PST 24
Peak memory 200844 kb
Host smart-d7da807f-91bc-449f-82af-fb79c1b1f20c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508963029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.2508963029
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.3067774944
Short name T598
Test name
Test status
Simulation time 494952912360 ps
CPU time 482.65 seconds
Started Jan 07 01:06:19 PM PST 24
Finished Jan 07 01:14:23 PM PST 24
Peak memory 200852 kb
Host smart-38794134-ded8-4b3d-a967-55f4fa1162f1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067774944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.3067774944
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.2837279757
Short name T428
Test name
Test status
Simulation time 118999049749 ps
CPU time 489.18 seconds
Started Jan 07 01:06:47 PM PST 24
Finished Jan 07 01:15:10 PM PST 24
Peak memory 201136 kb
Host smart-282d1d87-555d-4a16-a0d1-b77de6121ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837279757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.2837279757
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.1307131073
Short name T579
Test name
Test status
Simulation time 36346281714 ps
CPU time 39.76 seconds
Started Jan 07 01:06:32 PM PST 24
Finished Jan 07 01:07:30 PM PST 24
Peak memory 200680 kb
Host smart-734a5c4d-4458-4d50-92fd-12f4786c70ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307131073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.1307131073
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.2500473518
Short name T439
Test name
Test status
Simulation time 4394476529 ps
CPU time 3.3 seconds
Started Jan 07 01:06:22 PM PST 24
Finished Jan 07 01:06:27 PM PST 24
Peak memory 200716 kb
Host smart-ae4d7e61-5390-403c-9145-0c689f1db1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500473518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.2500473518
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.4092836150
Short name T781
Test name
Test status
Simulation time 5960280926 ps
CPU time 7.18 seconds
Started Jan 07 01:06:22 PM PST 24
Finished Jan 07 01:06:31 PM PST 24
Peak memory 200748 kb
Host smart-fd43b836-dfae-499a-adc0-4e5470335f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092836150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.4092836150
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.3355929907
Short name T662
Test name
Test status
Simulation time 311760932 ps
CPU time 1.32 seconds
Started Jan 07 01:06:33 PM PST 24
Finished Jan 07 01:06:52 PM PST 24
Peak memory 200692 kb
Host smart-b277a94c-2c20-409a-ab6f-b5ad5000d41d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355929907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.3355929907
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.4103966516
Short name T203
Test name
Test status
Simulation time 326990080818 ps
CPU time 718.83 seconds
Started Jan 07 01:06:43 PM PST 24
Finished Jan 07 01:18:57 PM PST 24
Peak memory 200704 kb
Host smart-38c76331-d5f2-473a-9811-2b35a3073ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103966516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.4103966516
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.2678171558
Short name T791
Test name
Test status
Simulation time 490664276593 ps
CPU time 290.97 seconds
Started Jan 07 01:06:33 PM PST 24
Finished Jan 07 01:11:42 PM PST 24
Peak memory 200864 kb
Host smart-031df7db-6dc0-4a79-8075-54d6b9e6efa1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678171558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.2678171558
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.4058733959
Short name T575
Test name
Test status
Simulation time 163311007814 ps
CPU time 302.44 seconds
Started Jan 07 01:06:32 PM PST 24
Finished Jan 07 01:11:53 PM PST 24
Peak memory 200864 kb
Host smart-9ca611d6-cf33-4abf-8663-2db884c467e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058733959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.4058733959
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.3603207466
Short name T821
Test name
Test status
Simulation time 162966664283 ps
CPU time 163.63 seconds
Started Jan 07 01:06:26 PM PST 24
Finished Jan 07 01:09:14 PM PST 24
Peak memory 200864 kb
Host smart-69bca604-6903-4bc6-b196-1866f7dc88d0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603207466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.3603207466
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.4187664228
Short name T645
Test name
Test status
Simulation time 333753704358 ps
CPU time 194.69 seconds
Started Jan 07 01:06:28 PM PST 24
Finished Jan 07 01:09:55 PM PST 24
Peak memory 200956 kb
Host smart-0177ec57-c3d2-4d44-b0ae-4eb64ebaedfd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187664228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.4187664228
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.2873747940
Short name T711
Test name
Test status
Simulation time 21940932206 ps
CPU time 28.9 seconds
Started Jan 07 01:06:40 PM PST 24
Finished Jan 07 01:07:23 PM PST 24
Peak memory 200688 kb
Host smart-1ffe670d-619e-4ff4-813e-40a53e44fe73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873747940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.2873747940
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.1409766677
Short name T734
Test name
Test status
Simulation time 4705907713 ps
CPU time 3.66 seconds
Started Jan 07 01:06:48 PM PST 24
Finished Jan 07 01:07:06 PM PST 24
Peak memory 200504 kb
Host smart-7c86beab-cd85-4a9d-86f3-ef43a69911f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409766677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.1409766677
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.3626187982
Short name T525
Test name
Test status
Simulation time 5912457069 ps
CPU time 4.3 seconds
Started Jan 07 01:06:43 PM PST 24
Finished Jan 07 01:07:03 PM PST 24
Peak memory 200496 kb
Host smart-137b780e-4a26-4784-bdb9-fe071dee0bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626187982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.3626187982
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.2549282463
Short name T466
Test name
Test status
Simulation time 189071346513 ps
CPU time 540.85 seconds
Started Jan 07 01:06:25 PM PST 24
Finished Jan 07 01:15:28 PM PST 24
Peak memory 209484 kb
Host smart-4f662971-81d0-47fd-9751-d570e0d9e437
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549282463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.2549282463
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.902582987
Short name T275
Test name
Test status
Simulation time 39125446286 ps
CPU time 83.1 seconds
Started Jan 07 01:06:30 PM PST 24
Finished Jan 07 01:08:10 PM PST 24
Peak memory 217136 kb
Host smart-e66f8145-ef27-4901-8039-fbf95c4e69e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902582987 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.902582987
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.2590862346
Short name T407
Test name
Test status
Simulation time 471809355 ps
CPU time 1.02 seconds
Started Jan 07 01:06:42 PM PST 24
Finished Jan 07 01:06:57 PM PST 24
Peak memory 200696 kb
Host smart-f8f63ab1-9e0e-45f1-908c-cb9ac0b16c70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590862346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.2590862346
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.1039696491
Short name T200
Test name
Test status
Simulation time 160622130782 ps
CPU time 141.91 seconds
Started Jan 07 01:06:34 PM PST 24
Finished Jan 07 01:09:13 PM PST 24
Peak memory 200916 kb
Host smart-655d19b5-a161-48d8-ad56-1bcde076e20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039696491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.1039696491
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.2236768379
Short name T614
Test name
Test status
Simulation time 331088477541 ps
CPU time 745.83 seconds
Started Jan 07 01:06:33 PM PST 24
Finished Jan 07 01:19:17 PM PST 24
Peak memory 200964 kb
Host smart-827d2d14-2c8a-4810-b870-2dcee19db7bb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236768379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.2236768379
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.2384898366
Short name T549
Test name
Test status
Simulation time 482871422995 ps
CPU time 1152.99 seconds
Started Jan 07 01:08:00 PM PST 24
Finished Jan 07 01:27:15 PM PST 24
Peak memory 200472 kb
Host smart-133a7abf-e5a4-4942-a7b2-930beea651bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384898366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.2384898366
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.3432787165
Short name T438
Test name
Test status
Simulation time 492185966675 ps
CPU time 269.08 seconds
Started Jan 07 01:06:32 PM PST 24
Finished Jan 07 01:11:20 PM PST 24
Peak memory 200916 kb
Host smart-49fc7300-e695-4401-8896-6bf660d16e29
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432787165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.3432787165
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.2716884504
Short name T151
Test name
Test status
Simulation time 166974121113 ps
CPU time 189.58 seconds
Started Jan 07 01:06:33 PM PST 24
Finished Jan 07 01:10:00 PM PST 24
Peak memory 200848 kb
Host smart-0457f619-029d-4aac-b05b-7a2d7bc05f76
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716884504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.2716884504
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.2525534165
Short name T179
Test name
Test status
Simulation time 133070033105 ps
CPU time 680.4 seconds
Started Jan 07 01:06:34 PM PST 24
Finished Jan 07 01:18:11 PM PST 24
Peak memory 201352 kb
Host smart-cb7e2e2e-3362-4bc6-9124-fe475040ea62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525534165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.2525534165
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.467643719
Short name T649
Test name
Test status
Simulation time 34530010012 ps
CPU time 74.18 seconds
Started Jan 07 01:06:38 PM PST 24
Finished Jan 07 01:08:07 PM PST 24
Peak memory 200672 kb
Host smart-190bce2e-69e8-4df2-b758-4affd5b832df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467643719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.467643719
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.3155613936
Short name T777
Test name
Test status
Simulation time 3134768279 ps
CPU time 2.16 seconds
Started Jan 07 01:06:43 PM PST 24
Finished Jan 07 01:07:01 PM PST 24
Peak memory 200764 kb
Host smart-c0ea3c25-960b-4588-89cb-6ac20e864451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155613936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.3155613936
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.2741334205
Short name T491
Test name
Test status
Simulation time 6202893635 ps
CPU time 14.36 seconds
Started Jan 07 01:06:31 PM PST 24
Finished Jan 07 01:07:04 PM PST 24
Peak memory 200656 kb
Host smart-66ac3b9e-2da0-4f34-89e6-d13821fe7876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741334205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.2741334205
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.2984592441
Short name T696
Test name
Test status
Simulation time 324472408325 ps
CPU time 236.49 seconds
Started Jan 07 01:06:35 PM PST 24
Finished Jan 07 01:10:49 PM PST 24
Peak memory 200916 kb
Host smart-acc1c185-47c2-4dc1-9c2a-13d3095a9152
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984592441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.2984592441
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.199396915
Short name T784
Test name
Test status
Simulation time 517098066 ps
CPU time 1.8 seconds
Started Jan 07 01:06:31 PM PST 24
Finished Jan 07 01:06:52 PM PST 24
Peak memory 200680 kb
Host smart-fb0e9873-5c75-403e-bc23-6c284ab67c01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199396915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.199396915
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.2277315295
Short name T97
Test name
Test status
Simulation time 384846118998 ps
CPU time 447.42 seconds
Started Jan 07 01:06:41 PM PST 24
Finished Jan 07 01:14:22 PM PST 24
Peak memory 200868 kb
Host smart-e8da2ac5-ad75-4ce8-88d4-4ca42f470e41
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277315295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.2277315295
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.1085313971
Short name T307
Test name
Test status
Simulation time 167739773015 ps
CPU time 202.41 seconds
Started Jan 07 01:06:36 PM PST 24
Finished Jan 07 01:10:15 PM PST 24
Peak memory 200916 kb
Host smart-4e234d3b-4ce3-4583-a932-7c8157a6820c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085313971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.1085313971
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.2184639415
Short name T382
Test name
Test status
Simulation time 491751379492 ps
CPU time 1129.48 seconds
Started Jan 07 01:08:03 PM PST 24
Finished Jan 07 01:26:54 PM PST 24
Peak memory 200460 kb
Host smart-f0c7dc69-fe60-463e-b3b2-95c3c703a2af
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184639415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.2184639415
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.559028009
Short name T294
Test name
Test status
Simulation time 333409941405 ps
CPU time 733.97 seconds
Started Jan 07 01:06:34 PM PST 24
Finished Jan 07 01:19:07 PM PST 24
Peak memory 200872 kb
Host smart-b92b0252-1281-4083-99ba-593bc3552d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559028009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.559028009
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.1032186293
Short name T663
Test name
Test status
Simulation time 490349264942 ps
CPU time 300.42 seconds
Started Jan 07 01:06:24 PM PST 24
Finished Jan 07 01:11:25 PM PST 24
Peak memory 200884 kb
Host smart-0141d736-d5f0-4b0b-bedc-bb5dc770ffc6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032186293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.1032186293
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.1899572953
Short name T636
Test name
Test status
Simulation time 164291535551 ps
CPU time 355.12 seconds
Started Jan 07 01:06:46 PM PST 24
Finished Jan 07 01:12:56 PM PST 24
Peak memory 200876 kb
Host smart-3933b882-b40a-4f80-90e1-cb05bcfda378
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899572953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.1899572953
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.3918635634
Short name T342
Test name
Test status
Simulation time 111832378298 ps
CPU time 558.73 seconds
Started Jan 07 01:06:28 PM PST 24
Finished Jan 07 01:15:59 PM PST 24
Peak memory 201340 kb
Host smart-05aed60f-ca5c-4f67-ba3d-ef70d6bb0931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918635634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.3918635634
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.1511634718
Short name T814
Test name
Test status
Simulation time 28972388795 ps
CPU time 22.58 seconds
Started Jan 07 01:08:02 PM PST 24
Finished Jan 07 01:08:27 PM PST 24
Peak memory 200300 kb
Host smart-8e85120d-47aa-4441-8512-e89691640317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511634718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.1511634718
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.3037608454
Short name T837
Test name
Test status
Simulation time 3528672306 ps
CPU time 2.75 seconds
Started Jan 07 01:06:33 PM PST 24
Finished Jan 07 01:06:53 PM PST 24
Peak memory 200764 kb
Host smart-f9f65e42-d7a5-4a77-9b29-e37cc9b1e2a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037608454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.3037608454
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.3152278220
Short name T408
Test name
Test status
Simulation time 5713554035 ps
CPU time 13.56 seconds
Started Jan 07 01:06:29 PM PST 24
Finished Jan 07 01:06:55 PM PST 24
Peak memory 200488 kb
Host smart-b85703b9-e4e3-4893-8c98-c75571573285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152278220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.3152278220
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.1205256018
Short name T323
Test name
Test status
Simulation time 77931964240 ps
CPU time 58.32 seconds
Started Jan 07 01:06:34 PM PST 24
Finished Jan 07 01:07:51 PM PST 24
Peak memory 209428 kb
Host smart-bbe7570b-936b-4e63-a12f-baf98931983e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205256018 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.1205256018
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.38292748
Short name T414
Test name
Test status
Simulation time 550860052 ps
CPU time 0.91 seconds
Started Jan 07 01:06:34 PM PST 24
Finished Jan 07 01:06:54 PM PST 24
Peak memory 200700 kb
Host smart-d4550e3f-a1c1-4f8e-8e8c-9d67bf6bccaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38292748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.38292748
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.1804748854
Short name T757
Test name
Test status
Simulation time 389794846048 ps
CPU time 207.69 seconds
Started Jan 07 01:06:45 PM PST 24
Finished Jan 07 01:10:26 PM PST 24
Peak memory 200684 kb
Host smart-efb6f2dd-2666-41bc-9e21-d8f15c5e2ccd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804748854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.1804748854
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.3879552918
Short name T205
Test name
Test status
Simulation time 324332565293 ps
CPU time 748.38 seconds
Started Jan 07 01:06:43 PM PST 24
Finished Jan 07 01:19:27 PM PST 24
Peak memory 200720 kb
Host smart-e3aeefe4-eb8b-46a6-8c86-7c88c94c660f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879552918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.3879552918
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.4145205749
Short name T581
Test name
Test status
Simulation time 482960338177 ps
CPU time 384.8 seconds
Started Jan 07 01:06:35 PM PST 24
Finished Jan 07 01:13:18 PM PST 24
Peak memory 200660 kb
Host smart-c104409d-6cd5-4298-85d1-6c7ed6cf0f28
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145205749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.4145205749
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.2027421227
Short name T232
Test name
Test status
Simulation time 329012536869 ps
CPU time 350.07 seconds
Started Jan 07 01:06:33 PM PST 24
Finished Jan 07 01:12:41 PM PST 24
Peak memory 201012 kb
Host smart-410a6ead-a522-40a5-a023-b14308f0f902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027421227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.2027421227
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.1157224287
Short name T423
Test name
Test status
Simulation time 326073058304 ps
CPU time 775.26 seconds
Started Jan 07 01:06:43 PM PST 24
Finished Jan 07 01:19:54 PM PST 24
Peak memory 200248 kb
Host smart-eca128ee-2eb6-4672-9ddb-0eed69bd3755
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157224287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.1157224287
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.986051439
Short name T420
Test name
Test status
Simulation time 171549156590 ps
CPU time 95.16 seconds
Started Jan 07 01:06:36 PM PST 24
Finished Jan 07 01:08:26 PM PST 24
Peak memory 200872 kb
Host smart-0ce213ff-4f95-4091-9e68-d1999698e15a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986051439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_
wakeup.986051439
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.3796280562
Short name T510
Test name
Test status
Simulation time 168217986743 ps
CPU time 96.74 seconds
Started Jan 07 01:06:43 PM PST 24
Finished Jan 07 01:08:35 PM PST 24
Peak memory 200832 kb
Host smart-17dab5ec-21eb-489b-a360-96ea4ba9a53f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796280562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.3796280562
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.4238858541
Short name T560
Test name
Test status
Simulation time 57342766872 ps
CPU time 358 seconds
Started Jan 07 01:06:26 PM PST 24
Finished Jan 07 01:12:28 PM PST 24
Peak memory 201228 kb
Host smart-94a66df2-8202-46f6-82b9-8c6ced50bb38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238858541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.4238858541
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.6691472
Short name T524
Test name
Test status
Simulation time 40502427188 ps
CPU time 87.53 seconds
Started Jan 07 01:06:26 PM PST 24
Finished Jan 07 01:07:57 PM PST 24
Peak memory 200656 kb
Host smart-0df48bc6-2c45-4464-a3fc-d6146e13764d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6691472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.6691472
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.1198127651
Short name T480
Test name
Test status
Simulation time 4411978583 ps
CPU time 5.58 seconds
Started Jan 07 01:06:33 PM PST 24
Finished Jan 07 01:06:56 PM PST 24
Peak memory 200700 kb
Host smart-91c015d7-e347-4817-b62a-7b971c32bd0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198127651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.1198127651
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.1334657710
Short name T486
Test name
Test status
Simulation time 6045500390 ps
CPU time 4.42 seconds
Started Jan 07 01:06:28 PM PST 24
Finished Jan 07 01:06:45 PM PST 24
Peak memory 200696 kb
Host smart-4f09f388-331d-4ed5-9110-397181b3016f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334657710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.1334657710
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.3430617275
Short name T753
Test name
Test status
Simulation time 457696656792 ps
CPU time 950.66 seconds
Started Jan 07 01:06:35 PM PST 24
Finished Jan 07 01:22:42 PM PST 24
Peak memory 201044 kb
Host smart-61a3820d-2d79-40f6-a905-47815ab8764f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430617275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.3430617275
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.460427533
Short name T708
Test name
Test status
Simulation time 56867424214 ps
CPU time 130.03 seconds
Started Jan 07 01:06:39 PM PST 24
Finished Jan 07 01:09:03 PM PST 24
Peak memory 215204 kb
Host smart-fb93e138-444f-4d8b-906a-d413a929a6d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460427533 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.460427533
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.3805658764
Short name T587
Test name
Test status
Simulation time 533049986 ps
CPU time 0.91 seconds
Started Jan 07 01:06:37 PM PST 24
Finished Jan 07 01:06:52 PM PST 24
Peak memory 200684 kb
Host smart-25715499-339e-494a-8423-893f2bf4ff10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805658764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.3805658764
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.3023826567
Short name T574
Test name
Test status
Simulation time 325125945628 ps
CPU time 172.26 seconds
Started Jan 07 01:06:42 PM PST 24
Finished Jan 07 01:09:50 PM PST 24
Peak memory 200876 kb
Host smart-ea68452d-b7da-4cb0-b1fb-5e65a03ae1fc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023826567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.3023826567
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.3212999815
Short name T335
Test name
Test status
Simulation time 322066560643 ps
CPU time 552.13 seconds
Started Jan 07 01:06:33 PM PST 24
Finished Jan 07 01:16:03 PM PST 24
Peak memory 200888 kb
Host smart-ada418b4-b05e-4247-b44d-0afe7a8e4392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212999815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.3212999815
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.1890813531
Short name T254
Test name
Test status
Simulation time 488234106458 ps
CPU time 358.25 seconds
Started Jan 07 01:06:31 PM PST 24
Finished Jan 07 01:12:49 PM PST 24
Peak memory 201004 kb
Host smart-4f73d2c6-7060-4ba4-b52a-16c2db077fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890813531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.1890813531
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.2000262288
Short name T387
Test name
Test status
Simulation time 330371088168 ps
CPU time 220.91 seconds
Started Jan 07 01:06:25 PM PST 24
Finished Jan 07 01:10:09 PM PST 24
Peak memory 200876 kb
Host smart-1b041a1d-ee6a-46da-8ad9-db4b76abcc83
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000262288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.2000262288
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.3419289936
Short name T531
Test name
Test status
Simulation time 167566229795 ps
CPU time 184.79 seconds
Started Jan 07 01:06:37 PM PST 24
Finished Jan 07 01:09:58 PM PST 24
Peak memory 200652 kb
Host smart-af539515-821a-4f6e-a430-5df47ebf573f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419289936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.3419289936
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.4066362587
Short name T449
Test name
Test status
Simulation time 164171736238 ps
CPU time 99.66 seconds
Started Jan 07 01:06:39 PM PST 24
Finished Jan 07 01:08:33 PM PST 24
Peak memory 200664 kb
Host smart-28ead04d-ea51-4d54-951a-bd0f1879a191
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066362587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.4066362587
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.3014913494
Short name T409
Test name
Test status
Simulation time 166691444427 ps
CPU time 94.32 seconds
Started Jan 07 01:08:02 PM PST 24
Finished Jan 07 01:09:37 PM PST 24
Peak memory 200520 kb
Host smart-0c3bc51e-c367-492d-9304-38643c75452a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014913494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.3014913494
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.4267566341
Short name T721
Test name
Test status
Simulation time 70045850578 ps
CPU time 339.55 seconds
Started Jan 07 01:06:35 PM PST 24
Finished Jan 07 01:12:32 PM PST 24
Peak memory 201296 kb
Host smart-b23ab5c0-6d5a-49af-8377-6fcf73a06a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267566341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.4267566341
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.1175137415
Short name T829
Test name
Test status
Simulation time 33114773395 ps
CPU time 13.64 seconds
Started Jan 07 01:06:46 PM PST 24
Finished Jan 07 01:07:12 PM PST 24
Peak memory 200764 kb
Host smart-7dbfce2a-49d0-4138-9e65-b81cd3591ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175137415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.1175137415
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.2091985382
Short name T730
Test name
Test status
Simulation time 4570712912 ps
CPU time 11.76 seconds
Started Jan 07 01:06:48 PM PST 24
Finished Jan 07 01:07:14 PM PST 24
Peak memory 200692 kb
Host smart-08a66b7b-5577-4bc3-99a9-6eb430b2b640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091985382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.2091985382
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.421424013
Short name T787
Test name
Test status
Simulation time 6000250369 ps
CPU time 2.95 seconds
Started Jan 07 01:08:03 PM PST 24
Finished Jan 07 01:08:07 PM PST 24
Peak memory 200296 kb
Host smart-e4c04161-8775-4a67-9387-e43fe1d913ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421424013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.421424013
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.1809421626
Short name T389
Test name
Test status
Simulation time 34659691223 ps
CPU time 76.47 seconds
Started Jan 07 01:06:36 PM PST 24
Finished Jan 07 01:08:09 PM PST 24
Peak memory 200768 kb
Host smart-4b404d80-77f0-4a23-ad17-455990aa6ec6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809421626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.1809421626
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.2476065911
Short name T85
Test name
Test status
Simulation time 140507373284 ps
CPU time 163.74 seconds
Started Jan 07 01:07:45 PM PST 24
Finished Jan 07 01:10:37 PM PST 24
Peak memory 199556 kb
Host smart-ccf44898-6416-4ef6-a0d9-4d38e563ea10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476065911 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.2476065911
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.3888165381
Short name T680
Test name
Test status
Simulation time 510261606 ps
CPU time 0.81 seconds
Started Jan 07 01:06:31 PM PST 24
Finished Jan 07 01:06:51 PM PST 24
Peak memory 200636 kb
Host smart-1469473e-4dd9-4b94-865a-112ee64dfcb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888165381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.3888165381
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.1406706436
Short name T114
Test name
Test status
Simulation time 167230538385 ps
CPU time 93.9 seconds
Started Jan 07 01:06:52 PM PST 24
Finished Jan 07 01:08:38 PM PST 24
Peak memory 200968 kb
Host smart-3cd142c1-0b9c-4abc-904c-34a356cfbbb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406706436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.1406706436
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.85491826
Short name T225
Test name
Test status
Simulation time 328246132159 ps
CPU time 54.56 seconds
Started Jan 07 01:08:01 PM PST 24
Finished Jan 07 01:08:57 PM PST 24
Peak memory 200532 kb
Host smart-fbf106cb-1a62-4c4c-91d0-89e4bf0538e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85491826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.85491826
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.2722216408
Short name T818
Test name
Test status
Simulation time 489062636244 ps
CPU time 283.85 seconds
Started Jan 07 01:06:38 PM PST 24
Finished Jan 07 01:11:35 PM PST 24
Peak memory 200872 kb
Host smart-73a177ce-d1fb-416a-8d73-384751431c0f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722216408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.2722216408
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.1257998994
Short name T515
Test name
Test status
Simulation time 164308872534 ps
CPU time 176.47 seconds
Started Jan 07 01:06:39 PM PST 24
Finished Jan 07 01:09:50 PM PST 24
Peak memory 200752 kb
Host smart-a84c6370-c428-47ea-a05d-4e7aca7ff508
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257998994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.1257998994
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.1766622164
Short name T792
Test name
Test status
Simulation time 329953765953 ps
CPU time 191.84 seconds
Started Jan 07 01:08:00 PM PST 24
Finished Jan 07 01:11:14 PM PST 24
Peak memory 200476 kb
Host smart-213685ee-8aa3-4003-b03c-12a04dc4fd5e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766622164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.1766622164
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.1580587784
Short name T383
Test name
Test status
Simulation time 166013551305 ps
CPU time 107.23 seconds
Started Jan 07 01:06:33 PM PST 24
Finished Jan 07 01:08:38 PM PST 24
Peak memory 200840 kb
Host smart-f94f80ee-80c9-4a35-8eb2-b5c282617aa2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580587784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.1580587784
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.288329292
Short name T182
Test name
Test status
Simulation time 86243818616 ps
CPU time 328.44 seconds
Started Jan 07 01:06:52 PM PST 24
Finished Jan 07 01:12:33 PM PST 24
Peak memory 201436 kb
Host smart-e1741356-f482-46fc-a4de-d83e878206f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288329292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.288329292
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.1959429930
Short name T698
Test name
Test status
Simulation time 35556833030 ps
CPU time 21.38 seconds
Started Jan 07 01:06:38 PM PST 24
Finished Jan 07 01:07:14 PM PST 24
Peak memory 200652 kb
Host smart-ac3bad89-dc07-43e3-ad3f-80d456ed4b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959429930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.1959429930
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.754332414
Short name T572
Test name
Test status
Simulation time 3196911227 ps
CPU time 7.39 seconds
Started Jan 07 01:06:42 PM PST 24
Finished Jan 07 01:07:04 PM PST 24
Peak memory 200720 kb
Host smart-fa3eac9a-7a1c-43f2-be33-329784764ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754332414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.754332414
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.3571415071
Short name T396
Test name
Test status
Simulation time 5953836741 ps
CPU time 14.83 seconds
Started Jan 07 01:06:40 PM PST 24
Finished Jan 07 01:07:09 PM PST 24
Peak memory 200636 kb
Host smart-726739a2-d580-455f-9934-911da44edab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571415071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.3571415071
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.1469898575
Short name T683
Test name
Test status
Simulation time 182662084692 ps
CPU time 103.52 seconds
Started Jan 07 01:06:35 PM PST 24
Finished Jan 07 01:08:36 PM PST 24
Peak memory 209120 kb
Host smart-eef8e4ad-864e-42b9-b319-91edd477eea6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469898575 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.1469898575
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.3976220639
Short name T767
Test name
Test status
Simulation time 478181540 ps
CPU time 1.71 seconds
Started Jan 07 01:06:44 PM PST 24
Finished Jan 07 01:07:00 PM PST 24
Peak memory 200576 kb
Host smart-af0c0df6-132e-4630-86c0-b42b3ee4ea4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976220639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.3976220639
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.1068530726
Short name T310
Test name
Test status
Simulation time 339939389943 ps
CPU time 87.42 seconds
Started Jan 07 01:06:35 PM PST 24
Finished Jan 07 01:08:18 PM PST 24
Peak memory 200900 kb
Host smart-94447a9d-da85-4a4e-8ae6-979685e2a390
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068530726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.1068530726
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.1054773795
Short name T228
Test name
Test status
Simulation time 165375048315 ps
CPU time 50.67 seconds
Started Jan 07 01:06:39 PM PST 24
Finished Jan 07 01:07:44 PM PST 24
Peak memory 200904 kb
Host smart-4a89ce03-43f1-4c4f-a3c6-e577165004fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054773795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.1054773795
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.2345971316
Short name T747
Test name
Test status
Simulation time 168140388877 ps
CPU time 110.19 seconds
Started Jan 07 01:06:50 PM PST 24
Finished Jan 07 01:08:53 PM PST 24
Peak memory 200804 kb
Host smart-b28033b0-b951-4da6-99f6-fa5f25dccbf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345971316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.2345971316
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.1549605776
Short name T822
Test name
Test status
Simulation time 159285237288 ps
CPU time 93.64 seconds
Started Jan 07 01:06:34 PM PST 24
Finished Jan 07 01:08:26 PM PST 24
Peak memory 200788 kb
Host smart-49077e9c-8192-4d97-beb1-8e024413bd5c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549605776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.1549605776
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.3442119783
Short name T106
Test name
Test status
Simulation time 483402701321 ps
CPU time 1054.72 seconds
Started Jan 07 01:06:36 PM PST 24
Finished Jan 07 01:24:26 PM PST 24
Peak memory 201008 kb
Host smart-d51dda50-0964-47c2-9857-7d19dc87a37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442119783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.3442119783
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.140840473
Short name T128
Test name
Test status
Simulation time 161564100836 ps
CPU time 95.46 seconds
Started Jan 07 01:06:38 PM PST 24
Finished Jan 07 01:08:28 PM PST 24
Peak memory 200772 kb
Host smart-d519952b-8da4-4e06-88fe-d76a1c8531d3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=140840473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fixe
d.140840473
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.3244025095
Short name T732
Test name
Test status
Simulation time 503031089415 ps
CPU time 433.3 seconds
Started Jan 07 01:06:36 PM PST 24
Finished Jan 07 01:14:05 PM PST 24
Peak memory 200828 kb
Host smart-a89341bb-2881-47ea-a40a-517857bc51e6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244025095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.3244025095
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.3333024503
Short name T379
Test name
Test status
Simulation time 324347407550 ps
CPU time 365.71 seconds
Started Jan 07 01:08:03 PM PST 24
Finished Jan 07 01:14:10 PM PST 24
Peak memory 200460 kb
Host smart-fed594b7-3494-47c1-b358-38700984131a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333024503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.3333024503
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.818875450
Short name T191
Test name
Test status
Simulation time 127108326992 ps
CPU time 486.61 seconds
Started Jan 07 01:06:48 PM PST 24
Finished Jan 07 01:15:09 PM PST 24
Peak memory 201364 kb
Host smart-51ad01e8-6095-42be-9b3f-a79d3a8256e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818875450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.818875450
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.3816449409
Short name T710
Test name
Test status
Simulation time 40641072110 ps
CPU time 95.4 seconds
Started Jan 07 01:07:45 PM PST 24
Finished Jan 07 01:09:28 PM PST 24
Peak memory 199368 kb
Host smart-fc25b159-9081-4a00-81e5-dd2f12e91bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816449409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.3816449409
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.156256573
Short name T783
Test name
Test status
Simulation time 4936305249 ps
CPU time 5.96 seconds
Started Jan 07 01:06:35 PM PST 24
Finished Jan 07 01:06:59 PM PST 24
Peak memory 200692 kb
Host smart-3608fb90-03b2-48dc-96be-3b95de347b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156256573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.156256573
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.3025392808
Short name T398
Test name
Test status
Simulation time 6145724712 ps
CPU time 1.73 seconds
Started Jan 07 01:06:38 PM PST 24
Finished Jan 07 01:06:55 PM PST 24
Peak memory 200704 kb
Host smart-e25b31e9-0753-4f82-be2c-ea5814ee55ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025392808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.3025392808
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.340769859
Short name T425
Test name
Test status
Simulation time 6799334268 ps
CPU time 8.72 seconds
Started Jan 07 01:06:45 PM PST 24
Finished Jan 07 01:07:07 PM PST 24
Peak memory 200716 kb
Host smart-db553c7e-c445-4540-afe1-78c44fd75b63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340769859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all.
340769859
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.511767668
Short name T729
Test name
Test status
Simulation time 46592263726 ps
CPU time 110.38 seconds
Started Jan 07 01:06:35 PM PST 24
Finished Jan 07 01:08:43 PM PST 24
Peak memory 201056 kb
Host smart-26b401f3-1be7-45c0-9daa-538afb1a743f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511767668 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.511767668
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.371273190
Short name T418
Test name
Test status
Simulation time 457938096 ps
CPU time 1.71 seconds
Started Jan 07 01:06:13 PM PST 24
Finished Jan 07 01:06:16 PM PST 24
Peak memory 200628 kb
Host smart-d7b6c6d5-dc90-4c5e-b5fb-c52d710d5379
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371273190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.371273190
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.1189930776
Short name T224
Test name
Test status
Simulation time 331661840471 ps
CPU time 742.23 seconds
Started Jan 07 01:06:01 PM PST 24
Finished Jan 07 01:18:27 PM PST 24
Peak memory 200724 kb
Host smart-b0865b68-2629-4627-9ff2-d52d149a0cdb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189930776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.1189930776
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.4071523132
Short name T102
Test name
Test status
Simulation time 495556737471 ps
CPU time 1157.86 seconds
Started Jan 07 01:06:08 PM PST 24
Finished Jan 07 01:25:27 PM PST 24
Peak memory 200892 kb
Host smart-a705d4d7-6ba2-4546-ba5f-0cc054beff28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071523132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.4071523132
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.3083053014
Short name T750
Test name
Test status
Simulation time 165229465506 ps
CPU time 364.47 seconds
Started Jan 07 01:05:54 PM PST 24
Finished Jan 07 01:12:00 PM PST 24
Peak memory 200892 kb
Host smart-d1f3251f-212a-438d-ac97-f6ec5afc7f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083053014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.3083053014
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.3620373843
Short name T609
Test name
Test status
Simulation time 165456083848 ps
CPU time 26.9 seconds
Started Jan 07 01:05:59 PM PST 24
Finished Jan 07 01:06:29 PM PST 24
Peak memory 200756 kb
Host smart-52e47b95-6782-40b1-9c72-9021e2ba08da
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620373843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.3620373843
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.2213101088
Short name T139
Test name
Test status
Simulation time 325635248022 ps
CPU time 70.36 seconds
Started Jan 07 01:05:59 PM PST 24
Finished Jan 07 01:07:12 PM PST 24
Peak memory 200892 kb
Host smart-6d42601d-e76a-4bf5-a449-feb23cc4d18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213101088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.2213101088
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.547720788
Short name T529
Test name
Test status
Simulation time 498121051010 ps
CPU time 1170.75 seconds
Started Jan 07 01:06:04 PM PST 24
Finished Jan 07 01:25:38 PM PST 24
Peak memory 200780 kb
Host smart-26ae2b42-7ca4-4b37-bd0d-780f72bf3e85
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=547720788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixed
.547720788
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.2888086159
Short name T135
Test name
Test status
Simulation time 334132777105 ps
CPU time 194.92 seconds
Started Jan 07 01:06:04 PM PST 24
Finished Jan 07 01:09:22 PM PST 24
Peak memory 200844 kb
Host smart-180c5a80-0340-4fff-89f8-99da2d5c8a6a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888086159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.2888086159
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.2735619704
Short name T48
Test name
Test status
Simulation time 492079562876 ps
CPU time 1129.11 seconds
Started Jan 07 01:06:09 PM PST 24
Finished Jan 07 01:25:00 PM PST 24
Peak memory 200928 kb
Host smart-1e774c04-1e7a-4b77-9097-9c90ba7fda53
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735619704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.2735619704
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.4153738818
Short name T752
Test name
Test status
Simulation time 100276355050 ps
CPU time 343.72 seconds
Started Jan 07 01:06:13 PM PST 24
Finished Jan 07 01:11:59 PM PST 24
Peak memory 201312 kb
Host smart-7ac7a7c5-4eab-4642-bfa0-c1e21991404c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153738818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.4153738818
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.3622552626
Short name T648
Test name
Test status
Simulation time 31935668094 ps
CPU time 18.44 seconds
Started Jan 07 01:05:52 PM PST 24
Finished Jan 07 01:06:19 PM PST 24
Peak memory 200752 kb
Host smart-4fdf3940-97e6-45b1-9d2e-e13fc9fbe489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622552626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.3622552626
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.1739957782
Short name T93
Test name
Test status
Simulation time 4498894685 ps
CPU time 3.11 seconds
Started Jan 07 01:06:15 PM PST 24
Finished Jan 07 01:06:19 PM PST 24
Peak memory 200732 kb
Host smart-19211631-7d97-4691-8df8-db97a13d2ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739957782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.1739957782
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.3087387512
Short name T41
Test name
Test status
Simulation time 8048107163 ps
CPU time 5.57 seconds
Started Jan 07 01:06:28 PM PST 24
Finished Jan 07 01:06:46 PM PST 24
Peak memory 217204 kb
Host smart-20b0decb-6b7e-4227-98b1-5e0e7432755c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087387512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.3087387512
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.3906518519
Short name T397
Test name
Test status
Simulation time 5763104383 ps
CPU time 13.84 seconds
Started Jan 07 01:05:45 PM PST 24
Finished Jan 07 01:06:01 PM PST 24
Peak memory 200776 kb
Host smart-902d6eef-fda6-487d-945d-c0c78aa088f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906518519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.3906518519
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.4279931490
Short name T219
Test name
Test status
Simulation time 550896530510 ps
CPU time 1313.45 seconds
Started Jan 07 01:06:10 PM PST 24
Finished Jan 07 01:28:05 PM PST 24
Peak memory 200976 kb
Host smart-e23c785d-1eeb-4409-86f3-23a6c44b8d70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279931490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
4279931490
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.578385723
Short name T505
Test name
Test status
Simulation time 9522754210 ps
CPU time 38.38 seconds
Started Jan 07 01:06:12 PM PST 24
Finished Jan 07 01:06:52 PM PST 24
Peak memory 209440 kb
Host smart-c83c6c79-8ec0-4184-b05d-37d87533f7ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578385723 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.578385723
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.2094680615
Short name T600
Test name
Test status
Simulation time 525774956 ps
CPU time 0.91 seconds
Started Jan 07 01:06:59 PM PST 24
Finished Jan 07 01:07:09 PM PST 24
Peak memory 200616 kb
Host smart-103a2ac6-0eb5-479f-8140-cb2bfbfac65a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094680615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.2094680615
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.1587539463
Short name T543
Test name
Test status
Simulation time 349469008393 ps
CPU time 192.18 seconds
Started Jan 07 01:06:32 PM PST 24
Finished Jan 07 01:10:03 PM PST 24
Peak memory 200896 kb
Host smart-b411d4c8-4150-40bf-b41f-47e77d1e1760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587539463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.1587539463
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.2283672804
Short name T198
Test name
Test status
Simulation time 162095772798 ps
CPU time 369.95 seconds
Started Jan 07 01:06:42 PM PST 24
Finished Jan 07 01:13:07 PM PST 24
Peak memory 200860 kb
Host smart-c3c924bd-b110-4cc6-98f8-83e41e2fa34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283672804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.2283672804
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.2243394037
Short name T416
Test name
Test status
Simulation time 322750327707 ps
CPU time 420.23 seconds
Started Jan 07 01:06:39 PM PST 24
Finished Jan 07 01:13:53 PM PST 24
Peak memory 200864 kb
Host smart-1a9783a9-f5c8-4624-afc8-1113b8745377
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243394037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.2243394037
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.96814174
Short name T266
Test name
Test status
Simulation time 334149114891 ps
CPU time 401.23 seconds
Started Jan 07 01:06:31 PM PST 24
Finished Jan 07 01:13:32 PM PST 24
Peak memory 200960 kb
Host smart-c75b4621-dfe0-480d-b8df-f7c42dea0608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96814174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.96814174
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.3335946611
Short name T547
Test name
Test status
Simulation time 493241986496 ps
CPU time 576.02 seconds
Started Jan 07 01:08:10 PM PST 24
Finished Jan 07 01:17:47 PM PST 24
Peak memory 200704 kb
Host smart-2b4d81dc-61e1-4e97-97da-e90d84e34875
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335946611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.3335946611
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.4224978748
Short name T331
Test name
Test status
Simulation time 327370353783 ps
CPU time 131.14 seconds
Started Jan 07 01:06:42 PM PST 24
Finished Jan 07 01:09:08 PM PST 24
Peak memory 200896 kb
Host smart-53a144b4-c881-4ee3-b5e9-fe8cd81340dd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224978748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.4224978748
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.1859054413
Short name T523
Test name
Test status
Simulation time 491422485377 ps
CPU time 597.87 seconds
Started Jan 07 01:06:42 PM PST 24
Finished Jan 07 01:16:55 PM PST 24
Peak memory 200692 kb
Host smart-c3c6230d-0057-46cd-9426-78f5d030c636
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859054413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.1859054413
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.1347274912
Short name T665
Test name
Test status
Simulation time 79063391502 ps
CPU time 317.11 seconds
Started Jan 07 01:07:09 PM PST 24
Finished Jan 07 01:12:29 PM PST 24
Peak memory 201364 kb
Host smart-2aca5297-9439-45a4-b2f1-fde215b4226a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347274912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.1347274912
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.39194194
Short name T419
Test name
Test status
Simulation time 35965573104 ps
CPU time 22.92 seconds
Started Jan 07 01:08:10 PM PST 24
Finished Jan 07 01:08:34 PM PST 24
Peak memory 200564 kb
Host smart-2dc1f4be-a636-4285-9e78-007dfb673e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39194194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.39194194
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.834532575
Short name T591
Test name
Test status
Simulation time 5154852093 ps
CPU time 8.39 seconds
Started Jan 07 01:06:38 PM PST 24
Finished Jan 07 01:07:00 PM PST 24
Peak memory 200704 kb
Host smart-32ec61b2-32d3-48c6-b547-8c10eaaaaf1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834532575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.834532575
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.2603672138
Short name T715
Test name
Test status
Simulation time 5957495776 ps
CPU time 4.41 seconds
Started Jan 07 01:07:52 PM PST 24
Finished Jan 07 01:08:02 PM PST 24
Peak memory 199812 kb
Host smart-f1e3a0d1-ed53-4633-9e41-b3f91199438f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603672138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.2603672138
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.3983769500
Short name T788
Test name
Test status
Simulation time 429518330 ps
CPU time 1.63 seconds
Started Jan 07 01:07:08 PM PST 24
Finished Jan 07 01:07:13 PM PST 24
Peak memory 200600 kb
Host smart-42f62296-8bb3-40bc-9ac1-6c59fbede4c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983769500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.3983769500
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.1514004358
Short name T246
Test name
Test status
Simulation time 494018867343 ps
CPU time 1076.78 seconds
Started Jan 07 01:07:00 PM PST 24
Finished Jan 07 01:25:05 PM PST 24
Peak memory 200820 kb
Host smart-e163c270-9a1f-4929-bea7-aa92eaa0d63e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514004358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.1514004358
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.4153934431
Short name T300
Test name
Test status
Simulation time 496212446829 ps
CPU time 1050.9 seconds
Started Jan 07 01:06:59 PM PST 24
Finished Jan 07 01:24:39 PM PST 24
Peak memory 200980 kb
Host smart-b5472827-aef9-4172-9614-e5913bdaaaab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153934431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.4153934431
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.3819458773
Short name T298
Test name
Test status
Simulation time 162034779799 ps
CPU time 184.57 seconds
Started Jan 07 01:07:01 PM PST 24
Finished Jan 07 01:10:13 PM PST 24
Peak memory 200836 kb
Host smart-f2d12850-c367-4e34-99c7-f409c34ac3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819458773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.3819458773
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.2327957805
Short name T635
Test name
Test status
Simulation time 164933357046 ps
CPU time 200.35 seconds
Started Jan 07 01:07:00 PM PST 24
Finished Jan 07 01:10:28 PM PST 24
Peak memory 200744 kb
Host smart-d3de39fd-1538-4bf8-8a00-66212bd7656c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327957805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.2327957805
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.46760821
Short name T502
Test name
Test status
Simulation time 159077098580 ps
CPU time 388.94 seconds
Started Jan 07 01:07:10 PM PST 24
Finished Jan 07 01:13:42 PM PST 24
Peak memory 200820 kb
Host smart-e748e722-c6fc-4930-8bf9-f987b2eeb8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46760821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.46760821
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.3809701929
Short name T504
Test name
Test status
Simulation time 321910586833 ps
CPU time 189.02 seconds
Started Jan 07 01:07:10 PM PST 24
Finished Jan 07 01:10:21 PM PST 24
Peak memory 200968 kb
Host smart-833aa525-1d30-4699-bb31-ea8550fc404a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809701929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.3809701929
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.1717589067
Short name T442
Test name
Test status
Simulation time 497099264443 ps
CPU time 1177.59 seconds
Started Jan 07 01:06:59 PM PST 24
Finished Jan 07 01:26:46 PM PST 24
Peak memory 200796 kb
Host smart-5903b0f4-523d-4f0c-ac9c-af8472a95265
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717589067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.1717589067
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.1347525186
Short name T513
Test name
Test status
Simulation time 41199988359 ps
CPU time 92.72 seconds
Started Jan 07 01:07:01 PM PST 24
Finished Jan 07 01:08:41 PM PST 24
Peak memory 200624 kb
Host smart-80e58a7c-2796-46ae-8c40-a7597e6aeacb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347525186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.1347525186
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.4257297363
Short name T91
Test name
Test status
Simulation time 3631827346 ps
CPU time 9.07 seconds
Started Jan 07 01:07:19 PM PST 24
Finished Jan 07 01:07:29 PM PST 24
Peak memory 200692 kb
Host smart-aabe4c99-467e-4fda-821f-160c2f400167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257297363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.4257297363
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.2083960155
Short name T469
Test name
Test status
Simulation time 5873826535 ps
CPU time 14.35 seconds
Started Jan 07 01:07:12 PM PST 24
Finished Jan 07 01:07:28 PM PST 24
Peak memory 200660 kb
Host smart-6effaccd-6afb-4484-9ca8-691e0d1ec4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083960155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.2083960155
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.197598293
Short name T344
Test name
Test status
Simulation time 358412872900 ps
CPU time 774.34 seconds
Started Jan 07 01:07:08 PM PST 24
Finished Jan 07 01:20:06 PM PST 24
Peak memory 209408 kb
Host smart-b58c7ca7-20e7-4b31-a256-277e1d1f3e4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197598293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all.
197598293
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.905834243
Short name T570
Test name
Test status
Simulation time 124232292811 ps
CPU time 185.56 seconds
Started Jan 07 01:07:18 PM PST 24
Finished Jan 07 01:10:25 PM PST 24
Peak memory 209492 kb
Host smart-e1e3e401-2ae2-4b11-bd6b-4185d838e068
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905834243 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.905834243
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.161380262
Short name T451
Test name
Test status
Simulation time 299301234 ps
CPU time 1.41 seconds
Started Jan 07 01:06:59 PM PST 24
Finished Jan 07 01:07:09 PM PST 24
Peak memory 200656 kb
Host smart-d24d2d62-1e78-44db-bd57-0bda4db2e929
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161380262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.161380262
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.307190137
Short name T820
Test name
Test status
Simulation time 327421446850 ps
CPU time 447.84 seconds
Started Jan 07 01:07:10 PM PST 24
Finished Jan 07 01:14:41 PM PST 24
Peak memory 200964 kb
Host smart-1deb9305-8f26-4507-bbb4-e8b2b2e8ee17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307190137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.307190137
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.4034538864
Short name T301
Test name
Test status
Simulation time 329022719635 ps
CPU time 177.66 seconds
Started Jan 07 01:07:00 PM PST 24
Finished Jan 07 01:10:06 PM PST 24
Peak memory 200912 kb
Host smart-f3d95039-80ed-4308-a8d1-626dfc7e6744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034538864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.4034538864
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.4123492415
Short name T499
Test name
Test status
Simulation time 491563682010 ps
CPU time 1128.13 seconds
Started Jan 07 01:06:59 PM PST 24
Finished Jan 07 01:25:56 PM PST 24
Peak memory 200852 kb
Host smart-fb719819-7f60-45d6-b19f-f2dac13c388c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123492415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.4123492415
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.1501598078
Short name T509
Test name
Test status
Simulation time 336055195273 ps
CPU time 378 seconds
Started Jan 07 01:06:59 PM PST 24
Finished Jan 07 01:13:26 PM PST 24
Peak memory 200924 kb
Host smart-5d3d0612-e21a-4029-9dc7-946a57375f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501598078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.1501598078
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.2326572823
Short name T550
Test name
Test status
Simulation time 166393015132 ps
CPU time 393.3 seconds
Started Jan 07 01:07:22 PM PST 24
Finished Jan 07 01:13:59 PM PST 24
Peak memory 200832 kb
Host smart-14a0d91c-d4e3-4bd8-87a5-f3732dd6c4b9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326572823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.2326572823
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.2721724164
Short name T213
Test name
Test status
Simulation time 172047857861 ps
CPU time 183.01 seconds
Started Jan 07 01:07:00 PM PST 24
Finished Jan 07 01:10:11 PM PST 24
Peak memory 200928 kb
Host smart-f5af2603-4998-48a6-8dd7-e956dec592ba
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721724164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.2721724164
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.3457712589
Short name T256
Test name
Test status
Simulation time 169301867697 ps
CPU time 203.51 seconds
Started Jan 07 01:07:08 PM PST 24
Finished Jan 07 01:10:35 PM PST 24
Peak memory 200824 kb
Host smart-f9eb981e-43b9-4fa0-a937-719679a54335
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457712589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.3457712589
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.1655847728
Short name T754
Test name
Test status
Simulation time 40556456772 ps
CPU time 94.17 seconds
Started Jan 07 01:07:10 PM PST 24
Finished Jan 07 01:08:47 PM PST 24
Peak memory 200736 kb
Host smart-148cd9d4-69c7-4503-be56-dfdb0e46581c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655847728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.1655847728
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.1071858839
Short name T763
Test name
Test status
Simulation time 5624345097 ps
CPU time 4.16 seconds
Started Jan 07 01:07:02 PM PST 24
Finished Jan 07 01:07:12 PM PST 24
Peak memory 200736 kb
Host smart-d1569284-9884-47ab-adc3-8b96e81127d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071858839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.1071858839
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.1910652097
Short name T590
Test name
Test status
Simulation time 5777492455 ps
CPU time 11.81 seconds
Started Jan 07 01:07:00 PM PST 24
Finished Jan 07 01:07:20 PM PST 24
Peak memory 200756 kb
Host smart-690224a7-6a92-45f8-9063-9739acb26a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910652097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.1910652097
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.1808505999
Short name T183
Test name
Test status
Simulation time 95117255431 ps
CPU time 459.89 seconds
Started Jan 07 01:07:12 PM PST 24
Finished Jan 07 01:14:54 PM PST 24
Peak memory 201200 kb
Host smart-01125c06-4d60-4a45-b94c-c9858ea5b8b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808505999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.1808505999
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.1088050068
Short name T36
Test name
Test status
Simulation time 484935327 ps
CPU time 1.73 seconds
Started Jan 07 01:06:57 PM PST 24
Finished Jan 07 01:07:09 PM PST 24
Peak memory 200596 kb
Host smart-dd938e54-eb7e-48e4-84eb-6bb8ccf2a51a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088050068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.1088050068
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.471114492
Short name T21
Test name
Test status
Simulation time 165608316637 ps
CPU time 272.64 seconds
Started Jan 07 01:07:01 PM PST 24
Finished Jan 07 01:11:41 PM PST 24
Peak memory 200832 kb
Host smart-c94ea44b-8c98-430e-98f7-d40844ded5cb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471114492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gati
ng.471114492
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.923123474
Short name T132
Test name
Test status
Simulation time 503189881260 ps
CPU time 1202.3 seconds
Started Jan 07 01:07:08 PM PST 24
Finished Jan 07 01:27:14 PM PST 24
Peak memory 200864 kb
Host smart-9cc19158-2726-486b-8aa9-c1773786cb08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923123474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.923123474
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.85377488
Short name T618
Test name
Test status
Simulation time 168528148335 ps
CPU time 399.06 seconds
Started Jan 07 01:07:00 PM PST 24
Finished Jan 07 01:13:47 PM PST 24
Peak memory 200792 kb
Host smart-366da95b-7307-45d9-91e8-e85cf79fdc55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85377488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.85377488
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.3994179888
Short name T705
Test name
Test status
Simulation time 332870493486 ps
CPU time 796.53 seconds
Started Jan 07 01:07:10 PM PST 24
Finished Jan 07 01:20:29 PM PST 24
Peak memory 200824 kb
Host smart-04c90439-79b2-4a4b-842d-1352a30cf7ab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994179888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.3994179888
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.1204599131
Short name T247
Test name
Test status
Simulation time 161313231551 ps
CPU time 89.35 seconds
Started Jan 07 01:06:59 PM PST 24
Finished Jan 07 01:08:37 PM PST 24
Peak memory 201028 kb
Host smart-18db477e-80cc-4a91-a39b-850b542f5aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204599131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.1204599131
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.713417406
Short name T412
Test name
Test status
Simulation time 169565505865 ps
CPU time 24.58 seconds
Started Jan 07 01:07:18 PM PST 24
Finished Jan 07 01:07:44 PM PST 24
Peak memory 200764 kb
Host smart-8058ba7c-6572-40b1-b54d-43e1cc96c242
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=713417406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fixe
d.713417406
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.2965403516
Short name T296
Test name
Test status
Simulation time 328149176443 ps
CPU time 601.19 seconds
Started Jan 07 01:07:00 PM PST 24
Finished Jan 07 01:17:09 PM PST 24
Peak memory 200828 kb
Host smart-82362ec9-56d0-405e-a93d-43d0dcdc8f87
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965403516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.2965403516
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.515109315
Short name T458
Test name
Test status
Simulation time 163551860878 ps
CPU time 391.97 seconds
Started Jan 07 01:07:09 PM PST 24
Finished Jan 07 01:13:44 PM PST 24
Peak memory 200908 kb
Host smart-2173bcea-781f-4b30-9797-0bc7f275ca98
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515109315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
adc_ctrl_filters_wakeup_fixed.515109315
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.3978897974
Short name T702
Test name
Test status
Simulation time 129315820952 ps
CPU time 487.46 seconds
Started Jan 07 01:07:00 PM PST 24
Finished Jan 07 01:15:16 PM PST 24
Peak memory 201272 kb
Host smart-24a20e01-e247-46ce-ab08-5bd7c62db097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978897974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.3978897974
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.1641551134
Short name T723
Test name
Test status
Simulation time 27870873183 ps
CPU time 15.42 seconds
Started Jan 07 01:07:10 PM PST 24
Finished Jan 07 01:07:28 PM PST 24
Peak memory 200760 kb
Host smart-cd449160-8336-4482-b59a-b3481534ea06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641551134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.1641551134
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.3749715460
Short name T450
Test name
Test status
Simulation time 3450438783 ps
CPU time 2.92 seconds
Started Jan 07 01:06:55 PM PST 24
Finished Jan 07 01:07:09 PM PST 24
Peak memory 200740 kb
Host smart-5209a56c-9007-4249-8fc0-8e1b23ba86d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749715460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.3749715460
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.1691539832
Short name T417
Test name
Test status
Simulation time 5613756218 ps
CPU time 13.88 seconds
Started Jan 07 01:06:59 PM PST 24
Finished Jan 07 01:07:22 PM PST 24
Peak memory 200796 kb
Host smart-569b5e44-7889-4832-a617-146f5f60c531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691539832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.1691539832
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.2260680676
Short name T503
Test name
Test status
Simulation time 320874813 ps
CPU time 1.39 seconds
Started Jan 07 01:07:12 PM PST 24
Finished Jan 07 01:07:15 PM PST 24
Peak memory 200604 kb
Host smart-a714ffe7-c4d4-43af-a7fe-4a6bce2f00b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260680676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.2260680676
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.3412207036
Short name T129
Test name
Test status
Simulation time 490710013870 ps
CPU time 607.95 seconds
Started Jan 07 01:07:00 PM PST 24
Finished Jan 07 01:17:16 PM PST 24
Peak memory 200912 kb
Host smart-be1a9c17-0733-42ad-bb36-eb1c70ab300d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412207036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.3412207036
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.2102506110
Short name T819
Test name
Test status
Simulation time 164394594103 ps
CPU time 200.69 seconds
Started Jan 07 01:07:02 PM PST 24
Finished Jan 07 01:10:29 PM PST 24
Peak memory 200888 kb
Host smart-dcf02cbe-b7f9-4d12-83b8-8a76bf24c73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102506110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.2102506110
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.250818046
Short name T562
Test name
Test status
Simulation time 165860749026 ps
CPU time 104.64 seconds
Started Jan 07 01:06:53 PM PST 24
Finished Jan 07 01:08:49 PM PST 24
Peak memory 200884 kb
Host smart-90f21f6a-9e3b-46ff-b9cb-fbbf5469936f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=250818046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrup
t_fixed.250818046
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.1694788502
Short name T736
Test name
Test status
Simulation time 325997996050 ps
CPU time 719.13 seconds
Started Jan 07 01:07:00 PM PST 24
Finished Jan 07 01:19:07 PM PST 24
Peak memory 200864 kb
Host smart-d162b6e7-1fbd-471a-a6bb-756e548adbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694788502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.1694788502
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.576088117
Short name T806
Test name
Test status
Simulation time 496541869776 ps
CPU time 863.55 seconds
Started Jan 07 01:07:09 PM PST 24
Finished Jan 07 01:21:36 PM PST 24
Peak memory 200808 kb
Host smart-c27fe744-3c3f-4a9d-93dc-b063b1f50a4c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=576088117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fixe
d.576088117
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.2563165837
Short name T632
Test name
Test status
Simulation time 501029820223 ps
CPU time 305.36 seconds
Started Jan 07 01:07:10 PM PST 24
Finished Jan 07 01:12:18 PM PST 24
Peak memory 200904 kb
Host smart-31311e3a-0d4d-4601-9d10-9b39fd2ce5d2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563165837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.2563165837
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.79443341
Short name T742
Test name
Test status
Simulation time 163867200707 ps
CPU time 204.89 seconds
Started Jan 07 01:07:06 PM PST 24
Finished Jan 07 01:10:35 PM PST 24
Peak memory 200852 kb
Host smart-c46c44f5-f1e0-4ed5-b32a-636a0434bda4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79443341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.a
dc_ctrl_filters_wakeup_fixed.79443341
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.421835317
Short name T341
Test name
Test status
Simulation time 138414102117 ps
CPU time 381.8 seconds
Started Jan 07 01:07:17 PM PST 24
Finished Jan 07 01:13:40 PM PST 24
Peak memory 201280 kb
Host smart-66150f1f-73b7-4527-bfd6-1227ef248fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421835317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.421835317
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.3859171804
Short name T511
Test name
Test status
Simulation time 24083479834 ps
CPU time 26.64 seconds
Started Jan 07 01:06:59 PM PST 24
Finished Jan 07 01:07:35 PM PST 24
Peak memory 200636 kb
Host smart-95c3f6a5-c985-4105-8fbf-b389aa13dfd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859171804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.3859171804
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.31713086
Short name T772
Test name
Test status
Simulation time 5146486911 ps
CPU time 3.79 seconds
Started Jan 07 01:07:18 PM PST 24
Finished Jan 07 01:07:23 PM PST 24
Peak memory 200584 kb
Host smart-fb302e4e-b87d-4dcf-bd7c-b49e4995daf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31713086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.31713086
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.1527966401
Short name T530
Test name
Test status
Simulation time 5752029616 ps
CPU time 7.46 seconds
Started Jan 07 01:06:58 PM PST 24
Finished Jan 07 01:07:15 PM PST 24
Peak memory 200688 kb
Host smart-a553ea98-13db-47a7-90ef-186cad18d999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527966401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.1527966401
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.2926486045
Short name T303
Test name
Test status
Simulation time 346109958335 ps
CPU time 226.79 seconds
Started Jan 07 01:07:20 PM PST 24
Finished Jan 07 01:11:09 PM PST 24
Peak memory 200828 kb
Host smart-281173e6-dc9a-4e5c-944f-e1a8372140ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926486045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.2926486045
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.2530174062
Short name T831
Test name
Test status
Simulation time 34582310790 ps
CPU time 16.44 seconds
Started Jan 07 01:07:21 PM PST 24
Finished Jan 07 01:07:42 PM PST 24
Peak memory 200940 kb
Host smart-b1d3ced9-1526-43c4-b3f8-c92ffc5c8079
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530174062 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.2530174062
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.2921208431
Short name T808
Test name
Test status
Simulation time 453037464 ps
CPU time 0.91 seconds
Started Jan 07 01:07:32 PM PST 24
Finished Jan 07 01:07:34 PM PST 24
Peak memory 200560 kb
Host smart-31014a2d-532d-451c-9822-d296ba5f6197
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921208431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.2921208431
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.2039770488
Short name T168
Test name
Test status
Simulation time 490366413107 ps
CPU time 263.96 seconds
Started Jan 07 01:07:32 PM PST 24
Finished Jan 07 01:11:58 PM PST 24
Peak memory 200848 kb
Host smart-ef781129-7d2e-4bac-9131-f4d759ece253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039770488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.2039770488
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.3858240416
Short name T631
Test name
Test status
Simulation time 161023434323 ps
CPU time 187.73 seconds
Started Jan 07 01:07:30 PM PST 24
Finished Jan 07 01:10:39 PM PST 24
Peak memory 200964 kb
Host smart-ba830777-4acb-405f-8325-666c5c6f41f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858240416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.3858240416
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.913818646
Short name T626
Test name
Test status
Simulation time 325615154466 ps
CPU time 759.06 seconds
Started Jan 07 01:07:23 PM PST 24
Finished Jan 07 01:20:06 PM PST 24
Peak memory 200888 kb
Host smart-27f2e33d-a4c3-4700-bd2d-af21aca8c9fc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=913818646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrup
t_fixed.913818646
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.3141747763
Short name T521
Test name
Test status
Simulation time 162932952275 ps
CPU time 392.44 seconds
Started Jan 07 01:07:13 PM PST 24
Finished Jan 07 01:13:47 PM PST 24
Peak memory 200996 kb
Host smart-7733c3db-2fa7-4b0c-bed6-9766d0a30fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141747763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.3141747763
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.1638979599
Short name T620
Test name
Test status
Simulation time 328205467680 ps
CPU time 302.13 seconds
Started Jan 07 01:07:15 PM PST 24
Finished Jan 07 01:12:18 PM PST 24
Peak memory 200872 kb
Host smart-9e8e9fc4-6b07-4664-a47c-b737355be589
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638979599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.1638979599
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.1428397147
Short name T47
Test name
Test status
Simulation time 169278594630 ps
CPU time 100.52 seconds
Started Jan 07 01:07:29 PM PST 24
Finished Jan 07 01:09:11 PM PST 24
Peak memory 200904 kb
Host smart-547220aa-32fb-490e-93a9-0129de99a3bf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428397147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.1428397147
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.3677952699
Short name T615
Test name
Test status
Simulation time 491353812020 ps
CPU time 1214.12 seconds
Started Jan 07 01:07:29 PM PST 24
Finished Jan 07 01:27:45 PM PST 24
Peak memory 200836 kb
Host smart-419e8b65-3d5c-40e7-a9a1-25d231864429
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677952699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.3677952699
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.527891828
Short name T561
Test name
Test status
Simulation time 110109497305 ps
CPU time 353.43 seconds
Started Jan 07 01:07:29 PM PST 24
Finished Jan 07 01:13:24 PM PST 24
Peak memory 201220 kb
Host smart-92cd9c56-27dd-429e-8427-36e972aa96ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527891828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.527891828
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.3716489161
Short name T394
Test name
Test status
Simulation time 38135918456 ps
CPU time 45.21 seconds
Started Jan 07 01:07:32 PM PST 24
Finished Jan 07 01:08:20 PM PST 24
Peak memory 200752 kb
Host smart-52db99bf-040a-4d80-9152-c79ab470414e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716489161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.3716489161
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.3630480322
Short name T733
Test name
Test status
Simulation time 4065207522 ps
CPU time 1.2 seconds
Started Jan 07 01:07:35 PM PST 24
Finished Jan 07 01:07:40 PM PST 24
Peak memory 200876 kb
Host smart-7b451848-8146-45bc-9c01-c991295da041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630480322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.3630480322
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.962027730
Short name T567
Test name
Test status
Simulation time 5691294533 ps
CPU time 3.63 seconds
Started Jan 07 01:07:22 PM PST 24
Finished Jan 07 01:07:30 PM PST 24
Peak memory 200704 kb
Host smart-95dcb5ed-187a-4ca2-a20c-05eb9b593b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962027730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.962027730
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.3552640318
Short name T220
Test name
Test status
Simulation time 212975665285 ps
CPU time 124.29 seconds
Started Jan 07 01:07:36 PM PST 24
Finished Jan 07 01:09:43 PM PST 24
Peak memory 200952 kb
Host smart-2043b5ae-c96a-4b18-a332-636bdf22bd09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552640318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.3552640318
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.1583792749
Short name T704
Test name
Test status
Simulation time 525097190 ps
CPU time 0.98 seconds
Started Jan 07 01:07:20 PM PST 24
Finished Jan 07 01:07:23 PM PST 24
Peak memory 200600 kb
Host smart-07b8df14-7e83-418e-84d9-09b63569533b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583792749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.1583792749
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.3077914884
Short name T107
Test name
Test status
Simulation time 163818968547 ps
CPU time 355.15 seconds
Started Jan 07 01:07:16 PM PST 24
Finished Jan 07 01:13:12 PM PST 24
Peak memory 200908 kb
Host smart-33584ce7-02c7-4fc0-9fff-cdca2ce7a5da
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077914884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.3077914884
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.358566364
Short name T111
Test name
Test status
Simulation time 176143796115 ps
CPU time 181.53 seconds
Started Jan 07 01:07:26 PM PST 24
Finished Jan 07 01:10:29 PM PST 24
Peak memory 200896 kb
Host smart-befb77a2-0601-4323-b5df-b156f3da7538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358566364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.358566364
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.270055184
Short name T162
Test name
Test status
Simulation time 329581265417 ps
CPU time 194.82 seconds
Started Jan 07 01:07:09 PM PST 24
Finished Jan 07 01:10:27 PM PST 24
Peak memory 200976 kb
Host smart-50747fed-428f-4135-9e38-5d6446a878ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270055184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.270055184
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.78661758
Short name T413
Test name
Test status
Simulation time 486965974831 ps
CPU time 1186.66 seconds
Started Jan 07 01:07:08 PM PST 24
Finished Jan 07 01:26:58 PM PST 24
Peak memory 200844 kb
Host smart-9c10187e-b83a-49e3-b03c-fdefc106a03a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=78661758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt
_fixed.78661758
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.1681108810
Short name T782
Test name
Test status
Simulation time 167254425707 ps
CPU time 94.81 seconds
Started Jan 07 01:07:36 PM PST 24
Finished Jan 07 01:09:15 PM PST 24
Peak memory 200912 kb
Host smart-0c18a385-1896-454c-b52b-c56635c690bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681108810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.1681108810
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.2963049492
Short name T744
Test name
Test status
Simulation time 165481198787 ps
CPU time 207.13 seconds
Started Jan 07 01:07:22 PM PST 24
Finished Jan 07 01:10:53 PM PST 24
Peak memory 200944 kb
Host smart-1a7a0910-ad36-4073-b9d9-3f7143722eb6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963049492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.2963049492
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.3801929444
Short name T790
Test name
Test status
Simulation time 344002760203 ps
CPU time 200.1 seconds
Started Jan 07 01:07:21 PM PST 24
Finished Jan 07 01:10:46 PM PST 24
Peak memory 200900 kb
Host smart-102c27ec-e0bf-4e7c-a44c-1b6a4319a880
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801929444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.3801929444
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.3803457995
Short name T740
Test name
Test status
Simulation time 329827511690 ps
CPU time 404.04 seconds
Started Jan 07 01:07:10 PM PST 24
Finished Jan 07 01:13:57 PM PST 24
Peak memory 200900 kb
Host smart-80b8ad4e-3bff-4f09-84cd-7be45ce0c6fd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803457995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.3803457995
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.2985087819
Short name T603
Test name
Test status
Simulation time 130841597839 ps
CPU time 460.77 seconds
Started Jan 07 01:07:09 PM PST 24
Finished Jan 07 01:14:53 PM PST 24
Peak memory 201396 kb
Host smart-56e097e0-1a6a-488f-9e18-9ab464385045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985087819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.2985087819
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.1798955143
Short name T555
Test name
Test status
Simulation time 44918085829 ps
CPU time 25.75 seconds
Started Jan 07 01:07:22 PM PST 24
Finished Jan 07 01:07:52 PM PST 24
Peak memory 200684 kb
Host smart-a94c2b00-3dbb-4d2e-a3a2-a4f4ce903a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798955143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.1798955143
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.2837935719
Short name T500
Test name
Test status
Simulation time 4491216005 ps
CPU time 4.62 seconds
Started Jan 07 01:07:22 PM PST 24
Finished Jan 07 01:07:30 PM PST 24
Peak memory 200716 kb
Host smart-f6dc0845-1d3f-412d-810a-aa7d44f6574a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837935719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.2837935719
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.1713225461
Short name T816
Test name
Test status
Simulation time 5709748450 ps
CPU time 12.58 seconds
Started Jan 07 01:07:35 PM PST 24
Finished Jan 07 01:07:51 PM PST 24
Peak memory 200600 kb
Host smart-582c497f-214e-48f7-ad4c-8cd5f6afb437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713225461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.1713225461
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.2911318362
Short name T326
Test name
Test status
Simulation time 338036631495 ps
CPU time 709.47 seconds
Started Jan 07 01:07:10 PM PST 24
Finished Jan 07 01:19:02 PM PST 24
Peak memory 200956 kb
Host smart-25ede87e-4668-48a4-9f5d-cb9532897606
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911318362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.2911318362
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.465069556
Short name T286
Test name
Test status
Simulation time 25033049573 ps
CPU time 55.97 seconds
Started Jan 07 01:07:17 PM PST 24
Finished Jan 07 01:08:14 PM PST 24
Peak memory 200880 kb
Host smart-b676068d-1910-4c2a-84dd-88add22716fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465069556 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.465069556
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.2134189766
Short name T556
Test name
Test status
Simulation time 405415747 ps
CPU time 1.49 seconds
Started Jan 07 01:07:22 PM PST 24
Finished Jan 07 01:07:28 PM PST 24
Peak memory 200556 kb
Host smart-0f55436e-d0f3-4cae-82ba-95d4ac58698a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134189766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.2134189766
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.2732520362
Short name T815
Test name
Test status
Simulation time 326052483318 ps
CPU time 788.42 seconds
Started Jan 07 01:07:16 PM PST 24
Finished Jan 07 01:20:26 PM PST 24
Peak memory 200800 kb
Host smart-c34ad56b-b7f7-4302-9cfe-9aad2d0f5542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732520362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.2732520362
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.3252599937
Short name T610
Test name
Test status
Simulation time 321919650955 ps
CPU time 799.27 seconds
Started Jan 07 01:07:15 PM PST 24
Finished Jan 07 01:20:35 PM PST 24
Peak memory 200816 kb
Host smart-165f2803-679a-401e-8cfa-bc76d04a1cc1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252599937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.3252599937
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.482479644
Short name T712
Test name
Test status
Simulation time 164593646411 ps
CPU time 273.2 seconds
Started Jan 07 01:07:13 PM PST 24
Finished Jan 07 01:11:48 PM PST 24
Peak memory 200828 kb
Host smart-a7efd55c-ec00-47fa-8036-272be5fa4efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482479644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.482479644
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.3058827603
Short name T526
Test name
Test status
Simulation time 163588776578 ps
CPU time 90.4 seconds
Started Jan 07 01:07:16 PM PST 24
Finished Jan 07 01:08:48 PM PST 24
Peak memory 200908 kb
Host smart-6f8b8de6-7144-406a-ac1a-9b32f65e3bd0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058827603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.3058827603
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.2530543194
Short name T427
Test name
Test status
Simulation time 329301792291 ps
CPU time 402.22 seconds
Started Jan 07 01:07:26 PM PST 24
Finished Jan 07 01:14:10 PM PST 24
Peak memory 200832 kb
Host smart-419ab3b2-004b-45f4-ae88-bd0a5493734e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530543194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.2530543194
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.10695773
Short name T625
Test name
Test status
Simulation time 151830790477 ps
CPU time 720.69 seconds
Started Jan 07 01:07:11 PM PST 24
Finished Jan 07 01:19:14 PM PST 24
Peak memory 201288 kb
Host smart-0d1c5d6d-9982-46c7-9fde-32d73171a0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10695773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.10695773
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.3881298761
Short name T827
Test name
Test status
Simulation time 36105696492 ps
CPU time 41.66 seconds
Started Jan 07 01:07:23 PM PST 24
Finished Jan 07 01:08:08 PM PST 24
Peak memory 200680 kb
Host smart-2d3d8514-ab6b-437d-a638-3069aa53a147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881298761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.3881298761
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.2082238465
Short name T519
Test name
Test status
Simulation time 4155385580 ps
CPU time 10.83 seconds
Started Jan 07 01:07:16 PM PST 24
Finished Jan 07 01:07:28 PM PST 24
Peak memory 200588 kb
Host smart-22e816b8-6bf5-411d-a0d2-5c7f6fd27554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082238465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.2082238465
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.3121161102
Short name T488
Test name
Test status
Simulation time 5477140279 ps
CPU time 13.59 seconds
Started Jan 07 01:07:24 PM PST 24
Finished Jan 07 01:07:41 PM PST 24
Peak memory 200756 kb
Host smart-46dccc1f-cafc-4ebb-b868-b8bcce9debc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121161102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.3121161102
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.2481147730
Short name T145
Test name
Test status
Simulation time 333663345935 ps
CPU time 761.89 seconds
Started Jan 07 01:07:15 PM PST 24
Finished Jan 07 01:19:58 PM PST 24
Peak memory 200780 kb
Host smart-27b21d67-0d0f-451a-929a-10be5bb1e946
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481147730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.2481147730
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.161812688
Short name T678
Test name
Test status
Simulation time 84244089364 ps
CPU time 138.96 seconds
Started Jan 07 01:07:17 PM PST 24
Finished Jan 07 01:09:38 PM PST 24
Peak memory 217332 kb
Host smart-75675d11-2a04-4436-9cef-a3238619da68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161812688 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.161812688
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.754102066
Short name T400
Test name
Test status
Simulation time 397613819 ps
CPU time 0.83 seconds
Started Jan 07 01:07:08 PM PST 24
Finished Jan 07 01:07:12 PM PST 24
Peak memory 200604 kb
Host smart-fa8540ea-30c9-4b13-9659-0267ee882696
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754102066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.754102066
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.2617580819
Short name T146
Test name
Test status
Simulation time 489620603020 ps
CPU time 131.43 seconds
Started Jan 07 01:07:17 PM PST 24
Finished Jan 07 01:09:30 PM PST 24
Peak memory 200904 kb
Host smart-60ae4165-40ec-49ee-bf85-eccae2182cb7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617580819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.2617580819
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.310415493
Short name T141
Test name
Test status
Simulation time 324532456481 ps
CPU time 207.18 seconds
Started Jan 07 01:07:02 PM PST 24
Finished Jan 07 01:10:35 PM PST 24
Peak memory 200960 kb
Host smart-8ea32132-316b-46f2-a951-29f20ff84d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310415493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.310415493
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.969682835
Short name T250
Test name
Test status
Simulation time 329169233272 ps
CPU time 781.43 seconds
Started Jan 07 01:07:20 PM PST 24
Finished Jan 07 01:20:25 PM PST 24
Peak memory 200968 kb
Host smart-467363f0-40f2-42d2-a071-3527307b57f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969682835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.969682835
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.3240923235
Short name T743
Test name
Test status
Simulation time 167713527914 ps
CPU time 405.27 seconds
Started Jan 07 01:07:19 PM PST 24
Finished Jan 07 01:14:06 PM PST 24
Peak memory 200888 kb
Host smart-a47efabc-9904-448d-9b96-102e8ead101d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240923235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.3240923235
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.1289304568
Short name T546
Test name
Test status
Simulation time 159166194435 ps
CPU time 392.8 seconds
Started Jan 07 01:07:22 PM PST 24
Finished Jan 07 01:13:59 PM PST 24
Peak memory 200872 kb
Host smart-5cc0a862-663c-4035-a4af-f965df83ef5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289304568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.1289304568
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.1955230584
Short name T532
Test name
Test status
Simulation time 328165782715 ps
CPU time 711.19 seconds
Started Jan 07 01:07:19 PM PST 24
Finished Jan 07 01:19:11 PM PST 24
Peak memory 200832 kb
Host smart-2320bacd-e8f2-4c1f-af33-f576e2e9045f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955230584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.1955230584
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.4238337859
Short name T217
Test name
Test status
Simulation time 334415630391 ps
CPU time 779.49 seconds
Started Jan 07 01:07:28 PM PST 24
Finished Jan 07 01:20:29 PM PST 24
Peak memory 200824 kb
Host smart-9457423a-3bde-4239-b86f-ae934380845c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238337859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.4238337859
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.4249906293
Short name T484
Test name
Test status
Simulation time 491603928661 ps
CPU time 780.61 seconds
Started Jan 07 01:07:20 PM PST 24
Finished Jan 07 01:20:23 PM PST 24
Peak memory 200832 kb
Host smart-4731c9a9-5d63-4fd6-916d-f33a15b7bf53
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249906293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.4249906293
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.597354901
Short name T749
Test name
Test status
Simulation time 98076817429 ps
CPU time 356.01 seconds
Started Jan 07 01:07:13 PM PST 24
Finished Jan 07 01:13:10 PM PST 24
Peak memory 201344 kb
Host smart-2b732f65-0d84-410b-875f-05dfe015eb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597354901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.597354901
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.3658701137
Short name T584
Test name
Test status
Simulation time 33056197642 ps
CPU time 36.73 seconds
Started Jan 07 01:07:23 PM PST 24
Finished Jan 07 01:08:03 PM PST 24
Peak memory 200712 kb
Host smart-30816eb4-4aad-47ce-be6c-e02ba40415df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658701137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.3658701137
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.3989921362
Short name T518
Test name
Test status
Simulation time 3820941921 ps
CPU time 9.37 seconds
Started Jan 07 01:07:27 PM PST 24
Finished Jan 07 01:07:38 PM PST 24
Peak memory 200760 kb
Host smart-ad121daa-e8c1-481f-9d53-60ce34bc3819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989921362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.3989921362
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.2253696115
Short name T28
Test name
Test status
Simulation time 5830114140 ps
CPU time 14.46 seconds
Started Jan 07 01:07:11 PM PST 24
Finished Jan 07 01:07:28 PM PST 24
Peak memory 200684 kb
Host smart-e4498d45-2e1d-4c46-b9a2-13a96337300a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253696115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.2253696115
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.2532316890
Short name T186
Test name
Test status
Simulation time 275808399478 ps
CPU time 234.08 seconds
Started Jan 07 01:07:17 PM PST 24
Finished Jan 07 01:11:13 PM PST 24
Peak memory 209612 kb
Host smart-10c50443-99d2-4ef7-b87c-1f8e490f1ab9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532316890 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.2532316890
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.843887885
Short name T453
Test name
Test status
Simulation time 524738608 ps
CPU time 0.93 seconds
Started Jan 07 01:07:32 PM PST 24
Finished Jan 07 01:07:35 PM PST 24
Peak memory 200660 kb
Host smart-329d79b1-46c7-4b3d-8d34-2c3ccfde21ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843887885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.843887885
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.292469059
Short name T240
Test name
Test status
Simulation time 326957160096 ps
CPU time 105.48 seconds
Started Jan 07 01:07:21 PM PST 24
Finished Jan 07 01:09:11 PM PST 24
Peak memory 200816 kb
Host smart-516d3912-fcd2-48ba-ab4c-cf2ef008c2b2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292469059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gati
ng.292469059
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.1494129568
Short name T142
Test name
Test status
Simulation time 325254717766 ps
CPU time 49.49 seconds
Started Jan 07 01:07:29 PM PST 24
Finished Jan 07 01:08:20 PM PST 24
Peak memory 200892 kb
Host smart-fecae961-7e23-4d03-b0c2-e83e60cb4b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494129568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.1494129568
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.2637388222
Short name T657
Test name
Test status
Simulation time 326838798105 ps
CPU time 378.12 seconds
Started Jan 07 01:07:18 PM PST 24
Finished Jan 07 01:13:38 PM PST 24
Peak memory 200896 kb
Host smart-c130c7e4-6d49-4967-999b-5475f4c2b262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637388222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.2637388222
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.1273257031
Short name T724
Test name
Test status
Simulation time 170142271198 ps
CPU time 292.28 seconds
Started Jan 07 01:07:22 PM PST 24
Finished Jan 07 01:12:18 PM PST 24
Peak memory 200932 kb
Host smart-f5483f5c-7bf9-405c-8a3a-ce24a2f4c4c8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273257031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.1273257031
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.371451415
Short name T320
Test name
Test status
Simulation time 327934685326 ps
CPU time 203.08 seconds
Started Jan 07 01:07:17 PM PST 24
Finished Jan 07 01:10:41 PM PST 24
Peak memory 201008 kb
Host smart-e2e6cf66-bdee-4af7-9514-a005c9847746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371451415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.371451415
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.195532208
Short name T647
Test name
Test status
Simulation time 329842738839 ps
CPU time 181.49 seconds
Started Jan 07 01:07:10 PM PST 24
Finished Jan 07 01:10:14 PM PST 24
Peak memory 200880 kb
Host smart-b8c50290-caed-4c4b-b73e-1fb636409752
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=195532208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fixe
d.195532208
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.3330031306
Short name T624
Test name
Test status
Simulation time 498349723381 ps
CPU time 311.82 seconds
Started Jan 07 01:07:22 PM PST 24
Finished Jan 07 01:12:38 PM PST 24
Peak memory 200872 kb
Host smart-96b41101-ca24-49db-a2f8-81262ec6180f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330031306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.3330031306
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.985616900
Short name T597
Test name
Test status
Simulation time 494589308979 ps
CPU time 602.21 seconds
Started Jan 07 01:07:17 PM PST 24
Finished Jan 07 01:17:20 PM PST 24
Peak memory 200936 kb
Host smart-c12d033d-1951-422b-9262-c4cdca060d90
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985616900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
adc_ctrl_filters_wakeup_fixed.985616900
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.288533311
Short name T193
Test name
Test status
Simulation time 98330396895 ps
CPU time 530.46 seconds
Started Jan 07 01:07:22 PM PST 24
Finished Jan 07 01:16:17 PM PST 24
Peak memory 201332 kb
Host smart-1f44acb6-ab02-4e9b-bd50-6e6641d89eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288533311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.288533311
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.2239414962
Short name T637
Test name
Test status
Simulation time 43789900284 ps
CPU time 88.08 seconds
Started Jan 07 01:07:29 PM PST 24
Finished Jan 07 01:08:59 PM PST 24
Peak memory 200724 kb
Host smart-5cd8902f-ab5e-442a-9e31-c94dd747d024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239414962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.2239414962
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.3079931672
Short name T799
Test name
Test status
Simulation time 3733186255 ps
CPU time 5.27 seconds
Started Jan 07 01:07:22 PM PST 24
Finished Jan 07 01:07:31 PM PST 24
Peak memory 200756 kb
Host smart-896502b9-c8f8-4118-aff2-7f24c6c2dcaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079931672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.3079931672
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.1476993794
Short name T621
Test name
Test status
Simulation time 5834654618 ps
CPU time 3.84 seconds
Started Jan 07 01:07:23 PM PST 24
Finished Jan 07 01:07:31 PM PST 24
Peak memory 200656 kb
Host smart-23737ea5-abcc-4ac0-96a9-bf6fba6d0ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476993794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.1476993794
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.2914866644
Short name T311
Test name
Test status
Simulation time 171718016456 ps
CPU time 399.35 seconds
Started Jan 07 01:07:30 PM PST 24
Finished Jan 07 01:14:12 PM PST 24
Peak memory 200928 kb
Host smart-8c0b0176-5e46-41c4-98bd-45ebb5e8964f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914866644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.2914866644
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.851270021
Short name T269
Test name
Test status
Simulation time 216175438023 ps
CPU time 263.75 seconds
Started Jan 07 01:07:22 PM PST 24
Finished Jan 07 01:11:50 PM PST 24
Peak memory 209816 kb
Host smart-64ff022b-ed67-4d69-b419-d78f8e9d8b36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851270021 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.851270021
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.3496880137
Short name T655
Test name
Test status
Simulation time 476283272 ps
CPU time 1.81 seconds
Started Jan 07 01:06:24 PM PST 24
Finished Jan 07 01:06:28 PM PST 24
Peak memory 200684 kb
Host smart-d8d9091d-216a-4ca9-ad2a-8979a0b189d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496880137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.3496880137
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.645009746
Short name T691
Test name
Test status
Simulation time 165231299619 ps
CPU time 27.75 seconds
Started Jan 07 01:06:23 PM PST 24
Finished Jan 07 01:06:52 PM PST 24
Peak memory 200968 kb
Host smart-dd497570-d420-4dfa-b726-d13b27038b8a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645009746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gatin
g.645009746
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.3778625697
Short name T273
Test name
Test status
Simulation time 165996284743 ps
CPU time 383.98 seconds
Started Jan 07 01:06:15 PM PST 24
Finished Jan 07 01:12:40 PM PST 24
Peak memory 200984 kb
Host smart-ba609322-9915-446a-813e-4ad1f1f8466d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778625697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.3778625697
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.1623260967
Short name T703
Test name
Test status
Simulation time 493869642524 ps
CPU time 1137.02 seconds
Started Jan 07 01:06:12 PM PST 24
Finished Jan 07 01:25:10 PM PST 24
Peak memory 200852 kb
Host smart-6efc9a6a-7211-459a-a2d0-d0b9e77422bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623260967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.1623260967
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.821056877
Short name T682
Test name
Test status
Simulation time 490342833185 ps
CPU time 186.12 seconds
Started Jan 07 01:06:16 PM PST 24
Finished Jan 07 01:09:23 PM PST 24
Peak memory 200900 kb
Host smart-71af254f-2638-4766-ad63-022f119478f6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=821056877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt
_fixed.821056877
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.3952783530
Short name T112
Test name
Test status
Simulation time 326783007666 ps
CPU time 54.58 seconds
Started Jan 07 01:06:09 PM PST 24
Finished Jan 07 01:07:05 PM PST 24
Peak memory 200984 kb
Host smart-c2b49ca0-e0e8-49a7-a534-a4b4b18c0dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952783530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.3952783530
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.2865605597
Short name T380
Test name
Test status
Simulation time 159649652160 ps
CPU time 341.39 seconds
Started Jan 07 01:06:06 PM PST 24
Finished Jan 07 01:11:50 PM PST 24
Peak memory 200908 kb
Host smart-57da2992-5686-430e-9c07-b54230ec0f7e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865605597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.2865605597
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.2461746140
Short name T166
Test name
Test status
Simulation time 510038183530 ps
CPU time 303.4 seconds
Started Jan 07 01:06:06 PM PST 24
Finished Jan 07 01:11:12 PM PST 24
Peak memory 200888 kb
Host smart-d9028add-34dc-479e-9d6c-2a242d7db069
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461746140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.2461746140
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.2624292333
Short name T405
Test name
Test status
Simulation time 493067719565 ps
CPU time 1163.19 seconds
Started Jan 07 01:06:16 PM PST 24
Finished Jan 07 01:25:40 PM PST 24
Peak memory 200872 kb
Host smart-ca7ce5c1-d663-4aa6-afd0-f58d4b644dd2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624292333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.2624292333
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.487441804
Short name T642
Test name
Test status
Simulation time 23120827816 ps
CPU time 13.94 seconds
Started Jan 07 01:06:00 PM PST 24
Finished Jan 07 01:06:17 PM PST 24
Peak memory 200712 kb
Host smart-255c75e0-de0b-49e9-b6fe-3525126f1329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487441804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.487441804
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.1587245650
Short name T707
Test name
Test status
Simulation time 4479158057 ps
CPU time 2.96 seconds
Started Jan 07 01:06:14 PM PST 24
Finished Jan 07 01:06:18 PM PST 24
Peak memory 200756 kb
Host smart-3a425dde-4754-4115-b99a-3edba6fce82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587245650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.1587245650
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.1006670290
Short name T40
Test name
Test status
Simulation time 4308808433 ps
CPU time 6.07 seconds
Started Jan 07 01:06:05 PM PST 24
Finished Jan 07 01:06:14 PM PST 24
Peak memory 216176 kb
Host smart-0b5c66ff-1aa3-4b09-a62a-2f6c3093f996
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006670290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.1006670290
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.2491983266
Short name T49
Test name
Test status
Simulation time 6076925248 ps
CPU time 15.12 seconds
Started Jan 07 01:06:15 PM PST 24
Finished Jan 07 01:06:32 PM PST 24
Peak memory 200724 kb
Host smart-c7d07e54-40b1-4dba-8964-340d851361bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491983266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.2491983266
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.3565854858
Short name T289
Test name
Test status
Simulation time 263874541115 ps
CPU time 431.54 seconds
Started Jan 07 01:06:03 PM PST 24
Finished Jan 07 01:13:18 PM PST 24
Peak memory 209664 kb
Host smart-2ed63ff2-8827-495c-86a5-4a7a5d8a024f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565854858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
3565854858
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.2102670020
Short name T622
Test name
Test status
Simulation time 412561826 ps
CPU time 1.1 seconds
Started Jan 07 01:07:39 PM PST 24
Finished Jan 07 01:07:43 PM PST 24
Peak memory 200692 kb
Host smart-8f94aee1-0c41-464a-a433-841e421caa30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102670020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.2102670020
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.1106782944
Short name T214
Test name
Test status
Simulation time 327367605623 ps
CPU time 209.9 seconds
Started Jan 07 01:07:39 PM PST 24
Finished Jan 07 01:11:12 PM PST 24
Peak memory 200892 kb
Host smart-3c0f1dfd-d5c3-4e80-b877-066625484d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106782944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.1106782944
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.3600026039
Short name T161
Test name
Test status
Simulation time 487338796212 ps
CPU time 1206.58 seconds
Started Jan 07 01:07:30 PM PST 24
Finished Jan 07 01:27:38 PM PST 24
Peak memory 200900 kb
Host smart-bff409a9-1c5f-44db-acc5-1cdecd16de7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600026039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.3600026039
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.2941719835
Short name T534
Test name
Test status
Simulation time 494784248616 ps
CPU time 546.07 seconds
Started Jan 07 01:07:33 PM PST 24
Finished Jan 07 01:16:42 PM PST 24
Peak memory 200888 kb
Host smart-257ca20b-1f43-4e93-af2e-2e1845fd3d36
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941719835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.2941719835
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.1790928725
Short name T481
Test name
Test status
Simulation time 161464799291 ps
CPU time 184.05 seconds
Started Jan 07 01:07:36 PM PST 24
Finished Jan 07 01:10:44 PM PST 24
Peak memory 200908 kb
Host smart-cdf6c23b-f3ea-438a-9037-2e39b0891693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790928725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.1790928725
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.2279400259
Short name T443
Test name
Test status
Simulation time 327250109436 ps
CPU time 209.76 seconds
Started Jan 07 01:07:35 PM PST 24
Finished Jan 07 01:11:09 PM PST 24
Peak memory 200824 kb
Host smart-9568a69a-a507-43b4-b0e7-0bb958e0c57a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279400259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.2279400259
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.3019892728
Short name T553
Test name
Test status
Simulation time 327555274529 ps
CPU time 154.31 seconds
Started Jan 07 01:07:36 PM PST 24
Finished Jan 07 01:10:14 PM PST 24
Peak memory 200864 kb
Host smart-e93775e0-de57-4f3c-aee1-b029cd36627f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019892728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.3019892728
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.184151317
Short name T437
Test name
Test status
Simulation time 78791860890 ps
CPU time 264.49 seconds
Started Jan 07 01:07:47 PM PST 24
Finished Jan 07 01:12:21 PM PST 24
Peak memory 201272 kb
Host smart-79ba25c4-edad-44db-b47f-7af131ecf9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184151317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.184151317
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.1807025630
Short name T823
Test name
Test status
Simulation time 32350364637 ps
CPU time 20.97 seconds
Started Jan 07 01:07:36 PM PST 24
Finished Jan 07 01:08:01 PM PST 24
Peak memory 200496 kb
Host smart-74967289-1f3e-454b-ab52-82bf93e35f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807025630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.1807025630
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.2232938449
Short name T444
Test name
Test status
Simulation time 4306519855 ps
CPU time 10.95 seconds
Started Jan 07 01:07:38 PM PST 24
Finished Jan 07 01:07:52 PM PST 24
Peak memory 200732 kb
Host smart-049bba69-4622-476b-b87b-2087b6e796b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232938449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.2232938449
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.1016941902
Short name T507
Test name
Test status
Simulation time 5831521262 ps
CPU time 14.29 seconds
Started Jan 07 01:07:28 PM PST 24
Finished Jan 07 01:07:44 PM PST 24
Peak memory 200756 kb
Host smart-e8e9cbaf-cf53-460a-9609-0d9ab48bbef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016941902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.1016941902
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.212722399
Short name T202
Test name
Test status
Simulation time 327712066356 ps
CPU time 672.07 seconds
Started Jan 07 01:07:46 PM PST 24
Finished Jan 07 01:19:06 PM PST 24
Peak memory 200904 kb
Host smart-41bdbaea-a1c6-49fe-876a-bebdf14b8be3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212722399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all.
212722399
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.1945626303
Short name T551
Test name
Test status
Simulation time 407290850 ps
CPU time 0.88 seconds
Started Jan 07 01:07:48 PM PST 24
Finished Jan 07 01:07:58 PM PST 24
Peak memory 200592 kb
Host smart-d6f825c8-7653-4d8d-9f2a-311052861d3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945626303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.1945626303
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.930375726
Short name T789
Test name
Test status
Simulation time 165115138484 ps
CPU time 103.62 seconds
Started Jan 07 01:07:45 PM PST 24
Finished Jan 07 01:09:35 PM PST 24
Peak memory 200812 kb
Host smart-da799f3f-a1d2-4532-90dd-8e9d4383e4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930375726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.930375726
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.3043205864
Short name T308
Test name
Test status
Simulation time 160867052452 ps
CPU time 364.63 seconds
Started Jan 07 01:07:49 PM PST 24
Finished Jan 07 01:14:02 PM PST 24
Peak memory 200968 kb
Host smart-124705ed-8eb5-4bf3-ace3-6c65e9905869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043205864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.3043205864
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.4208118335
Short name T640
Test name
Test status
Simulation time 323536795781 ps
CPU time 742.2 seconds
Started Jan 07 01:07:47 PM PST 24
Finished Jan 07 01:20:17 PM PST 24
Peak memory 200880 kb
Host smart-a8b62873-d721-462f-af44-bd611c0ba7c0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208118335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.4208118335
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.831119929
Short name T108
Test name
Test status
Simulation time 342629968484 ps
CPU time 169.64 seconds
Started Jan 07 01:07:37 PM PST 24
Finished Jan 07 01:10:30 PM PST 24
Peak memory 200804 kb
Host smart-a9a88608-3a61-4d91-9b9f-a6f0f29d9122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831119929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.831119929
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.2669073487
Short name T384
Test name
Test status
Simulation time 489470066998 ps
CPU time 1104.71 seconds
Started Jan 07 01:07:44 PM PST 24
Finished Jan 07 01:26:11 PM PST 24
Peak memory 200900 kb
Host smart-51ea304b-60f3-4484-a6d0-4671ecc775a5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669073487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.2669073487
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.1962752951
Short name T314
Test name
Test status
Simulation time 162004122645 ps
CPU time 89.32 seconds
Started Jan 07 01:07:44 PM PST 24
Finished Jan 07 01:09:16 PM PST 24
Peak memory 201012 kb
Host smart-64082a25-4c1d-4b22-9332-8ec7c1b0119e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962752951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.1962752951
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.2029143896
Short name T797
Test name
Test status
Simulation time 166956815941 ps
CPU time 374.58 seconds
Started Jan 07 01:07:42 PM PST 24
Finished Jan 07 01:14:00 PM PST 24
Peak memory 200812 kb
Host smart-1a156088-4ab1-4854-a5c3-b69e2d21fe5b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029143896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.2029143896
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.1231964581
Short name T184
Test name
Test status
Simulation time 139147233887 ps
CPU time 434.12 seconds
Started Jan 07 01:07:49 PM PST 24
Finished Jan 07 01:15:11 PM PST 24
Peak memory 201404 kb
Host smart-69652ba1-525e-402a-af53-4241d8c7dfdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231964581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.1231964581
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.3915408762
Short name T497
Test name
Test status
Simulation time 44970713688 ps
CPU time 36.45 seconds
Started Jan 07 01:07:49 PM PST 24
Finished Jan 07 01:08:33 PM PST 24
Peak memory 200708 kb
Host smart-1b39d840-0de6-45fe-b82c-ccb3e87d4d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915408762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.3915408762
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.2495975136
Short name T817
Test name
Test status
Simulation time 4448160641 ps
CPU time 3.23 seconds
Started Jan 07 01:07:38 PM PST 24
Finished Jan 07 01:07:45 PM PST 24
Peak memory 200724 kb
Host smart-23d75182-be8b-4c62-b034-717ba086e1d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495975136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.2495975136
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.1402936796
Short name T700
Test name
Test status
Simulation time 5990260173 ps
CPU time 4.14 seconds
Started Jan 07 01:07:45 PM PST 24
Finished Jan 07 01:07:56 PM PST 24
Peak memory 200692 kb
Host smart-73d34599-d844-40a8-bf76-8c2001026b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402936796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.1402936796
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.4123715960
Short name T520
Test name
Test status
Simulation time 520095905 ps
CPU time 1.75 seconds
Started Jan 07 01:07:31 PM PST 24
Finished Jan 07 01:07:35 PM PST 24
Peak memory 200584 kb
Host smart-3ba836d4-dbf6-4a61-9ecd-798d41772653
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123715960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.4123715960
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.4098491776
Short name T706
Test name
Test status
Simulation time 169876744015 ps
CPU time 383.98 seconds
Started Jan 07 01:07:38 PM PST 24
Finished Jan 07 01:14:05 PM PST 24
Peak memory 200716 kb
Host smart-1794e95d-adbd-4d49-933f-bcf38fb4ccc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098491776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.4098491776
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.1048930988
Short name T554
Test name
Test status
Simulation time 322364309574 ps
CPU time 416.16 seconds
Started Jan 07 01:07:35 PM PST 24
Finished Jan 07 01:14:35 PM PST 24
Peak memory 200792 kb
Host smart-568d94a4-90b2-4a1b-b680-f8b8ea44361a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048930988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.1048930988
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.3395356010
Short name T654
Test name
Test status
Simulation time 161580955896 ps
CPU time 116.96 seconds
Started Jan 07 01:07:30 PM PST 24
Finished Jan 07 01:09:29 PM PST 24
Peak memory 200872 kb
Host smart-ff975003-5d4f-49f0-bb9a-20ceb8f3d877
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395356010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.3395356010
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.585849022
Short name T585
Test name
Test status
Simulation time 163963729478 ps
CPU time 48.11 seconds
Started Jan 07 01:07:46 PM PST 24
Finished Jan 07 01:08:43 PM PST 24
Peak memory 200956 kb
Host smart-84d8caca-f2b6-40cd-b6c8-3495469eef08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585849022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.585849022
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.3038615347
Short name T668
Test name
Test status
Simulation time 493975836679 ps
CPU time 420.79 seconds
Started Jan 07 01:07:18 PM PST 24
Finished Jan 07 01:14:20 PM PST 24
Peak memory 200844 kb
Host smart-f8dfd294-5977-4ac2-bba0-e382bb397b18
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038615347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.3038615347
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.1569859199
Short name T812
Test name
Test status
Simulation time 328031250503 ps
CPU time 190.94 seconds
Started Jan 07 01:07:32 PM PST 24
Finished Jan 07 01:10:45 PM PST 24
Peak memory 201048 kb
Host smart-a67ebcc6-36ec-4b49-ac1f-6871677d0dad
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569859199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.1569859199
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.4103307970
Short name T674
Test name
Test status
Simulation time 125815630022 ps
CPU time 641.28 seconds
Started Jan 07 01:07:21 PM PST 24
Finished Jan 07 01:18:07 PM PST 24
Peak memory 201408 kb
Host smart-ed2344ec-8b92-4451-8772-000fcd47472f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103307970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.4103307970
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.1255829024
Short name T376
Test name
Test status
Simulation time 45223186840 ps
CPU time 28.03 seconds
Started Jan 07 01:07:22 PM PST 24
Finished Jan 07 01:07:54 PM PST 24
Peak memory 200760 kb
Host smart-e395fd7c-0395-4896-a88c-a0de84dd4194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255829024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.1255829024
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.143704187
Short name T596
Test name
Test status
Simulation time 3577258751 ps
CPU time 1.09 seconds
Started Jan 07 01:07:34 PM PST 24
Finished Jan 07 01:07:39 PM PST 24
Peak memory 200776 kb
Host smart-dbdc2b27-da92-4fb2-b894-3196a4ac0154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143704187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.143704187
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.125319063
Short name T638
Test name
Test status
Simulation time 5961879763 ps
CPU time 4.34 seconds
Started Jan 07 01:07:48 PM PST 24
Finished Jan 07 01:08:01 PM PST 24
Peak memory 200660 kb
Host smart-91aaf288-5d7c-489f-a1cb-7d589f62dc72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125319063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.125319063
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.4043474812
Short name T720
Test name
Test status
Simulation time 47072344986 ps
CPU time 149.96 seconds
Started Jan 07 01:07:28 PM PST 24
Finished Jan 07 01:10:00 PM PST 24
Peak memory 209592 kb
Host smart-b8029b78-b033-4f2d-add1-7dda10614a43
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043474812 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.4043474812
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.1049654202
Short name T37
Test name
Test status
Simulation time 367715431 ps
CPU time 0.82 seconds
Started Jan 07 01:07:32 PM PST 24
Finished Jan 07 01:07:34 PM PST 24
Peak memory 200692 kb
Host smart-6b1847f4-7899-4a3e-9d55-2ce1b62d8f8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049654202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.1049654202
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.4245658989
Short name T330
Test name
Test status
Simulation time 410893943317 ps
CPU time 462.72 seconds
Started Jan 07 01:07:23 PM PST 24
Finished Jan 07 01:15:09 PM PST 24
Peak memory 200952 kb
Host smart-218f7bbc-121a-40cf-bcb4-b67a9d96c3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245658989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.4245658989
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.3842533051
Short name T694
Test name
Test status
Simulation time 331123319042 ps
CPU time 367.72 seconds
Started Jan 07 01:07:22 PM PST 24
Finished Jan 07 01:13:34 PM PST 24
Peak memory 200872 kb
Host smart-99884ea7-e578-44c2-87d6-abd5b4cbc9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842533051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.3842533051
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.3778861470
Short name T558
Test name
Test status
Simulation time 502812966449 ps
CPU time 247.23 seconds
Started Jan 07 01:07:31 PM PST 24
Finished Jan 07 01:11:40 PM PST 24
Peak memory 200936 kb
Host smart-a85e2223-9882-42f4-b3cd-236007fed694
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778861470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.3778861470
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.2635471235
Short name T725
Test name
Test status
Simulation time 163494496375 ps
CPU time 179.4 seconds
Started Jan 07 01:07:23 PM PST 24
Finished Jan 07 01:10:26 PM PST 24
Peak memory 200860 kb
Host smart-c7c365e4-5ce6-4a81-970b-33a3d12ab28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635471235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.2635471235
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.895770262
Short name T460
Test name
Test status
Simulation time 489230468458 ps
CPU time 604.95 seconds
Started Jan 07 01:07:35 PM PST 24
Finished Jan 07 01:17:43 PM PST 24
Peak memory 200904 kb
Host smart-56ccb87a-a039-4868-9011-2aac86e49759
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=895770262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fixe
d.895770262
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.2251514020
Short name T260
Test name
Test status
Simulation time 163991936446 ps
CPU time 22.2 seconds
Started Jan 07 01:07:28 PM PST 24
Finished Jan 07 01:07:52 PM PST 24
Peak memory 200800 kb
Host smart-181df439-bade-42be-8f07-8cae5aa91e6d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251514020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.2251514020
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.3007055048
Short name T490
Test name
Test status
Simulation time 503173372765 ps
CPU time 1169.6 seconds
Started Jan 07 01:07:32 PM PST 24
Finished Jan 07 01:27:03 PM PST 24
Peak memory 200904 kb
Host smart-e677f0f7-fb1a-4a7f-8278-f5805373a66f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007055048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.3007055048
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.2154267863
Short name T825
Test name
Test status
Simulation time 82081373877 ps
CPU time 427.06 seconds
Started Jan 07 01:07:28 PM PST 24
Finished Jan 07 01:14:37 PM PST 24
Peak memory 201400 kb
Host smart-94f2611c-2ec1-438d-86b7-3e4d15929f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154267863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.2154267863
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.2425187823
Short name T830
Test name
Test status
Simulation time 28936793641 ps
CPU time 71.94 seconds
Started Jan 07 01:07:30 PM PST 24
Finished Jan 07 01:08:43 PM PST 24
Peak memory 200640 kb
Host smart-41ce4990-279c-4a1c-8616-ca93ee2fe5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425187823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.2425187823
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.3999795410
Short name T476
Test name
Test status
Simulation time 3239355378 ps
CPU time 7.15 seconds
Started Jan 07 01:07:32 PM PST 24
Finished Jan 07 01:07:41 PM PST 24
Peak memory 200764 kb
Host smart-52886996-5582-4f5c-bc0f-78ae3ee707e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999795410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.3999795410
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.3808363852
Short name T800
Test name
Test status
Simulation time 5828765316 ps
CPU time 1.51 seconds
Started Jan 07 01:07:33 PM PST 24
Finished Jan 07 01:07:38 PM PST 24
Peak memory 200584 kb
Host smart-2aa7a87e-9b3f-4e9e-aa20-a5d2d3803545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808363852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.3808363852
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.3033536611
Short name T90
Test name
Test status
Simulation time 188988669854 ps
CPU time 112.71 seconds
Started Jan 07 01:07:22 PM PST 24
Finished Jan 07 01:09:19 PM PST 24
Peak memory 200908 kb
Host smart-f42c2c3b-71c5-45a8-b53e-2b8c6cbe480a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033536611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.3033536611
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.1375757763
Short name T196
Test name
Test status
Simulation time 200829502981 ps
CPU time 85.14 seconds
Started Jan 07 01:07:33 PM PST 24
Finished Jan 07 01:09:01 PM PST 24
Peak memory 209184 kb
Host smart-4a19e012-fca0-4012-bede-0d1763d1a3a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375757763 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.1375757763
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.3579348200
Short name T676
Test name
Test status
Simulation time 530443419 ps
CPU time 1.29 seconds
Started Jan 07 01:07:39 PM PST 24
Finished Jan 07 01:07:43 PM PST 24
Peak memory 200728 kb
Host smart-97c3e942-bfb1-49aa-a96f-e00e48b96020
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579348200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.3579348200
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.671605002
Short name T234
Test name
Test status
Simulation time 164093618304 ps
CPU time 193.56 seconds
Started Jan 07 01:07:36 PM PST 24
Finished Jan 07 01:10:53 PM PST 24
Peak memory 200908 kb
Host smart-94e697df-df91-4eb6-94ef-b0b663cb2cbb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671605002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gati
ng.671605002
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.2988349847
Short name T685
Test name
Test status
Simulation time 332813284982 ps
CPU time 201.31 seconds
Started Jan 07 01:07:35 PM PST 24
Finished Jan 07 01:11:00 PM PST 24
Peak memory 200808 kb
Host smart-5080033c-7e56-43ae-bcc8-e542b9a4909f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988349847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.2988349847
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.3148297708
Short name T315
Test name
Test status
Simulation time 332718572306 ps
CPU time 809.73 seconds
Started Jan 07 01:07:31 PM PST 24
Finished Jan 07 01:21:03 PM PST 24
Peak memory 200876 kb
Host smart-f8159f4f-2980-4aad-a16d-2cc87f2fdbe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148297708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.3148297708
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.1088053776
Short name T501
Test name
Test status
Simulation time 488771586802 ps
CPU time 1182.2 seconds
Started Jan 07 01:07:30 PM PST 24
Finished Jan 07 01:27:14 PM PST 24
Peak memory 200840 kb
Host smart-88ac3be3-2be4-49c9-8a30-e8eaba1465d8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088053776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.1088053776
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.4053932820
Short name T319
Test name
Test status
Simulation time 167396451877 ps
CPU time 104.96 seconds
Started Jan 07 01:07:36 PM PST 24
Finished Jan 07 01:09:24 PM PST 24
Peak memory 201004 kb
Host smart-5252fead-0bb1-4f43-963d-9bd53321f88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053932820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.4053932820
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.217165698
Short name T462
Test name
Test status
Simulation time 326445473662 ps
CPU time 709.69 seconds
Started Jan 07 01:07:31 PM PST 24
Finished Jan 07 01:19:23 PM PST 24
Peak memory 200912 kb
Host smart-2021bfec-bc19-4e41-8baa-14c1bf11e9a1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=217165698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fixe
d.217165698
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.3563414807
Short name T564
Test name
Test status
Simulation time 495642985315 ps
CPU time 651.17 seconds
Started Jan 07 01:07:34 PM PST 24
Finished Jan 07 01:18:29 PM PST 24
Peak memory 200856 kb
Host smart-1cd3217a-22c4-425b-afb7-470e7e3ce9ff
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563414807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.3563414807
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.2913363845
Short name T684
Test name
Test status
Simulation time 78469483827 ps
CPU time 413.51 seconds
Started Jan 07 01:07:45 PM PST 24
Finished Jan 07 01:14:45 PM PST 24
Peak memory 201352 kb
Host smart-8039effa-15c8-4bf7-9a85-c34337d12f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913363845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.2913363845
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.2781729615
Short name T586
Test name
Test status
Simulation time 38703679760 ps
CPU time 29.61 seconds
Started Jan 07 01:07:37 PM PST 24
Finished Jan 07 01:08:11 PM PST 24
Peak memory 200664 kb
Host smart-23a9dbd5-c121-4a6e-91f0-27c3b65c0c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781729615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.2781729615
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.779777331
Short name T758
Test name
Test status
Simulation time 4801221494 ps
CPU time 2.52 seconds
Started Jan 07 01:07:36 PM PST 24
Finished Jan 07 01:07:42 PM PST 24
Peak memory 200636 kb
Host smart-2d6455ad-4db8-458f-8cf8-92e00ddaca58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779777331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.779777331
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.1069001699
Short name T689
Test name
Test status
Simulation time 5910736200 ps
CPU time 13.38 seconds
Started Jan 07 01:07:20 PM PST 24
Finished Jan 07 01:07:38 PM PST 24
Peak memory 200584 kb
Host smart-3d726fec-7493-4264-86ff-27f255554f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069001699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.1069001699
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.2936371416
Short name T487
Test name
Test status
Simulation time 491576077 ps
CPU time 1.71 seconds
Started Jan 07 01:07:48 PM PST 24
Finished Jan 07 01:07:59 PM PST 24
Peak memory 200616 kb
Host smart-2d0ee680-e5b5-4cec-8d5d-0da18a111e2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936371416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.2936371416
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.351916397
Short name T299
Test name
Test status
Simulation time 492272381974 ps
CPU time 1054.74 seconds
Started Jan 07 01:07:46 PM PST 24
Finished Jan 07 01:25:30 PM PST 24
Peak memory 200892 kb
Host smart-44d7f583-44ac-4c57-95b9-b88d8c273745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351916397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.351916397
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.1135377738
Short name T248
Test name
Test status
Simulation time 332365922670 ps
CPU time 375.21 seconds
Started Jan 07 01:07:44 PM PST 24
Finished Jan 07 01:14:07 PM PST 24
Peak memory 200944 kb
Host smart-6ed7ed6d-66a5-4d95-85e5-533b80b3d891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135377738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.1135377738
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.2504199812
Short name T644
Test name
Test status
Simulation time 494329103787 ps
CPU time 1171.47 seconds
Started Jan 07 01:07:38 PM PST 24
Finished Jan 07 01:27:13 PM PST 24
Peak memory 200832 kb
Host smart-a4e624a2-83d3-442e-93dd-a69c5c0d7adc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504199812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.2504199812
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.563900161
Short name T836
Test name
Test status
Simulation time 166042894925 ps
CPU time 378.75 seconds
Started Jan 07 01:07:44 PM PST 24
Finished Jan 07 01:14:05 PM PST 24
Peak memory 200820 kb
Host smart-5ab5e2cf-0d75-4f64-b88c-1c7dd9cb4c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563900161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.563900161
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.1993784284
Short name T514
Test name
Test status
Simulation time 163495406434 ps
CPU time 195.84 seconds
Started Jan 07 01:07:50 PM PST 24
Finished Jan 07 01:11:13 PM PST 24
Peak memory 200972 kb
Host smart-203689fb-5c2b-440e-a6fd-bab1604e0acd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993784284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.1993784284
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.1372637249
Short name T328
Test name
Test status
Simulation time 328698913562 ps
CPU time 200.09 seconds
Started Jan 07 01:07:48 PM PST 24
Finished Jan 07 01:11:17 PM PST 24
Peak memory 200988 kb
Host smart-691197f4-7d6e-4921-aff2-7a8b46fce61b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372637249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.1372637249
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.2568645364
Short name T675
Test name
Test status
Simulation time 164963690552 ps
CPU time 383.29 seconds
Started Jan 07 01:07:43 PM PST 24
Finished Jan 07 01:14:09 PM PST 24
Peak memory 200956 kb
Host smart-c5f2058a-5b3f-4cd2-ad5e-a7333b272608
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568645364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.2568645364
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.786654462
Short name T535
Test name
Test status
Simulation time 38904905363 ps
CPU time 89.04 seconds
Started Jan 07 01:07:37 PM PST 24
Finished Jan 07 01:09:09 PM PST 24
Peak memory 200756 kb
Host smart-5429aaf8-3b62-438d-b84c-f2b3766afe4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786654462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.786654462
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.646041019
Short name T541
Test name
Test status
Simulation time 3712584054 ps
CPU time 8.61 seconds
Started Jan 07 01:07:34 PM PST 24
Finished Jan 07 01:07:46 PM PST 24
Peak memory 200752 kb
Host smart-4fd36996-cfc1-483b-88db-2f8147b3ea2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646041019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.646041019
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.2275284168
Short name T385
Test name
Test status
Simulation time 5657573490 ps
CPU time 15.11 seconds
Started Jan 07 01:07:48 PM PST 24
Finished Jan 07 01:08:12 PM PST 24
Peak memory 200700 kb
Host smart-1dcecae4-5c75-4e33-9e27-41c869c4119b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275284168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.2275284168
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.500982517
Short name T165
Test name
Test status
Simulation time 324558536982 ps
CPU time 772.93 seconds
Started Jan 07 01:07:49 PM PST 24
Finished Jan 07 01:20:50 PM PST 24
Peak memory 200844 kb
Host smart-e81d3d32-0c5f-4b38-adbd-03c9857ffcaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500982517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all.
500982517
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.3118387385
Short name T737
Test name
Test status
Simulation time 1072160667051 ps
CPU time 1063.4 seconds
Started Jan 07 01:07:44 PM PST 24
Finished Jan 07 01:25:31 PM PST 24
Peak memory 209600 kb
Host smart-088fd9f6-3c48-4782-849c-4fb11ce2074b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118387385 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.3118387385
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.3803757118
Short name T778
Test name
Test status
Simulation time 435865738 ps
CPU time 1.61 seconds
Started Jan 07 01:07:33 PM PST 24
Finished Jan 07 01:07:38 PM PST 24
Peak memory 200604 kb
Host smart-ad8e526c-435b-48c1-a3e9-bcf0b7e1c9dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803757118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.3803757118
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.376269373
Short name T739
Test name
Test status
Simulation time 482657102113 ps
CPU time 165.13 seconds
Started Jan 07 01:07:54 PM PST 24
Finished Jan 07 01:10:46 PM PST 24
Peak memory 200852 kb
Host smart-b337e152-f547-49aa-8d91-e614d3bf4605
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376269373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gati
ng.376269373
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.1433147070
Short name T316
Test name
Test status
Simulation time 332089200134 ps
CPU time 376.9 seconds
Started Jan 07 01:07:50 PM PST 24
Finished Jan 07 01:14:14 PM PST 24
Peak memory 200984 kb
Host smart-b516de4b-546c-4062-a732-61655ca8a9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433147070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.1433147070
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.1037051937
Short name T20
Test name
Test status
Simulation time 331673982090 ps
CPU time 739.27 seconds
Started Jan 07 01:07:44 PM PST 24
Finished Jan 07 01:20:11 PM PST 24
Peak memory 200692 kb
Host smart-51eb1e9c-24ec-4eff-a394-e64ba8df77e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037051937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.1037051937
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.4115473651
Short name T456
Test name
Test status
Simulation time 163856209619 ps
CPU time 108.44 seconds
Started Jan 07 01:07:49 PM PST 24
Finished Jan 07 01:09:45 PM PST 24
Peak memory 200772 kb
Host smart-4689f649-42b7-4d4f-a4df-b33c7ea3839a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115473651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.4115473651
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.421204986
Short name T272
Test name
Test status
Simulation time 327404292947 ps
CPU time 695.07 seconds
Started Jan 07 01:07:48 PM PST 24
Finished Jan 07 01:19:32 PM PST 24
Peak memory 200368 kb
Host smart-6349e647-b0e1-4fcd-af84-1fcc3ed845f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421204986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.421204986
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.937674759
Short name T144
Test name
Test status
Simulation time 159083053631 ps
CPU time 90.72 seconds
Started Jan 07 01:07:49 PM PST 24
Finished Jan 07 01:09:28 PM PST 24
Peak memory 200784 kb
Host smart-7e14da77-4b6b-4280-a811-8876c617a9a7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=937674759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fixe
d.937674759
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.2931402636
Short name T536
Test name
Test status
Simulation time 168230814826 ps
CPU time 379.02 seconds
Started Jan 07 01:07:55 PM PST 24
Finished Jan 07 01:14:20 PM PST 24
Peak memory 200816 kb
Host smart-5c59d56b-1429-49b7-9d4c-d3f0164b3c5c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931402636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.2931402636
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.3313927538
Short name T465
Test name
Test status
Simulation time 63593913473 ps
CPU time 236.37 seconds
Started Jan 07 01:07:22 PM PST 24
Finished Jan 07 01:11:22 PM PST 24
Peak memory 201392 kb
Host smart-9daa6019-ee1e-4b1f-9a3b-7ff8b631cd66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313927538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.3313927538
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.3153577220
Short name T793
Test name
Test status
Simulation time 24295882940 ps
CPU time 54.36 seconds
Started Jan 07 01:07:49 PM PST 24
Finished Jan 07 01:08:51 PM PST 24
Peak memory 200756 kb
Host smart-f176bc24-0224-4049-ae5f-25a2f4a5152a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153577220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.3153577220
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.1257603671
Short name T718
Test name
Test status
Simulation time 2978831262 ps
CPU time 2.54 seconds
Started Jan 07 01:07:47 PM PST 24
Finished Jan 07 01:07:59 PM PST 24
Peak memory 200164 kb
Host smart-e74f3607-b9b5-4f77-bc0e-7c001f1f6d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257603671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.1257603671
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.1034850109
Short name T381
Test name
Test status
Simulation time 5820593994 ps
CPU time 5.65 seconds
Started Jan 07 01:07:48 PM PST 24
Finished Jan 07 01:08:03 PM PST 24
Peak memory 200176 kb
Host smart-371f51c8-2fdf-4ec0-8bb9-d42292457f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034850109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.1034850109
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.3017061428
Short name T30
Test name
Test status
Simulation time 140921745238 ps
CPU time 417.42 seconds
Started Jan 07 01:07:28 PM PST 24
Finished Jan 07 01:14:27 PM PST 24
Peak memory 201292 kb
Host smart-dd52d989-27d7-4a41-851c-5b51efd6bd15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017061428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.3017061428
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.3207548975
Short name T291
Test name
Test status
Simulation time 64853526422 ps
CPU time 142.71 seconds
Started Jan 07 01:07:23 PM PST 24
Finished Jan 07 01:09:49 PM PST 24
Peak memory 201032 kb
Host smart-1a9ce156-a9b3-4522-b607-ffb4e0ba1c49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207548975 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.3207548975
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.4106943100
Short name T796
Test name
Test status
Simulation time 493484360 ps
CPU time 0.78 seconds
Started Jan 07 01:07:37 PM PST 24
Finished Jan 07 01:07:42 PM PST 24
Peak memory 200668 kb
Host smart-1596db08-9394-4ae2-9457-220fdbf08c94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106943100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.4106943100
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.4200115450
Short name T279
Test name
Test status
Simulation time 160274697381 ps
CPU time 176.4 seconds
Started Jan 07 01:07:33 PM PST 24
Finished Jan 07 01:10:33 PM PST 24
Peak memory 200840 kb
Host smart-0fc9ec02-153c-4c0f-9730-f999120dbb33
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200115450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.4200115450
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.2188389021
Short name T121
Test name
Test status
Simulation time 490823667840 ps
CPU time 308.38 seconds
Started Jan 07 01:07:22 PM PST 24
Finished Jan 07 01:12:34 PM PST 24
Peak memory 200852 kb
Host smart-9212d1c3-e6c8-4e8c-810a-b3a52ca1b95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188389021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.2188389021
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.943397170
Short name T411
Test name
Test status
Simulation time 162653556138 ps
CPU time 300.5 seconds
Started Jan 07 01:07:28 PM PST 24
Finished Jan 07 01:12:30 PM PST 24
Peak memory 200832 kb
Host smart-577581a8-8325-4721-afba-1475409ec012
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=943397170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrup
t_fixed.943397170
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.593256934
Short name T222
Test name
Test status
Simulation time 487394321217 ps
CPU time 1119.77 seconds
Started Jan 07 01:07:35 PM PST 24
Finished Jan 07 01:26:19 PM PST 24
Peak memory 200832 kb
Host smart-a59ef5f8-0581-4ce3-b5f2-7af549140b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593256934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.593256934
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.2090530459
Short name T455
Test name
Test status
Simulation time 167847870233 ps
CPU time 101.41 seconds
Started Jan 07 01:07:33 PM PST 24
Finished Jan 07 01:09:16 PM PST 24
Peak memory 200800 kb
Host smart-45e247b6-5361-4a44-bc56-9ece6f7a547a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090530459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.2090530459
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.2553345864
Short name T477
Test name
Test status
Simulation time 337459551763 ps
CPU time 793.56 seconds
Started Jan 07 01:07:28 PM PST 24
Finished Jan 07 01:20:44 PM PST 24
Peak memory 200848 kb
Host smart-145a9ac4-2816-4939-bca6-da8e8fc01a28
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553345864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.2553345864
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.3888483627
Short name T516
Test name
Test status
Simulation time 104284282890 ps
CPU time 413.81 seconds
Started Jan 07 01:07:34 PM PST 24
Finished Jan 07 01:14:31 PM PST 24
Peak memory 201132 kb
Host smart-d72609bf-a85a-4f5a-9a6b-e0456e0466df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888483627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.3888483627
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.1185629706
Short name T576
Test name
Test status
Simulation time 24996097270 ps
CPU time 8.18 seconds
Started Jan 07 01:07:35 PM PST 24
Finished Jan 07 01:07:47 PM PST 24
Peak memory 200704 kb
Host smart-72e96175-4420-43a2-bcf4-bcb330a65220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185629706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.1185629706
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.310450042
Short name T489
Test name
Test status
Simulation time 4966439703 ps
CPU time 3.3 seconds
Started Jan 07 01:07:35 PM PST 24
Finished Jan 07 01:07:42 PM PST 24
Peak memory 200720 kb
Host smart-c5778528-6c66-49f3-bf21-c1585ffaba5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310450042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.310450042
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.3376916583
Short name T832
Test name
Test status
Simulation time 6139654229 ps
CPU time 4.8 seconds
Started Jan 07 01:07:21 PM PST 24
Finished Jan 07 01:07:30 PM PST 24
Peak memory 200588 kb
Host smart-6cc4e78c-5c51-4636-a5df-74164b7e2d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376916583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.3376916583
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.2384462690
Short name T697
Test name
Test status
Simulation time 5079338782 ps
CPU time 1.66 seconds
Started Jan 07 01:07:34 PM PST 24
Finished Jan 07 01:07:39 PM PST 24
Peak memory 200668 kb
Host smart-d9d1b59a-967f-4633-8616-44c0cb37e2a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384462690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.2384462690
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.709445119
Short name T155
Test name
Test status
Simulation time 31403593913 ps
CPU time 78.93 seconds
Started Jan 07 01:07:37 PM PST 24
Finished Jan 07 01:08:59 PM PST 24
Peak memory 209572 kb
Host smart-aef64cdf-d169-4356-ac91-dd241403ac2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709445119 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.709445119
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.1774754084
Short name T651
Test name
Test status
Simulation time 405549467 ps
CPU time 1.61 seconds
Started Jan 07 01:07:35 PM PST 24
Finished Jan 07 01:07:41 PM PST 24
Peak memory 200632 kb
Host smart-e5b03857-d73e-4a7f-b517-52e4cb27ca24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774754084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.1774754084
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.3335663002
Short name T302
Test name
Test status
Simulation time 336711499291 ps
CPU time 749.5 seconds
Started Jan 07 01:07:38 PM PST 24
Finished Jan 07 01:20:11 PM PST 24
Peak memory 200720 kb
Host smart-14bc6c2e-cbaf-4d99-9810-e6176d9eeb6f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335663002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.3335663002
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.395179845
Short name T134
Test name
Test status
Simulation time 330718888586 ps
CPU time 203.16 seconds
Started Jan 07 01:07:37 PM PST 24
Finished Jan 07 01:11:04 PM PST 24
Peak memory 200752 kb
Host smart-688a0936-31ba-4b0d-a9c1-c1e9c84785c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395179845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.395179845
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.3053448020
Short name T494
Test name
Test status
Simulation time 164582313607 ps
CPU time 100.16 seconds
Started Jan 07 01:07:33 PM PST 24
Finished Jan 07 01:09:16 PM PST 24
Peak memory 200904 kb
Host smart-33ae6268-ebcd-4013-a81d-6f9b16131014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053448020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.3053448020
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.3562132634
Short name T421
Test name
Test status
Simulation time 321788097113 ps
CPU time 737.07 seconds
Started Jan 07 01:07:34 PM PST 24
Finished Jan 07 01:19:56 PM PST 24
Peak memory 200956 kb
Host smart-9b96b56b-08ca-40ec-ac12-8460e020c90c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562132634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.3562132634
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.2279315129
Short name T156
Test name
Test status
Simulation time 324600558422 ps
CPU time 158.01 seconds
Started Jan 07 01:07:36 PM PST 24
Finished Jan 07 01:10:18 PM PST 24
Peak memory 200848 kb
Host smart-6f19e3c5-7baa-409c-bf7d-a0449ae04d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279315129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.2279315129
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.3680407714
Short name T634
Test name
Test status
Simulation time 327987652827 ps
CPU time 773.63 seconds
Started Jan 07 01:07:32 PM PST 24
Finished Jan 07 01:20:28 PM PST 24
Peak memory 200840 kb
Host smart-833a55f5-6934-4628-940e-371a3bdec9d2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680407714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.3680407714
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.1002879625
Short name T130
Test name
Test status
Simulation time 327316372336 ps
CPU time 741.17 seconds
Started Jan 07 01:07:34 PM PST 24
Finished Jan 07 01:19:58 PM PST 24
Peak memory 200912 kb
Host smart-2db5f159-bdd9-4fd3-b0fa-b25951efa894
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002879625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.1002879625
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.3403934551
Short name T431
Test name
Test status
Simulation time 489941311884 ps
CPU time 516.95 seconds
Started Jan 07 01:07:36 PM PST 24
Finished Jan 07 01:16:16 PM PST 24
Peak memory 200904 kb
Host smart-5435c71b-9320-43c7-ac60-081b4fa38506
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403934551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.3403934551
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.3740410056
Short name T395
Test name
Test status
Simulation time 92117064989 ps
CPU time 457.5 seconds
Started Jan 07 01:07:33 PM PST 24
Finished Jan 07 01:15:14 PM PST 24
Peak memory 201328 kb
Host smart-9a21ef75-eab8-42e2-843c-15e1e31ec5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740410056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.3740410056
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.2871031867
Short name T661
Test name
Test status
Simulation time 43703010860 ps
CPU time 92.14 seconds
Started Jan 07 01:07:37 PM PST 24
Finished Jan 07 01:09:13 PM PST 24
Peak memory 200712 kb
Host smart-974fc25f-88b7-478b-8f52-000deef4ca9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871031867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.2871031867
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.1853211815
Short name T388
Test name
Test status
Simulation time 4587535010 ps
CPU time 9.83 seconds
Started Jan 07 01:07:34 PM PST 24
Finished Jan 07 01:07:48 PM PST 24
Peak memory 200624 kb
Host smart-cb1f38c2-9e62-4acc-8050-ac129730d945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853211815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.1853211815
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.1117410480
Short name T803
Test name
Test status
Simulation time 5994249535 ps
CPU time 5.64 seconds
Started Jan 07 01:07:35 PM PST 24
Finished Jan 07 01:07:45 PM PST 24
Peak memory 200692 kb
Host smart-be84c028-799f-4ca8-b018-95fd8be0400c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117410480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.1117410480
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.1070179750
Short name T629
Test name
Test status
Simulation time 28451960759 ps
CPU time 65.46 seconds
Started Jan 07 01:07:35 PM PST 24
Finished Jan 07 01:08:44 PM PST 24
Peak memory 200692 kb
Host smart-70ba0169-be51-44be-96b5-90ef85ca7534
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070179750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.1070179750
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.1651104082
Short name T454
Test name
Test status
Simulation time 500628129 ps
CPU time 1.74 seconds
Started Jan 07 01:07:43 PM PST 24
Finished Jan 07 01:07:48 PM PST 24
Peak memory 200700 kb
Host smart-c6547e71-69e4-4068-8c5d-7bb078d32a84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651104082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.1651104082
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.1501757816
Short name T313
Test name
Test status
Simulation time 330580420336 ps
CPU time 186.17 seconds
Started Jan 07 01:07:38 PM PST 24
Finished Jan 07 01:10:47 PM PST 24
Peak memory 200932 kb
Host smart-41f2f363-1fd0-4a00-924d-47a4916a86b3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501757816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.1501757816
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.3816943790
Short name T616
Test name
Test status
Simulation time 167402728710 ps
CPU time 410.76 seconds
Started Jan 07 01:07:35 PM PST 24
Finished Jan 07 01:14:30 PM PST 24
Peak memory 200868 kb
Host smart-e64dda6d-17b5-4c47-b68f-4894f7a8b08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816943790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.3816943790
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.1246018819
Short name T115
Test name
Test status
Simulation time 485061978066 ps
CPU time 1089.11 seconds
Started Jan 07 01:07:34 PM PST 24
Finished Jan 07 01:25:47 PM PST 24
Peak memory 200852 kb
Host smart-11ac11b8-ba1a-4a83-bd6e-9ab41e576b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246018819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.1246018819
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.2300790131
Short name T463
Test name
Test status
Simulation time 170088676930 ps
CPU time 100.56 seconds
Started Jan 07 01:07:37 PM PST 24
Finished Jan 07 01:09:21 PM PST 24
Peak memory 200920 kb
Host smart-2e5b40bf-b63e-4f15-80a5-6e2da5e017de
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300790131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.2300790131
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.687167302
Short name T223
Test name
Test status
Simulation time 327208294019 ps
CPU time 656.85 seconds
Started Jan 07 01:07:36 PM PST 24
Finished Jan 07 01:18:36 PM PST 24
Peak memory 200828 kb
Host smart-68dca17e-4435-433c-b79b-2d32b48eac1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687167302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.687167302
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.2632811728
Short name T578
Test name
Test status
Simulation time 482179379283 ps
CPU time 177.05 seconds
Started Jan 07 01:07:31 PM PST 24
Finished Jan 07 01:10:30 PM PST 24
Peak memory 200852 kb
Host smart-45d28fe6-ea8e-4567-bb55-e958a48c9a83
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632811728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.2632811728
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.447210003
Short name T271
Test name
Test status
Simulation time 487235595276 ps
CPU time 1004.77 seconds
Started Jan 07 01:07:36 PM PST 24
Finished Jan 07 01:24:24 PM PST 24
Peak memory 200840 kb
Host smart-bbb7c361-261c-46d5-a767-9a1f7fef5846
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447210003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_
wakeup.447210003
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.2343471662
Short name T390
Test name
Test status
Simulation time 332021759111 ps
CPU time 384.09 seconds
Started Jan 07 01:07:33 PM PST 24
Finished Jan 07 01:14:01 PM PST 24
Peak memory 200828 kb
Host smart-349633b6-97c4-454a-9ca9-ee9bff9a9a73
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343471662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.2343471662
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.416985710
Short name T611
Test name
Test status
Simulation time 85223228939 ps
CPU time 331.88 seconds
Started Jan 07 01:07:35 PM PST 24
Finished Jan 07 01:13:11 PM PST 24
Peak memory 201532 kb
Host smart-5dfcea25-1ce9-47e7-9e1f-660e4e539686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416985710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.416985710
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.3480676958
Short name T607
Test name
Test status
Simulation time 25715700025 ps
CPU time 49.73 seconds
Started Jan 07 01:07:32 PM PST 24
Finished Jan 07 01:08:24 PM PST 24
Peak memory 200684 kb
Host smart-af6849ae-e5b4-45d2-99d6-aa7b6020f275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480676958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.3480676958
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.1572095076
Short name T813
Test name
Test status
Simulation time 3344246761 ps
CPU time 1.34 seconds
Started Jan 07 01:07:36 PM PST 24
Finished Jan 07 01:07:41 PM PST 24
Peak memory 200684 kb
Host smart-91be46d1-0e29-4477-83b0-18847b2019ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572095076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.1572095076
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.4066303305
Short name T399
Test name
Test status
Simulation time 6062520885 ps
CPU time 14.66 seconds
Started Jan 07 01:07:39 PM PST 24
Finished Jan 07 01:07:56 PM PST 24
Peak memory 200684 kb
Host smart-ba4aeb1d-1805-4e7d-a9b5-158cb62ba08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066303305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.4066303305
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.1114745728
Short name T176
Test name
Test status
Simulation time 118790913051 ps
CPU time 423.13 seconds
Started Jan 07 01:07:33 PM PST 24
Finished Jan 07 01:14:40 PM PST 24
Peak memory 201340 kb
Host smart-1505db9a-0c03-42ba-9696-9a8d3331db01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114745728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.1114745728
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.450536741
Short name T229
Test name
Test status
Simulation time 24478903405 ps
CPU time 74.92 seconds
Started Jan 07 01:07:36 PM PST 24
Finished Jan 07 01:08:54 PM PST 24
Peak memory 209540 kb
Host smart-989166ef-8ca0-4b69-98a2-be5199fcd36b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450536741 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.450536741
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.2375036872
Short name T770
Test name
Test status
Simulation time 372187165 ps
CPU time 1.38 seconds
Started Jan 07 01:05:56 PM PST 24
Finished Jan 07 01:06:01 PM PST 24
Peak memory 200708 kb
Host smart-756f0c72-051d-4fc4-a236-136c0780be4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375036872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.2375036872
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.638634722
Short name T113
Test name
Test status
Simulation time 493808019204 ps
CPU time 499.33 seconds
Started Jan 07 01:06:07 PM PST 24
Finished Jan 07 01:14:28 PM PST 24
Peak memory 200724 kb
Host smart-da3af3d1-c485-4b6a-8d2e-1364604997be
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638634722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gatin
g.638634722
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.2283774251
Short name T764
Test name
Test status
Simulation time 167318911441 ps
CPU time 39.42 seconds
Started Jan 07 01:06:13 PM PST 24
Finished Jan 07 01:06:54 PM PST 24
Peak memory 200956 kb
Host smart-a62822e7-14b6-44f2-8ee5-92e2c7b294b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283774251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.2283774251
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.2130675705
Short name T612
Test name
Test status
Simulation time 166633588960 ps
CPU time 35.68 seconds
Started Jan 07 01:06:06 PM PST 24
Finished Jan 07 01:06:44 PM PST 24
Peak memory 200844 kb
Host smart-774f3a7f-5fb1-4436-9d82-31f9de972717
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130675705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.2130675705
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.1897628931
Short name T261
Test name
Test status
Simulation time 330719388998 ps
CPU time 189.35 seconds
Started Jan 07 01:06:07 PM PST 24
Finished Jan 07 01:09:18 PM PST 24
Peak memory 200904 kb
Host smart-8213f320-eac0-45b2-923e-9167ec988f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897628931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.1897628931
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.1772055419
Short name T472
Test name
Test status
Simulation time 169612430173 ps
CPU time 36.75 seconds
Started Jan 07 01:06:05 PM PST 24
Finished Jan 07 01:06:45 PM PST 24
Peak memory 200892 kb
Host smart-2527b1c2-f427-4fdb-9c61-f9df00ed0019
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772055419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.1772055419
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.2016303852
Short name T212
Test name
Test status
Simulation time 169507207809 ps
CPU time 413.32 seconds
Started Jan 07 01:05:58 PM PST 24
Finished Jan 07 01:12:54 PM PST 24
Peak memory 200892 kb
Host smart-846e94f6-f02c-4893-8303-d46e62fb78ef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016303852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.2016303852
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.236793251
Short name T415
Test name
Test status
Simulation time 163189220324 ps
CPU time 100.27 seconds
Started Jan 07 01:06:22 PM PST 24
Finished Jan 07 01:08:04 PM PST 24
Peak memory 200896 kb
Host smart-ce5ac55e-553d-4506-9926-ce9a5f68b431
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236793251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.a
dc_ctrl_filters_wakeup_fixed.236793251
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.957740241
Short name T776
Test name
Test status
Simulation time 102865244001 ps
CPU time 521.05 seconds
Started Jan 07 01:06:20 PM PST 24
Finished Jan 07 01:15:02 PM PST 24
Peak memory 201324 kb
Host smart-ef4826c3-e18b-4110-8fd0-16ba8498fa6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957740241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.957740241
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.2732469628
Short name T496
Test name
Test status
Simulation time 31341024194 ps
CPU time 18.6 seconds
Started Jan 07 01:06:10 PM PST 24
Finished Jan 07 01:06:30 PM PST 24
Peak memory 200704 kb
Host smart-f28eebd0-f4d7-48a3-9414-bef3829237f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732469628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.2732469628
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.3792611784
Short name T482
Test name
Test status
Simulation time 2626106566 ps
CPU time 3.12 seconds
Started Jan 07 01:05:58 PM PST 24
Finished Jan 07 01:06:04 PM PST 24
Peak memory 200748 kb
Host smart-b4064e71-361c-4a92-b017-fc501e777bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792611784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.3792611784
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.973507514
Short name T498
Test name
Test status
Simulation time 5881411314 ps
CPU time 4.38 seconds
Started Jan 07 01:06:11 PM PST 24
Finished Jan 07 01:06:17 PM PST 24
Peak memory 200656 kb
Host smart-aeeae132-8698-4710-82a8-c3787da8bbab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973507514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.973507514
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.3230955860
Short name T185
Test name
Test status
Simulation time 266258805917 ps
CPU time 908.29 seconds
Started Jan 07 01:06:15 PM PST 24
Finished Jan 07 01:21:25 PM PST 24
Peak memory 217800 kb
Host smart-f683ecb3-2c5f-4876-a3e1-c65ed15f734e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230955860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
3230955860
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.851511676
Short name T731
Test name
Test status
Simulation time 133794842964 ps
CPU time 199.16 seconds
Started Jan 07 01:06:04 PM PST 24
Finished Jan 07 01:09:26 PM PST 24
Peak memory 209524 kb
Host smart-edbbe08d-4e75-4233-87bf-d1922a719cb0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851511676 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.851511676
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.4116540197
Short name T794
Test name
Test status
Simulation time 489483884 ps
CPU time 1.14 seconds
Started Jan 07 01:07:54 PM PST 24
Finished Jan 07 01:08:02 PM PST 24
Peak memory 200676 kb
Host smart-8f5e0de9-c024-4d93-8512-ccd68c847b96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116540197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.4116540197
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.1064186907
Short name T653
Test name
Test status
Simulation time 160770690247 ps
CPU time 384.08 seconds
Started Jan 07 01:07:38 PM PST 24
Finished Jan 07 01:14:05 PM PST 24
Peak memory 200872 kb
Host smart-4a703a63-7bd7-4af3-9f4e-d9a2538064c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064186907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.1064186907
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.944502306
Short name T769
Test name
Test status
Simulation time 320222622631 ps
CPU time 208.99 seconds
Started Jan 07 01:07:42 PM PST 24
Finished Jan 07 01:11:14 PM PST 24
Peak memory 200844 kb
Host smart-81ec14e4-5b77-421e-9bdf-c37a7c2028ba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=944502306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrup
t_fixed.944502306
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.2918070546
Short name T99
Test name
Test status
Simulation time 490438669351 ps
CPU time 593.77 seconds
Started Jan 07 01:07:43 PM PST 24
Finished Jan 07 01:17:39 PM PST 24
Peak memory 200780 kb
Host smart-5ac4d176-3862-447b-92c9-0a872fef867c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918070546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.2918070546
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.949073900
Short name T461
Test name
Test status
Simulation time 476993595895 ps
CPU time 1060.62 seconds
Started Jan 07 01:07:43 PM PST 24
Finished Jan 07 01:25:27 PM PST 24
Peak memory 200840 kb
Host smart-0c6d36e9-da5c-4120-93a6-f71dcbceef4a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=949073900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fixe
d.949073900
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.3937065772
Short name T255
Test name
Test status
Simulation time 496253598231 ps
CPU time 1172.47 seconds
Started Jan 07 01:07:43 PM PST 24
Finished Jan 07 01:27:18 PM PST 24
Peak memory 200736 kb
Host smart-f711de79-c567-4266-8f63-8a31ed673eda
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937065772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.3937065772
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.4001056912
Short name T406
Test name
Test status
Simulation time 500559040066 ps
CPU time 1019.14 seconds
Started Jan 07 01:07:46 PM PST 24
Finished Jan 07 01:24:53 PM PST 24
Peak memory 200912 kb
Host smart-7198107b-8787-4b1e-9523-8062fd87e103
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001056912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.4001056912
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.3258712135
Short name T775
Test name
Test status
Simulation time 106187015359 ps
CPU time 443.64 seconds
Started Jan 07 01:07:50 PM PST 24
Finished Jan 07 01:15:21 PM PST 24
Peak memory 201308 kb
Host smart-ba0c2efb-f718-4310-8f25-337cce06a461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258712135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.3258712135
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.1552204559
Short name T485
Test name
Test status
Simulation time 24339082193 ps
CPU time 52 seconds
Started Jan 07 01:07:46 PM PST 24
Finished Jan 07 01:08:45 PM PST 24
Peak memory 200680 kb
Host smart-daeb9bbc-deba-4569-9982-b110c4b377ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552204559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.1552204559
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.640871357
Short name T440
Test name
Test status
Simulation time 3193988489 ps
CPU time 3.98 seconds
Started Jan 07 01:07:39 PM PST 24
Finished Jan 07 01:07:46 PM PST 24
Peak memory 200744 kb
Host smart-87c40ab0-0a83-4eb3-adfb-b969bec8103a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640871357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.640871357
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.3527326086
Short name T160
Test name
Test status
Simulation time 5484387644 ps
CPU time 14.13 seconds
Started Jan 07 01:07:46 PM PST 24
Finished Jan 07 01:08:08 PM PST 24
Peak memory 200764 kb
Host smart-3106960c-0d87-4b5b-982a-6256dc885051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527326086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.3527326086
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.177472891
Short name T92
Test name
Test status
Simulation time 48645035570 ps
CPU time 31.96 seconds
Started Jan 07 01:07:49 PM PST 24
Finished Jan 07 01:08:29 PM PST 24
Peak memory 200668 kb
Host smart-56e30f7f-4c81-4c66-9edf-4c1765c114d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177472891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all.
177472891
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.2615415643
Short name T475
Test name
Test status
Simulation time 359259719 ps
CPU time 1.42 seconds
Started Jan 07 01:08:11 PM PST 24
Finished Jan 07 01:08:15 PM PST 24
Peak memory 199904 kb
Host smart-e8122d10-8c7b-4c60-bd91-efb79a9dad7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615415643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.2615415643
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.2066527010
Short name T309
Test name
Test status
Simulation time 321050027599 ps
CPU time 752.78 seconds
Started Jan 07 01:08:10 PM PST 24
Finished Jan 07 01:20:46 PM PST 24
Peak memory 200820 kb
Host smart-313dc752-b65a-481f-965a-1e03b54fcc67
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066527010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.2066527010
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.1423433536
Short name T167
Test name
Test status
Simulation time 325133757334 ps
CPU time 201.54 seconds
Started Jan 07 01:07:53 PM PST 24
Finished Jan 07 01:11:22 PM PST 24
Peak memory 200944 kb
Host smart-c60a8f0b-5503-49b3-a08a-8f43b884f571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423433536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.1423433536
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.3979530707
Short name T508
Test name
Test status
Simulation time 495510527692 ps
CPU time 149.32 seconds
Started Jan 07 01:08:11 PM PST 24
Finished Jan 07 01:10:43 PM PST 24
Peak memory 200168 kb
Host smart-4a5555a4-3b6b-4293-a61a-bf346bfaa008
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979530707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.3979530707
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.268355748
Short name T666
Test name
Test status
Simulation time 329000032526 ps
CPU time 793.3 seconds
Started Jan 07 01:07:56 PM PST 24
Finished Jan 07 01:21:15 PM PST 24
Peak memory 200772 kb
Host smart-261e601e-d044-461d-89ec-22945a5989e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268355748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.268355748
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.195925522
Short name T94
Test name
Test status
Simulation time 164748247949 ps
CPU time 97.01 seconds
Started Jan 07 01:07:51 PM PST 24
Finished Jan 07 01:09:34 PM PST 24
Peak memory 200968 kb
Host smart-939de123-bf60-448c-afec-e68d04375aea
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=195925522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fixe
d.195925522
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.1791349878
Short name T149
Test name
Test status
Simulation time 494460208956 ps
CPU time 257.17 seconds
Started Jan 07 01:07:51 PM PST 24
Finished Jan 07 01:12:14 PM PST 24
Peak memory 200884 kb
Host smart-d716a2d4-9c75-42ae-891f-5d68946c5868
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791349878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.1791349878
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.87872650
Short name T713
Test name
Test status
Simulation time 160987136644 ps
CPU time 372.17 seconds
Started Jan 07 01:07:56 PM PST 24
Finished Jan 07 01:14:14 PM PST 24
Peak memory 200840 kb
Host smart-47af1818-b07e-46cc-b900-bff7871c37cf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87872650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.a
dc_ctrl_filters_wakeup_fixed.87872650
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.2374905690
Short name T765
Test name
Test status
Simulation time 74725605936 ps
CPU time 286.19 seconds
Started Jan 07 01:07:52 PM PST 24
Finished Jan 07 01:12:43 PM PST 24
Peak memory 201276 kb
Host smart-87e2ab95-f7c2-4c66-85f1-7ea149258165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374905690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.2374905690
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.4180675170
Short name T377
Test name
Test status
Simulation time 45171403783 ps
CPU time 108.47 seconds
Started Jan 07 01:08:11 PM PST 24
Finished Jan 07 01:10:02 PM PST 24
Peak memory 200680 kb
Host smart-e3664883-5ab8-41e5-aa30-80d5625e28da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180675170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.4180675170
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.1323524836
Short name T717
Test name
Test status
Simulation time 3707382199 ps
CPU time 9.12 seconds
Started Jan 07 01:08:10 PM PST 24
Finished Jan 07 01:08:20 PM PST 24
Peak memory 200676 kb
Host smart-336ee6fe-697e-41bb-86c4-d6c16e646401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323524836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.1323524836
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.2780870247
Short name T404
Test name
Test status
Simulation time 5593540061 ps
CPU time 4 seconds
Started Jan 07 01:07:51 PM PST 24
Finished Jan 07 01:08:01 PM PST 24
Peak memory 200700 kb
Host smart-793f1620-1038-4d19-856e-d058dddf5d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780870247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.2780870247
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.2869811283
Short name T253
Test name
Test status
Simulation time 546893155910 ps
CPU time 292.74 seconds
Started Jan 07 01:07:50 PM PST 24
Finished Jan 07 01:12:50 PM PST 24
Peak memory 200860 kb
Host smart-3bd38c79-70df-4eb7-88cc-05c598b7cc88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869811283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.2869811283
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.1458236679
Short name T38
Test name
Test status
Simulation time 297724405 ps
CPU time 0.83 seconds
Started Jan 07 01:07:54 PM PST 24
Finished Jan 07 01:08:01 PM PST 24
Peak memory 200428 kb
Host smart-5beb5728-94c9-45d3-aaa4-a8e1cd61e181
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458236679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.1458236679
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.573229632
Short name T44
Test name
Test status
Simulation time 330725556823 ps
CPU time 156.15 seconds
Started Jan 07 01:07:51 PM PST 24
Finished Jan 07 01:10:33 PM PST 24
Peak memory 200876 kb
Host smart-6faf275b-7baf-4780-8c22-1d300089feaf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573229632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gati
ng.573229632
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.3524263320
Short name T245
Test name
Test status
Simulation time 161871674248 ps
CPU time 191.16 seconds
Started Jan 07 01:07:55 PM PST 24
Finished Jan 07 01:11:13 PM PST 24
Peak memory 200832 kb
Host smart-57f229f3-67b3-4355-a75a-57309afa27d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524263320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.3524263320
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.2583777304
Short name T227
Test name
Test status
Simulation time 161743071891 ps
CPU time 91.1 seconds
Started Jan 07 01:07:50 PM PST 24
Finished Jan 07 01:09:28 PM PST 24
Peak memory 200896 kb
Host smart-3407da59-c857-4df9-9122-3d8ffa87756c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583777304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.2583777304
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.3566418964
Short name T727
Test name
Test status
Simulation time 165798486491 ps
CPU time 96.28 seconds
Started Jan 07 01:08:09 PM PST 24
Finished Jan 07 01:09:46 PM PST 24
Peak memory 200812 kb
Host smart-d7f6d27b-8443-4e73-b35b-c2cd32ce7126
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566418964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.3566418964
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.3887260755
Short name T835
Test name
Test status
Simulation time 491094836126 ps
CPU time 1030.78 seconds
Started Jan 07 01:07:53 PM PST 24
Finished Jan 07 01:25:11 PM PST 24
Peak memory 200944 kb
Host smart-b78a84ca-9423-4b15-a285-a20de46f4b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887260755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.3887260755
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.678626935
Short name T671
Test name
Test status
Simulation time 161059464611 ps
CPU time 389.65 seconds
Started Jan 07 01:07:52 PM PST 24
Finished Jan 07 01:14:27 PM PST 24
Peak memory 200912 kb
Host smart-fc10cfee-b9f1-49ec-b7a7-64b04eb743ed
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=678626935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fixe
d.678626935
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.209740478
Short name T304
Test name
Test status
Simulation time 162138353100 ps
CPU time 35.37 seconds
Started Jan 07 01:07:53 PM PST 24
Finished Jan 07 01:08:35 PM PST 24
Peak memory 200924 kb
Host smart-cd54e49e-a769-42b1-8c15-faae01dfc554
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209740478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_
wakeup.209740478
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.2728701927
Short name T613
Test name
Test status
Simulation time 328020950404 ps
CPU time 85.59 seconds
Started Jan 07 01:07:52 PM PST 24
Finished Jan 07 01:09:23 PM PST 24
Peak memory 200916 kb
Host smart-2ae5df63-0a32-47a6-8dc8-1be113f0bffe
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728701927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.2728701927
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.1967557491
Short name T457
Test name
Test status
Simulation time 75357870716 ps
CPU time 399.66 seconds
Started Jan 07 01:07:53 PM PST 24
Finished Jan 07 01:14:40 PM PST 24
Peak memory 201284 kb
Host smart-6ce166c5-3441-4e55-87f8-de19d051e7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967557491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.1967557491
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.2811014026
Short name T595
Test name
Test status
Simulation time 42660902880 ps
CPU time 101.05 seconds
Started Jan 07 01:07:50 PM PST 24
Finished Jan 07 01:09:38 PM PST 24
Peak memory 200672 kb
Host smart-a90ee324-1431-4657-a36f-27f9a85b64b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811014026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.2811014026
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.186873369
Short name T441
Test name
Test status
Simulation time 3065431607 ps
CPU time 4.28 seconds
Started Jan 07 01:08:08 PM PST 24
Finished Jan 07 01:08:13 PM PST 24
Peak memory 200692 kb
Host smart-49a3ddbe-e17c-4efa-873a-595386660c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186873369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.186873369
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.4002591604
Short name T681
Test name
Test status
Simulation time 5821034177 ps
CPU time 13.79 seconds
Started Jan 07 01:07:53 PM PST 24
Finished Jan 07 01:08:14 PM PST 24
Peak memory 200712 kb
Host smart-5bed6224-d9f7-42ae-bdf4-872ac7b00dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002591604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.4002591604
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.435385101
Short name T760
Test name
Test status
Simulation time 112439750918 ps
CPU time 207.32 seconds
Started Jan 07 01:07:52 PM PST 24
Finished Jan 07 01:11:25 PM PST 24
Peak memory 209484 kb
Host smart-d09601df-1655-4dfa-b043-b6d4cbed7a76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435385101 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.435385101
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.143259885
Short name T478
Test name
Test status
Simulation time 293092590 ps
CPU time 1.25 seconds
Started Jan 07 01:08:10 PM PST 24
Finished Jan 07 01:08:14 PM PST 24
Peak memory 200524 kb
Host smart-9b9522a4-a620-419e-9094-b02eebb397f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143259885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.143259885
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.4222760292
Short name T297
Test name
Test status
Simulation time 328510855313 ps
CPU time 439.02 seconds
Started Jan 07 01:08:12 PM PST 24
Finished Jan 07 01:15:35 PM PST 24
Peak memory 200776 kb
Host smart-3b5dd5ae-ba34-48af-a6ad-ea3a4f12817f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222760292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.4222760292
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.579090650
Short name T147
Test name
Test status
Simulation time 338398469761 ps
CPU time 95.17 seconds
Started Jan 07 01:08:11 PM PST 24
Finished Jan 07 01:09:49 PM PST 24
Peak memory 200992 kb
Host smart-22fc2dc6-24f5-44ed-b374-05aff2cd9881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579090650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.579090650
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.571357085
Short name T605
Test name
Test status
Simulation time 165224109274 ps
CPU time 71.21 seconds
Started Jan 07 01:08:12 PM PST 24
Finished Jan 07 01:09:27 PM PST 24
Peak memory 200820 kb
Host smart-91f0aa02-2dc9-4830-b420-8f90d234c055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571357085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.571357085
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.757933386
Short name T805
Test name
Test status
Simulation time 163852446350 ps
CPU time 197.63 seconds
Started Jan 07 01:08:11 PM PST 24
Finished Jan 07 01:11:31 PM PST 24
Peak memory 200816 kb
Host smart-cf6f45bb-1058-4377-8a89-d835232419af
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=757933386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrup
t_fixed.757933386
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.3942258570
Short name T14
Test name
Test status
Simulation time 323336311150 ps
CPU time 559.48 seconds
Started Jan 07 01:08:11 PM PST 24
Finished Jan 07 01:17:33 PM PST 24
Peak memory 200872 kb
Host smart-87db9988-0aca-4864-9e38-7f181f005b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942258570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.3942258570
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.3056082060
Short name T548
Test name
Test status
Simulation time 331864060447 ps
CPU time 225.94 seconds
Started Jan 07 01:08:12 PM PST 24
Finished Jan 07 01:12:02 PM PST 24
Peak memory 200876 kb
Host smart-d78891d9-0b54-44ff-a0bc-a1a5a5f31823
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056082060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.3056082060
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.153490687
Short name T762
Test name
Test status
Simulation time 165412858247 ps
CPU time 399.38 seconds
Started Jan 07 01:08:17 PM PST 24
Finished Jan 07 01:14:59 PM PST 24
Peak memory 200808 kb
Host smart-874ad6fd-c044-478b-b469-53c78ac4aaef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153490687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_
wakeup.153490687
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.2392831058
Short name T493
Test name
Test status
Simulation time 327300607379 ps
CPU time 772 seconds
Started Jan 07 01:08:12 PM PST 24
Finished Jan 07 01:21:07 PM PST 24
Peak memory 200896 kb
Host smart-1f9bb4b0-5201-472d-91b5-e55d8cb5c5db
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392831058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.2392831058
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.3534617863
Short name T338
Test name
Test status
Simulation time 73594748778 ps
CPU time 271.42 seconds
Started Jan 07 01:08:13 PM PST 24
Finished Jan 07 01:12:48 PM PST 24
Peak memory 201184 kb
Host smart-0e373348-d870-444a-9a8f-a04558e77934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534617863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.3534617863
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.749790363
Short name T163
Test name
Test status
Simulation time 43662768798 ps
CPU time 16.95 seconds
Started Jan 07 01:08:11 PM PST 24
Finished Jan 07 01:08:31 PM PST 24
Peak memory 200648 kb
Host smart-6eacc1dd-88c2-4875-96b0-67ed92bc2f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749790363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.749790363
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.2891780426
Short name T430
Test name
Test status
Simulation time 2570093066 ps
CPU time 6.68 seconds
Started Jan 07 01:08:12 PM PST 24
Finished Jan 07 01:08:22 PM PST 24
Peak memory 200656 kb
Host smart-b3ca3d9c-b090-438b-a587-edca62d3b109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891780426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.2891780426
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.111144169
Short name T672
Test name
Test status
Simulation time 5619652227 ps
CPU time 8.35 seconds
Started Jan 07 01:08:12 PM PST 24
Finished Jan 07 01:08:24 PM PST 24
Peak memory 200616 kb
Host smart-118b64f6-4813-452a-acbf-1837ffc2f0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111144169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.111144169
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.1065827328
Short name T573
Test name
Test status
Simulation time 246272806986 ps
CPU time 160.74 seconds
Started Jan 07 01:08:13 PM PST 24
Finished Jan 07 01:10:57 PM PST 24
Peak memory 209584 kb
Host smart-1c743743-c89a-45a3-8cdf-c178e5fcdad0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065827328 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.1065827328
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.3457909731
Short name T641
Test name
Test status
Simulation time 507868681 ps
CPU time 1.2 seconds
Started Jan 07 01:08:10 PM PST 24
Finished Jan 07 01:08:14 PM PST 24
Peak memory 200644 kb
Host smart-4628b49d-975d-4c72-8714-5d03388bc204
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457909731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.3457909731
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.2416865682
Short name T33
Test name
Test status
Simulation time 164560162324 ps
CPU time 193.16 seconds
Started Jan 07 01:08:11 PM PST 24
Finished Jan 07 01:11:27 PM PST 24
Peak memory 200896 kb
Host smart-3258bd04-2a18-4b42-8715-1def2cb24a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416865682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.2416865682
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.2222287326
Short name T226
Test name
Test status
Simulation time 494806918468 ps
CPU time 1099.86 seconds
Started Jan 07 01:08:12 PM PST 24
Finished Jan 07 01:26:35 PM PST 24
Peak memory 200936 kb
Host smart-019bcfce-75e7-4e51-8445-ca6b392995be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222287326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.2222287326
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.95644171
Short name T688
Test name
Test status
Simulation time 495402180988 ps
CPU time 306.65 seconds
Started Jan 07 01:08:11 PM PST 24
Finished Jan 07 01:13:20 PM PST 24
Peak memory 200888 kb
Host smart-bc3f4a0e-118c-47e6-bd6b-7eb1ae280193
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=95644171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt
_fixed.95644171
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.4002204360
Short name T810
Test name
Test status
Simulation time 325219000516 ps
CPU time 807.16 seconds
Started Jan 07 01:08:10 PM PST 24
Finished Jan 07 01:21:40 PM PST 24
Peak memory 200892 kb
Host smart-6b831f00-3fdb-4a7c-b9e5-6a3b6fb55e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002204360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.4002204360
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.2182473334
Short name T391
Test name
Test status
Simulation time 331820251957 ps
CPU time 393.69 seconds
Started Jan 07 01:08:13 PM PST 24
Finished Jan 07 01:14:50 PM PST 24
Peak memory 200924 kb
Host smart-ac3de905-ab7d-4fee-b519-154aee0660c6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182473334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.2182473334
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.2343354993
Short name T282
Test name
Test status
Simulation time 172337961058 ps
CPU time 104.26 seconds
Started Jan 07 01:08:12 PM PST 24
Finished Jan 07 01:10:00 PM PST 24
Peak memory 200848 kb
Host smart-2698bfb2-6055-48a1-9f5d-410f03161c93
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343354993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.2343354993
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.3310303034
Short name T701
Test name
Test status
Simulation time 486395022488 ps
CPU time 516.1 seconds
Started Jan 07 01:08:12 PM PST 24
Finished Jan 07 01:16:52 PM PST 24
Peak memory 200900 kb
Host smart-d44d85d5-94e6-49f6-a7b9-29c68c95601d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310303034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.3310303034
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.796282379
Short name T470
Test name
Test status
Simulation time 100485562119 ps
CPU time 375.98 seconds
Started Jan 07 01:08:12 PM PST 24
Finished Jan 07 01:14:32 PM PST 24
Peak memory 201340 kb
Host smart-60728632-8f22-4be7-b04c-29bcc0ae9dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796282379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.796282379
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.1326214152
Short name T604
Test name
Test status
Simulation time 24853657518 ps
CPU time 58.82 seconds
Started Jan 07 01:08:11 PM PST 24
Finished Jan 07 01:09:12 PM PST 24
Peak memory 200760 kb
Host smart-b43df3c3-c295-4688-bdac-ec1ed418462f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326214152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.1326214152
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.1437934455
Short name T471
Test name
Test status
Simulation time 5170470159 ps
CPU time 12.88 seconds
Started Jan 07 01:08:12 PM PST 24
Finished Jan 07 01:08:28 PM PST 24
Peak memory 200748 kb
Host smart-9037eb51-966a-4fa9-a565-abe8f80265f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437934455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.1437934455
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.1445999069
Short name T599
Test name
Test status
Simulation time 5968498009 ps
CPU time 4.06 seconds
Started Jan 07 01:08:12 PM PST 24
Finished Jan 07 01:08:19 PM PST 24
Peak memory 200708 kb
Host smart-6f9d6963-f1d2-44df-87cd-52ca3acb78c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445999069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.1445999069
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.1780307821
Short name T557
Test name
Test status
Simulation time 173446738088 ps
CPU time 373.71 seconds
Started Jan 07 01:08:10 PM PST 24
Finished Jan 07 01:14:26 PM PST 24
Peak memory 200812 kb
Host smart-c5ffeb80-6d1c-465c-a160-faa2d2f67292
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780307821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.1780307821
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.1299886713
Short name T761
Test name
Test status
Simulation time 350833983 ps
CPU time 0.82 seconds
Started Jan 07 01:08:13 PM PST 24
Finished Jan 07 01:08:17 PM PST 24
Peak memory 200628 kb
Host smart-7491c925-a5ca-4e8d-b2b5-6ec99419dad3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299886713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.1299886713
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.2703431700
Short name T677
Test name
Test status
Simulation time 330449738797 ps
CPU time 522.36 seconds
Started Jan 07 01:08:11 PM PST 24
Finished Jan 07 01:16:56 PM PST 24
Peak memory 200892 kb
Host smart-19b2cd30-13d6-4100-b1ad-11f1d55f7457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703431700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.2703431700
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.706821759
Short name T249
Test name
Test status
Simulation time 161538259389 ps
CPU time 373.58 seconds
Started Jan 07 01:08:12 PM PST 24
Finished Jan 07 01:14:29 PM PST 24
Peak memory 200888 kb
Host smart-fe777935-c3b9-4775-9f26-6b87df040e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706821759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.706821759
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.915707389
Short name T495
Test name
Test status
Simulation time 162245216327 ps
CPU time 65.15 seconds
Started Jan 07 01:08:10 PM PST 24
Finished Jan 07 01:09:17 PM PST 24
Peak memory 200908 kb
Host smart-03e376e6-8887-43da-a984-9d880355f3df
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=915707389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrup
t_fixed.915707389
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.3414513672
Short name T756
Test name
Test status
Simulation time 160588665117 ps
CPU time 362.18 seconds
Started Jan 07 01:08:11 PM PST 24
Finished Jan 07 01:14:16 PM PST 24
Peak memory 200968 kb
Host smart-12518667-f3e7-4df9-b39b-f23fe59eaa0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414513672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.3414513672
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.1458672146
Short name T533
Test name
Test status
Simulation time 322555728831 ps
CPU time 810.78 seconds
Started Jan 07 01:08:10 PM PST 24
Finished Jan 07 01:21:42 PM PST 24
Peak memory 200728 kb
Host smart-0034e079-d971-4a94-8318-3c26da027cf5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458672146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.1458672146
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.2523504359
Short name T435
Test name
Test status
Simulation time 168016148057 ps
CPU time 23.67 seconds
Started Jan 07 01:08:11 PM PST 24
Finished Jan 07 01:08:37 PM PST 24
Peak memory 200860 kb
Host smart-85e0e13e-ac15-49d7-b016-74206dab179e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523504359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.2523504359
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.1500173832
Short name T566
Test name
Test status
Simulation time 164939096426 ps
CPU time 408.11 seconds
Started Jan 07 01:08:13 PM PST 24
Finished Jan 07 01:15:05 PM PST 24
Peak memory 200816 kb
Host smart-81b8e5a4-492f-4466-86da-70a4ff9492e0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500173832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.1500173832
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.13966078
Short name T738
Test name
Test status
Simulation time 124351886460 ps
CPU time 406.64 seconds
Started Jan 07 01:08:17 PM PST 24
Finished Jan 07 01:15:06 PM PST 24
Peak memory 201340 kb
Host smart-ad4fe6de-04a2-47ae-bfdb-f0dbd3db9971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13966078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.13966078
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.1049047526
Short name T393
Test name
Test status
Simulation time 43962448066 ps
CPU time 91.14 seconds
Started Jan 07 01:08:10 PM PST 24
Finished Jan 07 01:09:43 PM PST 24
Peak memory 200688 kb
Host smart-548f766b-109a-46f0-86a7-c7cd94543c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049047526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.1049047526
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.2771955865
Short name T690
Test name
Test status
Simulation time 4476876990 ps
CPU time 4.56 seconds
Started Jan 07 01:08:13 PM PST 24
Finished Jan 07 01:08:21 PM PST 24
Peak memory 200712 kb
Host smart-20c108cd-451f-42b8-b92a-c7178c0b5adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771955865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.2771955865
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.3466791860
Short name T386
Test name
Test status
Simulation time 5443584740 ps
CPU time 13.98 seconds
Started Jan 07 01:08:13 PM PST 24
Finished Jan 07 01:08:31 PM PST 24
Peak memory 200744 kb
Host smart-bed1de57-d502-4530-a483-058afe318d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466791860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.3466791860
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.2001271503
Short name T716
Test name
Test status
Simulation time 121028761159 ps
CPU time 479.67 seconds
Started Jan 07 01:08:12 PM PST 24
Finished Jan 07 01:16:16 PM PST 24
Peak memory 209484 kb
Host smart-005d3785-7a3c-47a2-a784-b57a57b02ae7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001271503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.2001271503
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.3080211116
Short name T281
Test name
Test status
Simulation time 112264691855 ps
CPU time 140.27 seconds
Started Jan 07 01:08:12 PM PST 24
Finished Jan 07 01:10:35 PM PST 24
Peak memory 200972 kb
Host smart-743c04e4-eb26-4a92-b042-2c151439b82e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080211116 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.3080211116
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.3002100336
Short name T774
Test name
Test status
Simulation time 408475101 ps
CPU time 0.81 seconds
Started Jan 07 01:08:12 PM PST 24
Finished Jan 07 01:08:16 PM PST 24
Peak memory 200652 kb
Host smart-823fcc30-f849-4d84-a53d-3b0214c097e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002100336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.3002100336
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.2673998329
Short name T267
Test name
Test status
Simulation time 503501555067 ps
CPU time 1183.63 seconds
Started Jan 07 01:08:11 PM PST 24
Finished Jan 07 01:27:58 PM PST 24
Peak memory 201004 kb
Host smart-9af8cca1-5783-47e0-88d7-245b8ba1493e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673998329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.2673998329
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.2944701567
Short name T811
Test name
Test status
Simulation time 326209774019 ps
CPU time 134.09 seconds
Started Jan 07 01:08:10 PM PST 24
Finished Jan 07 01:10:26 PM PST 24
Peak memory 200844 kb
Host smart-70789dd4-63f2-4c91-8a26-6c7ef3d6276b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944701567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.2944701567
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.3804850349
Short name T528
Test name
Test status
Simulation time 165528193005 ps
CPU time 91 seconds
Started Jan 07 01:08:11 PM PST 24
Finished Jan 07 01:09:45 PM PST 24
Peak memory 200800 kb
Host smart-f6d3fa5e-6cbd-4f5f-9d10-848bb0a00298
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804850349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.3804850349
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.3839300130
Short name T838
Test name
Test status
Simulation time 336892287138 ps
CPU time 386.31 seconds
Started Jan 07 01:08:14 PM PST 24
Finished Jan 07 01:14:44 PM PST 24
Peak memory 200976 kb
Host smart-ea7e5636-ea38-4e9a-947e-523911822a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839300130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.3839300130
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.1377764939
Short name T594
Test name
Test status
Simulation time 332137212280 ps
CPU time 371.59 seconds
Started Jan 07 01:08:11 PM PST 24
Finished Jan 07 01:14:26 PM PST 24
Peak memory 200848 kb
Host smart-5b6fb188-2e3c-4c80-b5a0-7676e6d8de5a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377764939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.1377764939
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.1179671510
Short name T780
Test name
Test status
Simulation time 334545294670 ps
CPU time 208.22 seconds
Started Jan 07 01:08:12 PM PST 24
Finished Jan 07 01:11:43 PM PST 24
Peak memory 200824 kb
Host smart-cf49d6a4-3684-4e05-8541-7218a5cd9513
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179671510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.1179671510
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.1600934309
Short name T664
Test name
Test status
Simulation time 125861754704 ps
CPU time 468.96 seconds
Started Jan 07 01:08:17 PM PST 24
Finished Jan 07 01:16:09 PM PST 24
Peak memory 201424 kb
Host smart-8c2f7ab8-b9d6-4340-b1d0-4959217132d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600934309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.1600934309
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.1761684067
Short name T751
Test name
Test status
Simulation time 46312465517 ps
CPU time 27.97 seconds
Started Jan 07 01:08:11 PM PST 24
Finished Jan 07 01:08:41 PM PST 24
Peak memory 200688 kb
Host smart-e82ed731-7b38-4dba-aa5f-7671fa69d762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761684067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.1761684067
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.2709441371
Short name T150
Test name
Test status
Simulation time 3968248201 ps
CPU time 2.9 seconds
Started Jan 07 01:08:11 PM PST 24
Finished Jan 07 01:08:18 PM PST 24
Peak memory 200716 kb
Host smart-8dd4ac08-72aa-4511-9112-2a96eafd868d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709441371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.2709441371
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.1258320148
Short name T589
Test name
Test status
Simulation time 5776330150 ps
CPU time 5.86 seconds
Started Jan 07 01:08:10 PM PST 24
Finished Jan 07 01:08:19 PM PST 24
Peak memory 200704 kb
Host smart-d0a5f71e-324f-4018-bc03-bf6e309e2d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258320148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.1258320148
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.2486880078
Short name T773
Test name
Test status
Simulation time 7667278304 ps
CPU time 1.65 seconds
Started Jan 07 01:08:17 PM PST 24
Finished Jan 07 01:08:21 PM PST 24
Peak memory 200776 kb
Host smart-ad8e1124-371d-4692-884a-5fa68a007cfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486880078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.2486880078
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.757484758
Short name T119
Test name
Test status
Simulation time 252692442877 ps
CPU time 219.8 seconds
Started Jan 07 01:08:16 PM PST 24
Finished Jan 07 01:11:59 PM PST 24
Peak memory 209612 kb
Host smart-7bcba9f3-d3c3-4048-a6ae-e31e505f266c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757484758 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.757484758
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.482742880
Short name T580
Test name
Test status
Simulation time 410125225 ps
CPU time 0.85 seconds
Started Jan 07 01:08:17 PM PST 24
Finished Jan 07 01:08:20 PM PST 24
Peak memory 200624 kb
Host smart-ee526ba9-a104-4029-bdf9-78ce2276ce14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482742880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.482742880
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.1198400700
Short name T276
Test name
Test status
Simulation time 162328702985 ps
CPU time 94.11 seconds
Started Jan 07 01:08:17 PM PST 24
Finished Jan 07 01:09:53 PM PST 24
Peak memory 200976 kb
Host smart-e3c03837-f90d-4436-88db-571615d21c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198400700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.1198400700
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.1688194695
Short name T197
Test name
Test status
Simulation time 492162239334 ps
CPU time 1112.92 seconds
Started Jan 07 01:08:17 PM PST 24
Finished Jan 07 01:26:52 PM PST 24
Peak memory 200960 kb
Host smart-c7ac5f91-fc6d-4079-9594-c3224f38e572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688194695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.1688194695
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.1677839024
Short name T512
Test name
Test status
Simulation time 333874382093 ps
CPU time 198.6 seconds
Started Jan 07 01:08:17 PM PST 24
Finished Jan 07 01:11:38 PM PST 24
Peak memory 200900 kb
Host smart-f687394c-5738-430c-9161-0d1e332cfbf1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677839024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.1677839024
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.1042073210
Short name T293
Test name
Test status
Simulation time 490129579856 ps
CPU time 518.84 seconds
Started Jan 07 01:08:17 PM PST 24
Finished Jan 07 01:16:58 PM PST 24
Peak memory 200924 kb
Host smart-3eabddd3-7821-4134-bcbc-cb0cddd417a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042073210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.1042073210
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.2142957356
Short name T748
Test name
Test status
Simulation time 328210213490 ps
CPU time 208.97 seconds
Started Jan 07 01:08:13 PM PST 24
Finished Jan 07 01:11:45 PM PST 24
Peak memory 200716 kb
Host smart-2cfa43bc-74fa-4f0b-a3d0-fd73d78b217c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142957356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.2142957356
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.2062384495
Short name T287
Test name
Test status
Simulation time 501178714050 ps
CPU time 617.06 seconds
Started Jan 07 01:08:17 PM PST 24
Finished Jan 07 01:18:37 PM PST 24
Peak memory 200924 kb
Host smart-1c7c2e67-a419-472f-9f7c-c3915c02729f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062384495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.2062384495
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.2126558590
Short name T826
Test name
Test status
Simulation time 167301027924 ps
CPU time 402.81 seconds
Started Jan 07 01:08:17 PM PST 24
Finished Jan 07 01:15:02 PM PST 24
Peak memory 200912 kb
Host smart-c9b80e88-8fa5-4823-b94f-a41053d0c5de
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126558590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.2126558590
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.4027008410
Short name T722
Test name
Test status
Simulation time 114431376544 ps
CPU time 396.6 seconds
Started Jan 07 01:08:16 PM PST 24
Finished Jan 07 01:14:55 PM PST 24
Peak memory 201284 kb
Host smart-2ce060ac-469e-4a73-aa68-9351cdacfce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027008410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.4027008410
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.2143043342
Short name T545
Test name
Test status
Simulation time 27131815681 ps
CPU time 32.77 seconds
Started Jan 07 01:08:16 PM PST 24
Finished Jan 07 01:08:51 PM PST 24
Peak memory 200700 kb
Host smart-4948a543-59b1-4c4b-8ad2-62437b314b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143043342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.2143043342
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.1156822213
Short name T658
Test name
Test status
Simulation time 3744366648 ps
CPU time 2.6 seconds
Started Jan 07 01:08:14 PM PST 24
Finished Jan 07 01:08:20 PM PST 24
Peak memory 200700 kb
Host smart-86ae30ee-a736-49c1-a354-269022aefdc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156822213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.1156822213
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.1460961488
Short name T492
Test name
Test status
Simulation time 5722039167 ps
CPU time 7.21 seconds
Started Jan 07 01:08:17 PM PST 24
Finished Jan 07 01:08:27 PM PST 24
Peak memory 200728 kb
Host smart-7f20f8a1-89dd-435a-a9a0-17c83945af30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460961488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.1460961488
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.1734653335
Short name T582
Test name
Test status
Simulation time 45810846051 ps
CPU time 102 seconds
Started Jan 07 01:08:24 PM PST 24
Finished Jan 07 01:10:07 PM PST 24
Peak memory 200768 kb
Host smart-a850044c-36d4-438d-853d-ec01ec224635
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734653335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.1734653335
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.2894870550
Short name T571
Test name
Test status
Simulation time 36893917156 ps
CPU time 54.49 seconds
Started Jan 07 01:08:14 PM PST 24
Finished Jan 07 01:09:12 PM PST 24
Peak memory 208924 kb
Host smart-0f68f2ed-a4fe-4d4f-adfa-857cda69e8e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894870550 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.2894870550
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.3551336540
Short name T646
Test name
Test status
Simulation time 506621315 ps
CPU time 1.78 seconds
Started Jan 07 01:08:32 PM PST 24
Finished Jan 07 01:08:35 PM PST 24
Peak memory 200648 kb
Host smart-6c6e0aaa-4fd9-4206-8866-bad02502cf98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551336540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.3551336540
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.3826857799
Short name T312
Test name
Test status
Simulation time 334815373945 ps
CPU time 391.03 seconds
Started Jan 07 01:08:23 PM PST 24
Finished Jan 07 01:14:55 PM PST 24
Peak memory 200892 kb
Host smart-e9feca9b-e4c3-481d-82bb-599ecc1fbc97
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826857799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.3826857799
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.2050420625
Short name T687
Test name
Test status
Simulation time 326315658277 ps
CPU time 801.68 seconds
Started Jan 07 01:08:24 PM PST 24
Finished Jan 07 01:21:47 PM PST 24
Peak memory 200920 kb
Host smart-31ea8269-7325-4e6b-a175-ae22543a6de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050420625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.2050420625
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.4243485828
Short name T745
Test name
Test status
Simulation time 165478814812 ps
CPU time 403.86 seconds
Started Jan 07 01:08:22 PM PST 24
Finished Jan 07 01:15:08 PM PST 24
Peak memory 200864 kb
Host smart-a07e1efe-5ed9-4c22-ac83-db46d8f76b18
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243485828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.4243485828
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.2022417980
Short name T474
Test name
Test status
Simulation time 493104891181 ps
CPU time 1171.29 seconds
Started Jan 07 01:08:13 PM PST 24
Finished Jan 07 01:27:48 PM PST 24
Peak memory 201004 kb
Host smart-05403cff-650c-48f4-b60f-b950c14c4735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022417980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.2022417980
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.746858207
Short name T464
Test name
Test status
Simulation time 162631446282 ps
CPU time 103.36 seconds
Started Jan 07 01:08:22 PM PST 24
Finished Jan 07 01:10:07 PM PST 24
Peak memory 200964 kb
Host smart-6255fc12-d1f2-4599-86ec-bc9b6712874f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=746858207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fixe
d.746858207
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.1843760296
Short name T643
Test name
Test status
Simulation time 326528668265 ps
CPU time 352.94 seconds
Started Jan 07 01:08:24 PM PST 24
Finished Jan 07 01:14:18 PM PST 24
Peak memory 200972 kb
Host smart-70fcf3f3-c9b9-474d-8eb2-982982a8b077
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843760296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.1843760296
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.2556369669
Short name T473
Test name
Test status
Simulation time 162645276824 ps
CPU time 349.16 seconds
Started Jan 07 01:08:21 PM PST 24
Finished Jan 07 01:14:12 PM PST 24
Peak memory 200940 kb
Host smart-5681b9f6-e831-4f2e-b42c-0c66c533434f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556369669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.2556369669
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.2479046589
Short name T588
Test name
Test status
Simulation time 70111905976 ps
CPU time 383.1 seconds
Started Jan 07 01:08:23 PM PST 24
Finished Jan 07 01:14:48 PM PST 24
Peak memory 201340 kb
Host smart-732178cf-4f87-4e88-9c20-720dc6846692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479046589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.2479046589
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.1792971634
Short name T633
Test name
Test status
Simulation time 45893918557 ps
CPU time 55.26 seconds
Started Jan 07 01:08:29 PM PST 24
Finished Jan 07 01:09:27 PM PST 24
Peak memory 200692 kb
Host smart-733c982b-3781-4e2e-93ed-f1cd1a762b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792971634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.1792971634
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.289346254
Short name T446
Test name
Test status
Simulation time 4078800186 ps
CPU time 5.43 seconds
Started Jan 07 01:08:25 PM PST 24
Finished Jan 07 01:08:32 PM PST 24
Peak memory 200764 kb
Host smart-08145b68-a23c-4c7c-898c-5a108bff5759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289346254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.289346254
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.3210217664
Short name T630
Test name
Test status
Simulation time 6149665143 ps
CPU time 4.48 seconds
Started Jan 07 01:08:23 PM PST 24
Finished Jan 07 01:08:28 PM PST 24
Peak memory 200712 kb
Host smart-efe5ef5a-7c7f-4c1c-9065-4e38d1198d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210217664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.3210217664
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.2516502905
Short name T98
Test name
Test status
Simulation time 332675337872 ps
CPU time 759.18 seconds
Started Jan 07 01:08:27 PM PST 24
Finished Jan 07 01:21:08 PM PST 24
Peak memory 200904 kb
Host smart-1e0604b9-4d85-4236-9048-9ace5fcb17f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516502905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.2516502905
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.539602818
Short name T89
Test name
Test status
Simulation time 136169963117 ps
CPU time 156.89 seconds
Started Jan 07 01:08:29 PM PST 24
Finished Jan 07 01:11:08 PM PST 24
Peak memory 209576 kb
Host smart-81e58b5a-6f42-4edf-b631-ef47a04b2e2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539602818 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.539602818
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.1790758960
Short name T544
Test name
Test status
Simulation time 517377234 ps
CPU time 0.9 seconds
Started Jan 07 01:08:27 PM PST 24
Finished Jan 07 01:08:29 PM PST 24
Peak memory 200620 kb
Host smart-a0668fdf-12fc-44ce-8a02-dfab38f481d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790758960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.1790758960
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.1658265544
Short name T264
Test name
Test status
Simulation time 493945126423 ps
CPU time 241.86 seconds
Started Jan 07 01:08:25 PM PST 24
Finished Jan 07 01:12:29 PM PST 24
Peak memory 200944 kb
Host smart-378d5cbf-f2a3-4f6b-89d8-332052f6dd0c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658265544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.1658265544
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.3249351925
Short name T164
Test name
Test status
Simulation time 481244997443 ps
CPU time 1064.97 seconds
Started Jan 07 01:08:25 PM PST 24
Finished Jan 07 01:26:12 PM PST 24
Peak memory 200808 kb
Host smart-3387cb48-599c-44e8-86bd-cf0b18cb37bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249351925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.3249351925
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.3984093932
Short name T746
Test name
Test status
Simulation time 330337330836 ps
CPU time 747.55 seconds
Started Jan 07 01:08:27 PM PST 24
Finished Jan 07 01:20:56 PM PST 24
Peak memory 200756 kb
Host smart-ba7920fb-6150-4843-a3ad-43eee96db2e9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984093932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.3984093932
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.3537867852
Short name T127
Test name
Test status
Simulation time 486054194634 ps
CPU time 188.68 seconds
Started Jan 07 01:08:26 PM PST 24
Finished Jan 07 01:11:37 PM PST 24
Peak memory 200900 kb
Host smart-97868ade-db24-44ba-8820-76cf497dbfbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537867852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.3537867852
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.2862527275
Short name T768
Test name
Test status
Simulation time 163495560616 ps
CPU time 400.01 seconds
Started Jan 07 01:08:25 PM PST 24
Finished Jan 07 01:15:07 PM PST 24
Peak memory 200852 kb
Host smart-a9b3e64e-7dc9-42c8-9cb6-bff7e87197d1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862527275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.2862527275
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.1859914075
Short name T334
Test name
Test status
Simulation time 328035082493 ps
CPU time 755.39 seconds
Started Jan 07 01:08:25 PM PST 24
Finished Jan 07 01:21:02 PM PST 24
Peak memory 200836 kb
Host smart-7dae20ac-be39-488b-8b52-dc79c8a70dbe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859914075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.1859914075
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.2136902823
Short name T143
Test name
Test status
Simulation time 326546144850 ps
CPU time 192.59 seconds
Started Jan 07 01:08:25 PM PST 24
Finished Jan 07 01:11:39 PM PST 24
Peak memory 200888 kb
Host smart-cef82484-6a43-4530-8aef-0b76bff0b634
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136902823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.2136902823
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.4117078116
Short name T178
Test name
Test status
Simulation time 119914743149 ps
CPU time 352.89 seconds
Started Jan 07 01:08:24 PM PST 24
Finished Jan 07 01:14:18 PM PST 24
Peak memory 201324 kb
Host smart-36da2acb-2ef5-41f2-b89e-3c32d51269f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117078116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.4117078116
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.3675087050
Short name T392
Test name
Test status
Simulation time 33262664709 ps
CPU time 70.77 seconds
Started Jan 07 01:08:26 PM PST 24
Finished Jan 07 01:09:39 PM PST 24
Peak memory 200692 kb
Host smart-8d9b2237-cf03-4558-96da-4d3b40569c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675087050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.3675087050
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.1451229987
Short name T759
Test name
Test status
Simulation time 4559384149 ps
CPU time 8.17 seconds
Started Jan 07 01:08:24 PM PST 24
Finished Jan 07 01:08:33 PM PST 24
Peak memory 200704 kb
Host smart-30277633-e0e4-469f-99f2-5a024c329c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451229987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.1451229987
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.3563528395
Short name T401
Test name
Test status
Simulation time 5720448540 ps
CPU time 13.28 seconds
Started Jan 07 01:08:28 PM PST 24
Finished Jan 07 01:08:43 PM PST 24
Peak memory 200596 kb
Host smart-12d453fb-5f0c-46fd-b8b1-1dbaf9e204bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563528395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.3563528395
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.499511945
Short name T159
Test name
Test status
Simulation time 334255731722 ps
CPU time 292.32 seconds
Started Jan 07 01:08:27 PM PST 24
Finished Jan 07 01:13:21 PM PST 24
Peak memory 200764 kb
Host smart-8d97e4a9-a753-484a-aceb-d9079cfa70a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499511945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all.
499511945
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.2384816548
Short name T779
Test name
Test status
Simulation time 106979193042 ps
CPU time 120.27 seconds
Started Jan 07 01:08:26 PM PST 24
Finished Jan 07 01:10:29 PM PST 24
Peak memory 200964 kb
Host smart-871f8fcb-7e60-4906-8c86-343944dc19a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384816548 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.2384816548
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.205578298
Short name T592
Test name
Test status
Simulation time 386949266 ps
CPU time 0.82 seconds
Started Jan 07 01:06:04 PM PST 24
Finished Jan 07 01:06:07 PM PST 24
Peak memory 200552 kb
Host smart-a7ccd18c-3efc-4458-91c7-88ca4021efe5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205578298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.205578298
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.1817387209
Short name T537
Test name
Test status
Simulation time 164930622834 ps
CPU time 101.95 seconds
Started Jan 07 01:06:16 PM PST 24
Finished Jan 07 01:07:59 PM PST 24
Peak memory 200952 kb
Host smart-56169a09-bdde-4fae-91d1-9f8cd8ff7446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817387209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.1817387209
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.1729168330
Short name T833
Test name
Test status
Simulation time 162376398169 ps
CPU time 101.13 seconds
Started Jan 07 01:05:54 PM PST 24
Finished Jan 07 01:07:38 PM PST 24
Peak memory 200888 kb
Host smart-07dc0272-3c9c-4be9-b0b2-346b65fe0565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729168330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.1729168330
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.86082422
Short name T577
Test name
Test status
Simulation time 325832143817 ps
CPU time 712.01 seconds
Started Jan 07 01:06:02 PM PST 24
Finished Jan 07 01:17:57 PM PST 24
Peak memory 200892 kb
Host smart-a7d3758e-f9ce-4e60-a753-79ffd8d05c2f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=86082422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt_
fixed.86082422
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.3773497056
Short name T527
Test name
Test status
Simulation time 316840638054 ps
CPU time 713.29 seconds
Started Jan 07 01:05:55 PM PST 24
Finished Jan 07 01:17:52 PM PST 24
Peak memory 201008 kb
Host smart-38f516e4-b76e-4dac-958f-c8c1683e9c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773497056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.3773497056
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.2141388879
Short name T45
Test name
Test status
Simulation time 483612647063 ps
CPU time 303.98 seconds
Started Jan 07 01:06:14 PM PST 24
Finished Jan 07 01:11:20 PM PST 24
Peak memory 200764 kb
Host smart-a4a8f555-5883-4966-87b3-fd95ddcc8c64
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141388879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.2141388879
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.3687644133
Short name T238
Test name
Test status
Simulation time 522314706431 ps
CPU time 1120.96 seconds
Started Jan 07 01:06:17 PM PST 24
Finished Jan 07 01:24:59 PM PST 24
Peak memory 200852 kb
Host smart-29740f6d-f5fa-4ac2-bed2-01037335c48b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687644133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.3687644133
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.894665045
Short name T714
Test name
Test status
Simulation time 322209712712 ps
CPU time 399.25 seconds
Started Jan 07 01:06:20 PM PST 24
Finished Jan 07 01:13:01 PM PST 24
Peak memory 200920 kb
Host smart-68d2567d-bf2b-4910-9107-af85c2f67731
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894665045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.a
dc_ctrl_filters_wakeup_fixed.894665045
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.2187903122
Short name T29
Test name
Test status
Simulation time 68205653738 ps
CPU time 227.2 seconds
Started Jan 07 01:06:13 PM PST 24
Finished Jan 07 01:10:01 PM PST 24
Peak memory 201292 kb
Host smart-42c06bad-5ecd-4cf7-a1d3-9a7c96b17f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187903122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.2187903122
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.2099220050
Short name T403
Test name
Test status
Simulation time 36936364749 ps
CPU time 82.62 seconds
Started Jan 07 01:06:14 PM PST 24
Finished Jan 07 01:07:38 PM PST 24
Peak memory 200620 kb
Host smart-21ee5c25-15e3-467d-8fff-498b0b4f6f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099220050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.2099220050
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.2061603700
Short name T540
Test name
Test status
Simulation time 3302943927 ps
CPU time 7.93 seconds
Started Jan 07 01:06:13 PM PST 24
Finished Jan 07 01:06:22 PM PST 24
Peak memory 200660 kb
Host smart-707b147a-c976-4edc-9c55-c797b6771a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061603700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.2061603700
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.4266171912
Short name T569
Test name
Test status
Simulation time 6118915279 ps
CPU time 14.14 seconds
Started Jan 07 01:06:14 PM PST 24
Finished Jan 07 01:06:30 PM PST 24
Peak memory 200860 kb
Host smart-60dd224c-e817-4ff3-95ed-7115c6def402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266171912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.4266171912
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.2284325145
Short name T340
Test name
Test status
Simulation time 64253162052 ps
CPU time 79.19 seconds
Started Jan 07 01:06:12 PM PST 24
Finished Jan 07 01:07:32 PM PST 24
Peak memory 209212 kb
Host smart-11bc7b64-35d8-45a2-82ee-72df6f385cb9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284325145 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.2284325145
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.1768495766
Short name T402
Test name
Test status
Simulation time 425981570 ps
CPU time 0.71 seconds
Started Jan 07 01:06:11 PM PST 24
Finished Jan 07 01:06:13 PM PST 24
Peak memory 200700 kb
Host smart-48f463e0-c2e2-409f-8208-f7782218e8e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768495766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.1768495766
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.4170408681
Short name T257
Test name
Test status
Simulation time 331959090801 ps
CPU time 200.84 seconds
Started Jan 07 01:06:22 PM PST 24
Finished Jan 07 01:09:58 PM PST 24
Peak memory 200960 kb
Host smart-240e2050-09e4-49ef-b36d-0e1f7c06bdbc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170408681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.4170408681
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.994767991
Short name T728
Test name
Test status
Simulation time 334051066362 ps
CPU time 755.49 seconds
Started Jan 07 01:06:07 PM PST 24
Finished Jan 07 01:18:45 PM PST 24
Peak memory 200864 kb
Host smart-4b6cd841-28f6-4301-8f3e-321494b8c544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994767991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.994767991
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.1500657192
Short name T17
Test name
Test status
Simulation time 493161647847 ps
CPU time 1131.07 seconds
Started Jan 07 01:06:10 PM PST 24
Finished Jan 07 01:25:03 PM PST 24
Peak memory 200892 kb
Host smart-2c09390d-455b-42ce-a161-3405dbfad335
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500657192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.1500657192
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.2633650786
Short name T206
Test name
Test status
Simulation time 159618345798 ps
CPU time 372.13 seconds
Started Jan 07 01:06:18 PM PST 24
Finished Jan 07 01:12:31 PM PST 24
Peak memory 200876 kb
Host smart-5fbac6b0-4076-4447-a505-a6e5265ee27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633650786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.2633650786
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.2132741968
Short name T785
Test name
Test status
Simulation time 331673787442 ps
CPU time 762.81 seconds
Started Jan 07 01:06:18 PM PST 24
Finished Jan 07 01:19:02 PM PST 24
Peak memory 200900 kb
Host smart-cead3852-3268-4651-a5fd-978dd2f9d4e7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132741968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.2132741968
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.3093585597
Short name T565
Test name
Test status
Simulation time 337483040736 ps
CPU time 765.28 seconds
Started Jan 07 01:06:04 PM PST 24
Finished Jan 07 01:18:53 PM PST 24
Peak memory 200884 kb
Host smart-025d5f7e-e734-411b-8de1-57169dd3de55
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093585597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.3093585597
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.3356416283
Short name T445
Test name
Test status
Simulation time 487989093470 ps
CPU time 287.08 seconds
Started Jan 07 01:06:09 PM PST 24
Finished Jan 07 01:10:58 PM PST 24
Peak memory 200984 kb
Host smart-b3ae71a4-7f42-4cfb-a7c1-53d3345d25bb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356416283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.3356416283
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.2790496686
Short name T602
Test name
Test status
Simulation time 113200465166 ps
CPU time 319.97 seconds
Started Jan 07 01:06:07 PM PST 24
Finished Jan 07 01:11:29 PM PST 24
Peak memory 201312 kb
Host smart-baa74306-b44e-4f4f-944d-ff2e0647ed81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790496686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.2790496686
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.132653772
Short name T804
Test name
Test status
Simulation time 46331217316 ps
CPU time 57.28 seconds
Started Jan 07 01:06:19 PM PST 24
Finished Jan 07 01:07:18 PM PST 24
Peak memory 200724 kb
Host smart-e4692f89-1422-4b30-bbb2-48d9ba12bb75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132653772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.132653772
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.4080166213
Short name T766
Test name
Test status
Simulation time 3574586579 ps
CPU time 2.72 seconds
Started Jan 07 01:06:07 PM PST 24
Finished Jan 07 01:06:12 PM PST 24
Peak memory 200768 kb
Host smart-67fe0cf7-54f1-4550-bc60-3f9db03f287f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080166213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.4080166213
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.3134424793
Short name T468
Test name
Test status
Simulation time 5823872431 ps
CPU time 4.38 seconds
Started Jan 07 01:06:14 PM PST 24
Finished Jan 07 01:06:20 PM PST 24
Peak memory 200732 kb
Host smart-955ab420-6887-429f-bcd1-a43aae7fef66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134424793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.3134424793
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.407313776
Short name T252
Test name
Test status
Simulation time 169283978668 ps
CPU time 214.6 seconds
Started Jan 07 01:06:13 PM PST 24
Finished Jan 07 01:09:50 PM PST 24
Peak memory 200856 kb
Host smart-07605bf6-6281-46a6-ac01-12fdcf0a52d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407313776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.407313776
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.1785875986
Short name T673
Test name
Test status
Simulation time 130603539455 ps
CPU time 134.67 seconds
Started Jan 07 01:06:03 PM PST 24
Finished Jan 07 01:08:21 PM PST 24
Peak memory 201500 kb
Host smart-6bfc98fd-7725-4dcf-8b85-4524c8f2d8fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785875986 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.1785875986
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.437227189
Short name T623
Test name
Test status
Simulation time 426019694 ps
CPU time 0.86 seconds
Started Jan 07 01:06:22 PM PST 24
Finished Jan 07 01:06:24 PM PST 24
Peak memory 200680 kb
Host smart-ad5592fa-83a6-456f-b5a8-9f69639fef62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437227189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.437227189
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.2920949626
Short name T13
Test name
Test status
Simulation time 330830998814 ps
CPU time 200.27 seconds
Started Jan 07 01:06:14 PM PST 24
Finished Jan 07 01:09:36 PM PST 24
Peak memory 200936 kb
Host smart-1980f8a6-10a1-4e12-8756-fc48fd5daead
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920949626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.2920949626
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.1381461968
Short name T834
Test name
Test status
Simulation time 165914824594 ps
CPU time 385.33 seconds
Started Jan 07 01:06:05 PM PST 24
Finished Jan 07 01:12:33 PM PST 24
Peak memory 200848 kb
Host smart-c63b3a3b-b68f-404f-80e4-82995c012851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381461968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.1381461968
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.2759919039
Short name T133
Test name
Test status
Simulation time 323988322678 ps
CPU time 123.98 seconds
Started Jan 07 01:06:33 PM PST 24
Finished Jan 07 01:08:55 PM PST 24
Peak memory 200980 kb
Host smart-8dfe4634-ae94-4dc0-a0c1-e51e8da7dae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759919039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.2759919039
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.2918230819
Short name T432
Test name
Test status
Simulation time 330670412447 ps
CPU time 777.42 seconds
Started Jan 07 01:06:08 PM PST 24
Finished Jan 07 01:19:07 PM PST 24
Peak memory 200904 kb
Host smart-e60be942-ebee-4969-b24e-c46206529442
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918230819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.2918230819
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.4023693367
Short name T101
Test name
Test status
Simulation time 327349483377 ps
CPU time 383.77 seconds
Started Jan 07 01:06:15 PM PST 24
Finished Jan 07 01:12:40 PM PST 24
Peak memory 200908 kb
Host smart-a34ea534-1e42-4220-8d97-96daff8f9bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023693367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.4023693367
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.1230233334
Short name T606
Test name
Test status
Simulation time 487568172096 ps
CPU time 1149.67 seconds
Started Jan 07 01:06:16 PM PST 24
Finished Jan 07 01:25:27 PM PST 24
Peak memory 200848 kb
Host smart-efec5600-a098-41fb-8e4a-9b2507f93cc9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230233334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.1230233334
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.2939339241
Short name T669
Test name
Test status
Simulation time 164205519494 ps
CPU time 215.61 seconds
Started Jan 07 01:06:14 PM PST 24
Finished Jan 07 01:09:51 PM PST 24
Peak memory 200884 kb
Host smart-d0848368-2909-4446-b6d8-22fa480a4f16
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939339241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.2939339241
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.4068761546
Short name T517
Test name
Test status
Simulation time 161258020361 ps
CPU time 162.08 seconds
Started Jan 07 01:06:00 PM PST 24
Finished Jan 07 01:08:45 PM PST 24
Peak memory 200964 kb
Host smart-ebcf58dc-82c2-4ba3-aa57-f044316767d4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068761546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.4068761546
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.3379634351
Short name T175
Test name
Test status
Simulation time 118472696171 ps
CPU time 446.81 seconds
Started Jan 07 01:06:25 PM PST 24
Finished Jan 07 01:13:53 PM PST 24
Peak memory 201384 kb
Host smart-3ee529fc-2659-4866-b3c2-4d51ac7853c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379634351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.3379634351
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.4006048896
Short name T639
Test name
Test status
Simulation time 29837815824 ps
CPU time 72.9 seconds
Started Jan 07 01:06:18 PM PST 24
Finished Jan 07 01:07:32 PM PST 24
Peak memory 200764 kb
Host smart-ae58a75d-1d59-413d-986f-174935a556a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006048896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.4006048896
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.3554361960
Short name T601
Test name
Test status
Simulation time 3929110483 ps
CPU time 3.86 seconds
Started Jan 07 01:06:18 PM PST 24
Finished Jan 07 01:06:23 PM PST 24
Peak memory 200760 kb
Host smart-d254742f-5d65-49d1-990d-2ba83ca88fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554361960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.3554361960
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.771585643
Short name T424
Test name
Test status
Simulation time 5609880086 ps
CPU time 7.58 seconds
Started Jan 07 01:06:30 PM PST 24
Finished Jan 07 01:06:54 PM PST 24
Peak memory 200728 kb
Host smart-d7771575-be76-414f-9434-11669bd27100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771585643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.771585643
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.2014171863
Short name T670
Test name
Test status
Simulation time 34120725104 ps
CPU time 13.5 seconds
Started Jan 07 01:06:06 PM PST 24
Finished Jan 07 01:06:22 PM PST 24
Peak memory 200752 kb
Host smart-28fc4a4b-b013-42d5-8cac-6bf670c00624
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014171863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
2014171863
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.328070273
Short name T333
Test name
Test status
Simulation time 287617187293 ps
CPU time 161.35 seconds
Started Jan 07 01:06:03 PM PST 24
Finished Jan 07 01:08:47 PM PST 24
Peak memory 209560 kb
Host smart-ca6abaae-9463-4e00-840c-b97f12c68acc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328070273 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.328070273
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.2010698821
Short name T695
Test name
Test status
Simulation time 300268008 ps
CPU time 1.23 seconds
Started Jan 07 01:06:29 PM PST 24
Finished Jan 07 01:06:42 PM PST 24
Peak memory 200708 kb
Host smart-70ba6f40-a88a-4638-9d90-195f1f36ca2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010698821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.2010698821
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.3194275180
Short name T735
Test name
Test status
Simulation time 162994532518 ps
CPU time 37.38 seconds
Started Jan 07 01:06:25 PM PST 24
Finished Jan 07 01:07:05 PM PST 24
Peak memory 200888 kb
Host smart-a2a0acbb-fda3-44ba-868b-50eb3e831f2e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194275180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.3194275180
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.1100985031
Short name T786
Test name
Test status
Simulation time 343025611226 ps
CPU time 802.87 seconds
Started Jan 07 01:06:28 PM PST 24
Finished Jan 07 01:20:03 PM PST 24
Peak memory 200836 kb
Host smart-32f206b9-bd31-452a-bc07-715797cb3871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100985031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.1100985031
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.363236977
Short name T95
Test name
Test status
Simulation time 334431084569 ps
CPU time 395.96 seconds
Started Jan 07 01:06:17 PM PST 24
Finished Jan 07 01:12:54 PM PST 24
Peak memory 200828 kb
Host smart-120a8926-c16a-4117-8ced-4fd32bb49ee2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=363236977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt
_fixed.363236977
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.1115088830
Short name T795
Test name
Test status
Simulation time 167646354079 ps
CPU time 99.22 seconds
Started Jan 07 01:06:19 PM PST 24
Finished Jan 07 01:08:00 PM PST 24
Peak memory 200920 kb
Host smart-cc1ab999-8631-41cd-803d-98890922a894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115088830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.1115088830
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.1728159746
Short name T434
Test name
Test status
Simulation time 329463725846 ps
CPU time 209.87 seconds
Started Jan 07 01:06:26 PM PST 24
Finished Jan 07 01:10:00 PM PST 24
Peak memory 200912 kb
Host smart-abc6bd17-0bda-4d11-828c-d2c176a2d74b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728159746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.1728159746
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.492772169
Short name T268
Test name
Test status
Simulation time 163432123781 ps
CPU time 387.69 seconds
Started Jan 07 01:06:22 PM PST 24
Finished Jan 07 01:12:51 PM PST 24
Peak memory 200956 kb
Host smart-552ed167-ff4f-4abf-a7fd-6b04f5f9976d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492772169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_w
akeup.492772169
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.3648675525
Short name T539
Test name
Test status
Simulation time 332904606110 ps
CPU time 807.71 seconds
Started Jan 07 01:06:24 PM PST 24
Finished Jan 07 01:19:53 PM PST 24
Peak memory 200884 kb
Host smart-e92c15e1-fcda-4bef-9e08-d841f9dda0f7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648675525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.3648675525
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.4256535154
Short name T187
Test name
Test status
Simulation time 139927923810 ps
CPU time 743.53 seconds
Started Jan 07 01:06:20 PM PST 24
Finished Jan 07 01:18:45 PM PST 24
Peak memory 201212 kb
Host smart-f59b45c3-d17c-4123-93f3-d7d996d59b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256535154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.4256535154
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.503738099
Short name T552
Test name
Test status
Simulation time 44512455155 ps
CPU time 27.37 seconds
Started Jan 07 01:06:32 PM PST 24
Finished Jan 07 01:07:18 PM PST 24
Peak memory 200652 kb
Host smart-5a57ab8a-37cc-4262-a3e6-2a95241079b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503738099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.503738099
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.1155440813
Short name T652
Test name
Test status
Simulation time 3380831253 ps
CPU time 4.52 seconds
Started Jan 07 01:06:34 PM PST 24
Finished Jan 07 01:06:56 PM PST 24
Peak memory 200812 kb
Host smart-5d0b18a8-1432-4634-acea-f42f751c51de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155440813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.1155440813
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.3458279554
Short name T593
Test name
Test status
Simulation time 5731871800 ps
CPU time 3.24 seconds
Started Jan 07 01:06:37 PM PST 24
Finished Jan 07 01:06:55 PM PST 24
Peak memory 200608 kb
Host smart-4d91d4b0-e026-49bc-882f-e2a67b8482cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458279554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.3458279554
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.449432622
Short name T686
Test name
Test status
Simulation time 14834966629 ps
CPU time 48.35 seconds
Started Jan 07 01:06:31 PM PST 24
Finished Jan 07 01:07:38 PM PST 24
Peak memory 209580 kb
Host smart-78258097-7ad8-4557-9a01-7a7f64a9f008
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449432622 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.449432622
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.2874070121
Short name T51
Test name
Test status
Simulation time 395209890 ps
CPU time 0.81 seconds
Started Jan 07 01:06:22 PM PST 24
Finished Jan 07 01:06:24 PM PST 24
Peak memory 200596 kb
Host smart-754ed3a1-407b-4532-8fc7-8ffd56e2a20f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874070121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.2874070121
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.1318542091
Short name T679
Test name
Test status
Simulation time 170310985622 ps
CPU time 30.57 seconds
Started Jan 07 01:06:17 PM PST 24
Finished Jan 07 01:06:49 PM PST 24
Peak memory 200832 kb
Host smart-6fc0535b-94bd-41c9-b25c-8d328f02cd00
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318542091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.1318542091
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.932268838
Short name T259
Test name
Test status
Simulation time 328464427215 ps
CPU time 389.76 seconds
Started Jan 07 01:06:31 PM PST 24
Finished Jan 07 01:13:20 PM PST 24
Peak memory 200900 kb
Host smart-cb380fb5-021d-4f50-87e9-4a1e4ff6ad3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932268838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.932268838
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.3267218584
Short name T709
Test name
Test status
Simulation time 483865213306 ps
CPU time 1063.95 seconds
Started Jan 07 01:06:12 PM PST 24
Finished Jan 07 01:23:57 PM PST 24
Peak memory 200956 kb
Host smart-ea1eaaa7-6679-4893-91a1-e1c0e427cd83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267218584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.3267218584
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.761258273
Short name T608
Test name
Test status
Simulation time 170102720494 ps
CPU time 102.55 seconds
Started Jan 07 01:06:24 PM PST 24
Finished Jan 07 01:08:09 PM PST 24
Peak memory 200904 kb
Host smart-673aba42-17bc-4e29-99a1-6d5f9dbdf0ff
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=761258273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt
_fixed.761258273
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.1101614756
Short name T231
Test name
Test status
Simulation time 168575663692 ps
CPU time 107.25 seconds
Started Jan 07 01:06:29 PM PST 24
Finished Jan 07 01:08:29 PM PST 24
Peak memory 200968 kb
Host smart-2608a3a1-04d6-462b-8b22-d35f29ed448a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101614756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.1101614756
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.1506192019
Short name T459
Test name
Test status
Simulation time 325219468235 ps
CPU time 183.2 seconds
Started Jan 07 01:06:26 PM PST 24
Finished Jan 07 01:09:33 PM PST 24
Peak memory 200840 kb
Host smart-a51f514b-243f-4824-acca-c38238b22b2a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506192019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.1506192019
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.1705616596
Short name T542
Test name
Test status
Simulation time 494384261753 ps
CPU time 1097.21 seconds
Started Jan 07 01:06:19 PM PST 24
Finished Jan 07 01:24:38 PM PST 24
Peak memory 200816 kb
Host smart-6660690a-0aa7-43b5-a09f-33f2959f5acd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705616596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.1705616596
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.2151077963
Short name T15
Test name
Test status
Simulation time 164849551657 ps
CPU time 102.62 seconds
Started Jan 07 01:06:23 PM PST 24
Finished Jan 07 01:08:07 PM PST 24
Peak memory 200908 kb
Host smart-47ccc02b-b45a-472e-b963-bdae37b05978
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151077963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.2151077963
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.1361942213
Short name T617
Test name
Test status
Simulation time 129290339390 ps
CPU time 583.36 seconds
Started Jan 07 01:06:27 PM PST 24
Finished Jan 07 01:16:14 PM PST 24
Peak memory 201320 kb
Host smart-c4190aed-05df-44ee-8fe1-a648658144f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361942213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.1361942213
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.1150864447
Short name T378
Test name
Test status
Simulation time 29989469392 ps
CPU time 18.95 seconds
Started Jan 07 01:06:27 PM PST 24
Finished Jan 07 01:06:50 PM PST 24
Peak memory 200624 kb
Host smart-1cb27d69-90e0-456f-93d4-fd163ef971f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150864447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.1150864447
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.1254149398
Short name T479
Test name
Test status
Simulation time 3911219963 ps
CPU time 10.27 seconds
Started Jan 07 01:06:35 PM PST 24
Finished Jan 07 01:07:03 PM PST 24
Peak memory 200736 kb
Host smart-29f75c75-8465-4a15-bd9b-343ee140f194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254149398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.1254149398
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.584237089
Short name T433
Test name
Test status
Simulation time 5616113641 ps
CPU time 4.87 seconds
Started Jan 07 01:06:14 PM PST 24
Finished Jan 07 01:06:21 PM PST 24
Peak memory 200708 kb
Host smart-08b58ed3-16dd-4863-880e-00e797263347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584237089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.584237089
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.202503727
Short name T809
Test name
Test status
Simulation time 113816231404 ps
CPU time 382.36 seconds
Started Jan 07 01:06:32 PM PST 24
Finished Jan 07 01:13:13 PM PST 24
Peak memory 201400 kb
Host smart-15b6d4d0-cda5-4b77-9acf-73c8905257dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202503727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.202503727
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.3605087559
Short name T116
Test name
Test status
Simulation time 353852648632 ps
CPU time 214.44 seconds
Started Jan 07 01:06:33 PM PST 24
Finished Jan 07 01:10:25 PM PST 24
Peak memory 216956 kb
Host smart-d22aa5bd-788e-4597-9862-fd34195dced6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605087559 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.3605087559
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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