Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6187	1			T17	8		T20	32		T37	20
testmodes[AdcCtrlTestmodeNormal]	5032	1			T15	1		T16	1		T17	7
testmodes[AdcCtrlTestmodeLowpower]	5267	1			T18	1		T19	1		T20	75
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3320	1			T17	3		T20	4		T37	19
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1590	1			T17	5		T20	13		T38	15
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1185	1			T20	14		T38	12		T55	12
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1600	1			T17	4		T20	16		T38	16
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1825	1			T17	2		T20	11		T21	2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1290	1			T20	26		T38	19		T55	21
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1180	1			T20	12		T38	11		T55	18
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1305	1			T20	28		T21	1		T38	21
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2572	1			T20	35		T23	2		T38	20