Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23108

1

T7

2

T29

3

T36

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20395

1

T7

2

T29

3

T36

1

auto[ADC_CTRL_FILTER_COND_OUT]

2713

1

T15

5

T16

1

T20

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18221

1

T7

2

T29

3

T36

1

auto[1]

4887

1

T15

5

T16

1

T18

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19568

1

T15

1

T16

1

T17

15

auto[1]

3540

1

T7

2

T29

3

T36

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
values[0]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	13	1			T111	1		T213	1		T214	11
values[1]	459	1			T41	28		T40	9		T50	19
values[2]	603	1			T21	4		T24	1		T106	1
values[3]	661	1			T42	22		T110	28		T153	38
values[4]	409	1			T16	1		T106	2		T33	7
values[5]	640	1			T20	8		T22	23		T116	15
values[6]	611	1			T53	1		T148	10		T153	25
values[7]	635	1			T21	30		T109	5		T110	34
values[8]	2281	1			T15	5		T18	10		T21	20
values[9]	1127	1			T19	33		T20	12		T21	15
minimum	15669	1			T7	2		T29	3		T36	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	681	1			T24	1		T41	28		T106	1
values[1]	579	1			T21	4		T118	1		T109	5
values[2]	576	1			T16	1		T106	1		T42	22
values[3]	431	1			T22	23		T106	1		T116	15
values[4]	624	1			T20	8		T104	1		T112	13
values[5]	618	1			T53	1		T110	12		T148	10
values[6]	2387	1			T18	10		T23	22		T25	3
values[7]	502	1			T15	5		T21	30		T24	1
values[8]	786	1			T19	33		T20	12		T21	35
values[9]	242	1			T107	7		T108	26		T111	1
minimum	15682	1			T7	2		T29	3		T36	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20026

1

T7

2

T29

3

T36

1

auto[1]

3082

1

T18

9

T19

17

T21

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T24	1		T50	10		T109	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T41	11		T106	1		T40	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T21	1		T118	1		T109	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T104	1		T180	1		T171	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T42	12		T111	1		T114	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T16	1		T106	1		T110	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T22	12		T106	1		T116	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T33	5		T148	6		T59	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T104	1		T153	10		T121	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T20	1		T112	13		T113	28
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T53	1		T215	12		T216	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T110	10		T148	4		T217	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1228	1			T18	10		T23	22		T25	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T35	4		T112	9		T151	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T24	1		T101	6		T119	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T15	1		T21	15		T103	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T19	18		T20	1		T21	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T21	11		T24	1		T107	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T107	1		T111	1		T171	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T108	11		T218	3		T219	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15549	1			T17	15		T20	158		T37	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T50	9		T109	5		T150	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T41	17		T220	2		T137	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T21	3		T109	4		T119	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T171	22		T221	12		T222	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T42	10		T114	5		T155	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T110	15		T182	8		T153	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T22	11		T108	5		T223	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T33	2		T148	6		T59	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T153	15		T121	2		T224	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T20	7		T175	9		T125	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T215	9		T216	15		T178	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T110	2		T148	6		T217	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	926	1			T109	4		T110	10		T139	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T35	4		T63	8		T225	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T119	13		T148	13		T63	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T15	4		T21	15		T103	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T19	15		T20	11		T21	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T21	9		T107	14		T103	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T107	6		T171	16		T226	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T108	15		T218	1		T219	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T7	2		T29	3		T36	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	8	40	83.33	8

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[values[0]]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T111	1		T213	1		T214	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T50	10		T109	1		T150	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T41	11		T40	9		T111	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T21	1		T24	1		T118	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T106	1		T104	2		T182	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T42	12		T122	13		T114	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T110	13		T153	18		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T106	1		T111	1		T223	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T16	1		T106	1		T33	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T22	12		T116	15		T108	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T20	1		T112	13		T113	28
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T53	1		T153	10		T216	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T148	4		T217	11		T123	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T109	1		T110	12		T215	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T21	15		T110	10		T35	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1171	1			T18	10		T23	22		T24	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T15	1		T21	11		T103	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T19	18		T20	1		T21	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T24	1		T107	1		T103	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15540	1			T17	15		T20	158		T37	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T214	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T50	9		T109	5		T150	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T41	17		T220	2		T154	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T21	3		T109	4		T119	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T182	8		T137	5		T171	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T42	10		T122	12		T114	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T110	15		T153	20		T171	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T223	2		T155	14		T227	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T33	2		T148	6		T59	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T22	11		T108	5		T121	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T20	7		T175	9		T125	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T153	15		T216	15		T228	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T148	6		T217	6		T141	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T109	4		T110	10		T215	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T21	15		T110	2		T35	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	891	1			T119	13		T139	14		T148	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T15	4		T21	9		T103	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T19	15		T20	11		T21	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T107	14		T103	16		T108	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T7	2		T29	3		T36	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T24	1		T50	10		T109	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T41	18		T106	1		T40	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T21	4		T118	1		T109	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T104	1		T180	1		T171	24
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T42	11		T111	1		T114	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T16	1		T106	1		T110	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T22	12		T106	1		T116	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T33	6		T148	7		T59	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T104	1		T153	16		T121	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T20	8		T112	1		T113	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T53	1		T215	10		T216	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T110	3		T148	7		T217	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1227	1			T18	1		T23	3		T25	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T35	6		T112	1		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T24	1		T101	1		T119	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T15	5		T21	16		T103	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T19	16		T20	12		T21	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T21	10		T24	1		T107	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T107	7		T111	1		T171	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T108	16		T218	3		T219	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15675	1			T7	2		T29	3		T36	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T50	9		T150	6		T121	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T41	10		T40	8		T220	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T122	12		T229	10		T230	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T171	13		T221	13		T222	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T42	11		T114	5		T231	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T110	12		T153	17		T232	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T22	11		T116	14		T108	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T33	1		T148	5		T59	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T153	9		T121	3		T114	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T112	12		T113	26		T175	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T215	11		T216	13		T233	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T110	9		T148	3		T217	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	927	1			T18	9		T23	19		T166	34
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T35	2		T112	8		T151	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T101	5		T148	15		T63	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T21	14		T58	1		T105	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T19	17		T21	9		T41	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T21	10		T103	14		T34	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T171	4		T234	10		T226	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T108	10		T218	1		T235	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T236	7		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	10	38	79.17	10

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	*	--	--	2
[auto[1]]	[maximum , values[0]]	*	--	--	4
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T111	1		T213	1		T214	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T50	10		T109	6		T150	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T41	18		T40	1		T111	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T21	4		T24	1		T118	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T106	1		T104	2		T182	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T42	11		T122	13		T114	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T110	16		T153	21		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T106	1		T111	1		T223	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T16	1		T106	1		T33	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T22	12		T116	1		T108	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T20	8		T112	1		T113	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T53	1		T153	16		T216	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T148	7		T217	7		T123	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T109	5		T110	11		T215	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T21	16		T110	3		T35	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1191	1			T18	1		T23	3		T24	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T15	5		T21	10		T103	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	370	1			T19	16		T20	12		T21	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T24	1		T107	15		T103	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15669	1			T7	2		T29	3		T36	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T50	9		T150	6		T237	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T41	10		T40	8		T220	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T121	14		T122	10		T229	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T137	5		T171	2		T125	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T42	11		T122	12		T114	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T110	12		T153	17		T171	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T238	8		T239	9		T240	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T33	1		T148	5		T59	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T22	11		T116	14		T108	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T112	12		T113	26		T175	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T153	9		T216	13		T113	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T148	3		T217	10		T141	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T110	11		T215	11		T233	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T21	14		T110	9		T35	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	871	1			T18	9		T23	19		T166	34
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T21	10		T58	1		T112	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T19	17		T21	9		T41	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T103	14		T108	10		T34	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20026

1

T7

2

T29

3

T36

1

auto[1]

auto[0]

3082

1

T18

9

T19

17

T21

33

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23108

1

T7

2

T29

3

T36

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20168

1

T7

2

T29

3

T36

1

auto[ADC_CTRL_FILTER_COND_OUT]

2940

1

T15

5

T16

1

T20

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18303

1

T7

2

T29

3

T36

1

auto[1]

4805

1

T15

5

T16

1

T18

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19568

1

T15

1

T16

1

T17

15

auto[1]

3540

1

T7

2

T29

3

T36

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	2	1			T129	1		T241	1		-	-
values[0]	19	1			T167	17		T242	1		T243	1
values[1]	540	1			T15	5		T116	15		T108	17
values[2]	477	1			T106	1		T50	19		T110	12
values[3]	602	1			T16	1		T19	33		T20	12
values[4]	662	1			T20	8		T21	20		T24	1
values[5]	605	1			T42	22		T33	7		T111	1
values[6]	617	1			T106	1		T53	1		T54	35
values[7]	595	1			T21	19		T106	1		T103	3
values[8]	464	1			T24	1		T41	28		T101	6
values[9]	2856	1			T18	10		T21	30		T23	22
minimum	15669	1			T7	2		T29	3		T36	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	646	1			T15	5		T116	15		T108	17
values[1]	493	1			T106	1		T50	19		T110	12
values[2]	719	1			T16	1		T19	33		T20	20
values[3]	635	1			T21	20		T24	1		T109	6
values[4]	602	1			T42	22		T33	7		T111	1
values[5]	570	1			T106	1		T53	1		T54	35
values[6]	2338	1			T18	10		T21	19		T23	22
values[7]	446	1			T24	1		T58	4		T119	18
values[8]	848	1			T21	30		T107	7		T103	31
values[9]	142	1			T24	1		T111	1		T104	1
minimum	15669	1			T7	2		T29	3		T36	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20026

1

T7

2

T29

3

T36

1

auto[1]

3082

1

T18

9

T19

17

T21

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T108	12		T177	11		T180	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T15	1		T116	15		T112	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T106	1		T50	10		T110	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T59	7		T215	12		T238	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T19	18		T20	1		T40	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T16	1		T20	1		T22	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T24	1		T109	1		T110	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T21	11		T111	1		T105	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T111	1		T113	13		T226	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T42	12		T33	5		T148	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T106	1		T182	1		T228	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T53	1		T54	17		T107	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1193	1			T18	10		T23	22		T25	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T21	11		T41	11		T101	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T24	1		T58	3		T119	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T104	1		T220	13		T225	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T107	1		T108	11		T110	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T21	15		T103	15		T109	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T111	1		T229	11		T244	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T24	1		T104	1		T216	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15540	1			T17	15		T20	158		T37	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T108	5		T177	16		T221	29
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T15	4		T153	20		T223	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T50	9		T110	2		T182	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T59	2		T215	9		T245	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T19	15		T20	11		T109	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T20	7		T22	11		T41	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T109	5		T110	10		T148	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T21	9		T232	16		T61	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T226	14		T183	11		T190	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T42	10		T33	2		T148	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T182	11		T228	2		T171	26
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T54	18		T107	14		T34	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	899	1			T35	4		T139	14		T149	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T21	8		T41	17		T103	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T58	1		T119	17		T222	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T220	2		T225	14		T121	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T107	6		T108	15		T110	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T21	15		T103	16		T109	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T229	3		T244	2		T172	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T216	16		T246	4		T247	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T7	2		T29	3		T36	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T129	1		T241	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T167	9		T243	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T242	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T108	12		T177	11		T180	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T15	1		T116	15		T112	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T106	1		T50	10		T110	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T59	7		T215	12		T153	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T19	18		T20	1		T40	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T16	1		T22	12		T112	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T24	1		T109	1		T110	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T20	1		T21	11		T41	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T111	1		T216	14		T113	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T42	12		T33	5		T137	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T106	1		T182	1		T228	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T53	1		T54	17		T107	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T106	1		T151	3		T189	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T21	11		T103	1		T119	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T24	1		T35	4		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T41	11		T101	6		T104	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1300	1			T18	10		T23	22		T25	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T21	15		T24	1		T103	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15540	1			T17	15		T20	158		T37	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T167	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T108	5		T177	16		T221	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T15	4		T122	9		T245	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T50	9		T110	2		T182	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T59	2		T215	9		T153	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T19	15		T20	11		T109	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T22	11		T224	8		T114	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T109	5		T110	10		T148	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T20	7		T21	9		T41	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T216	15		T177	1		T226	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T42	10		T33	2		T137	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T182	11		T228	2		T171	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T54	18		T107	14		T34	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T189	10		T171	16		T141	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T21	8		T103	2		T119	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T35	4		T121	2		T230	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T41	17		T148	13		T220	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1038	1			T107	6		T108	15		T58	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T21	15		T103	16		T109	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T7	2		T29	3		T36	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T108	6		T177	17		T180	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T15	5		T116	1		T112	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T106	1		T50	10		T110	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T59	7		T215	10		T238	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T19	16		T20	12		T40	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T16	1		T20	8		T22	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T24	1		T109	6		T110	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T21	10		T111	1		T105	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T111	1		T113	1		T226	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T42	11		T33	6		T148	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T106	1		T182	12		T228	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T53	1		T54	19		T107	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1202	1			T18	1		T23	3		T25	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T21	10		T41	18		T101	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T24	1		T58	3		T119	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T104	1		T220	3		T225	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T107	7		T108	16		T110	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T21	16		T103	17		T109	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T111	1		T229	4		T244	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T24	1		T104	1		T216	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15669	1			T7	2		T29	3		T36	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T108	11		T177	10		T221	28
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T116	14		T112	8		T153	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T50	9		T110	9		T237	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T59	2		T215	11		T238	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T19	17		T40	8		T233	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T22	11		T41	13		T112	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T110	11		T148	5		T216	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T21	10		T105	10		T234	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T113	12		T226	2		T183	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T42	11		T33	1		T148	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T228	2		T171	15		T141	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T54	16		T34	1		T112	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	890	1			T18	9		T23	19		T166	34
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T21	9		T41	10		T101	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T58	1		T222	9		T230	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T220	12		T121	14		T113	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T108	10		T110	12		T153	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T21	14		T103	14		T148	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T229	10		T169	12		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T216	10		T179	15		T248	8