Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23108

1

T7

2

T29

3

T36

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

18496

1

T7

2

T29

3

T36

1

auto[ADC_CTRL_FILTER_COND_OUT]

4612

1

T15

5

T18

10

T20

20

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18150

1

T7

2

T29

3

T36

1

auto[1]

4958

1

T16

1

T18

10

T20

20

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19568

1

T15

1

T16

1

T17

15

auto[1]

3540

1

T7

2

T29

3

T36

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	187	1			T19	33		T106	1		T118	1
values[0]	3	1			T279	1		T302	2		-	-
values[1]	603	1			T22	23		T50	19		T119	18
values[2]	699	1			T21	30		T24	1		T101	6
values[3]	712	1			T15	5		T21	15		T116	15
values[4]	667	1			T41	16		T106	1		T42	22
values[5]	467	1			T20	8		T106	1		T103	3
values[6]	503	1			T103	31		T104	1		T112	11
values[7]	443	1			T16	1		T53	1		T112	22
values[8]	621	1			T20	12		T21	20		T24	1
values[9]	2534	1			T18	10		T21	4		T23	22
minimum	15669	1			T7	2		T29	3		T36	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	509	1			T107	15		T119	18		T224	15
values[1]	2646	1			T18	10		T21	45		T23	22
values[2]	636	1			T15	5		T42	22		T116	15
values[3]	569	1			T41	16		T106	2		T54	35
values[4]	518	1			T20	8		T103	34		T111	2
values[5]	592	1			T104	1		T112	11		T148	10
values[6]	443	1			T16	1		T20	12		T21	20
values[7]	562	1			T41	28		T40	9		T34	4
values[8]	673	1			T19	33		T24	1		T33	7
values[9]	68	1			T21	4		T106	1		T220	15
minimum	15892	1			T7	2		T29	3		T36	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20026

1

T7

2

T29

3

T36

1

auto[1]

3082

1

T18

9

T19

17

T21

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T119	1		T224	1		T228	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T107	1		T122	13		T179	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T21	10		T24	1		T58	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1279	1			T18	10		T21	15		T23	22
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T107	1		T110	13		T114	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T15	1		T42	12		T116	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T41	14		T106	1		T54	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T106	1		T109	1		T119	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T103	16		T148	6		T215	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T20	1		T111	2		T137	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T112	11		T63	13		T238	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T104	1		T148	4		T105	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T16	1		T21	11		T112	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T20	1		T24	1		T53	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T34	3		T216	8		T223	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T41	11		T40	9		T104	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T19	18		T118	1		T109	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T24	1		T33	5		T113	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T21	1		T220	13		T303	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T106	1		T123	1		T249	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15581	1			T17	15		T20	158		T37	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T22	12		T50	10		T142	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T119	17		T224	14		T228	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T107	14		T122	12		T141	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T21	5		T58	1		T122	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	949	1			T21	15		T110	2		T139	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T107	6		T110	15		T114	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T15	4		T42	10		T108	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T41	2		T54	18		T108	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T109	5		T119	11		T61	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T103	18		T148	6		T215	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T20	7		T137	5		T60	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T63	9		T232	16		T141	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T148	6		T153	20		T141	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T21	9		T59	2		T182	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T20	11		T110	10		T221	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T34	1		T216	2		T223	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T41	17		T245	12		T154	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T19	15		T109	8		T119	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T33	2		T125	11		T250	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T21	3		T220	2		T304	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T249	4		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T7	2		T29	3		T36	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T22	11		T50	9		T142	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T19	18		T118	1		T109	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T106	1		T250	1		T129	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T279	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T302	2		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T119	1		T217	11		T228	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T22	12		T50	10		T122	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T24	1		T58	3		T224	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T21	15		T101	6		T107	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T21	10		T107	1		T110	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T15	1		T116	15		T182	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T41	14		T106	1		T54	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T42	12		T108	11		T119	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T103	1		T148	6		T215	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T20	1		T106	1		T109	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T103	15		T112	11		T63	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T104	1		T105	3		T153	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T16	1		T112	9		T151	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T53	1		T112	13		T148	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T21	11		T34	3		T59	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T20	1		T24	1		T110	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T21	1		T109	1		T104	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1272	1			T18	10		T23	22		T24	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15540	1			T17	15		T20	158		T37	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T19	15		T109	4		T119	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T250	4		T305	2		T306	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T119	17		T217	6		T228	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T22	11		T50	9		T122	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T58	1		T224	14		T122	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T21	15		T107	14		T110	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T21	5		T107	6		T110	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T15	4		T182	8		T216	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T41	2		T54	18		T108	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T42	10		T108	15		T119	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T103	2		T148	6		T215	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T20	7		T109	5		T244	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T103	16		T63	9		T141	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T153	20		T137	5		T60	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T175	9		T232	16		T155	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T148	6		T221	2		T141	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T21	9		T34	1		T59	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T20	11		T110	10		T154	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T21	3		T109	4		T35	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	922	1			T41	17		T33	2		T139	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T7	2		T29	3		T36	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T119	18		T224	15		T228	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T107	15		T122	13		T179	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T21	6		T24	1		T58	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1248	1			T18	1		T21	16		T23	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T107	7		T110	16		T114	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T15	5		T42	11		T116	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T41	3		T106	1		T54	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T106	1		T109	6		T119	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T103	20		T148	7		T215	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T20	8		T111	2		T137	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T112	1		T63	14		T238	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T104	1		T148	7		T105	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T16	1		T21	10		T112	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T20	12		T24	1		T53	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T34	3		T216	3		T223	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T41	18		T40	1		T104	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T19	16		T118	1		T109	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T24	1		T33	6		T113	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T21	4		T220	3		T303	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T106	1		T123	1		T249	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15755	1			T7	2		T29	3		T36	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T22	12		T50	10		T142	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T228	11		T234	6		T307	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T122	12		T179	14		T141	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T21	9		T58	1		T122	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	980	1			T18	9		T21	14		T23	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T110	12		T114	4		T217	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T42	11		T116	14		T108	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T41	13		T54	16		T108	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T105	8		T61	6		T230	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T103	14		T148	5		T215	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T137	5		T233	3		T60	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T112	10		T63	8		T238	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T148	3		T105	2		T153	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T21	10		T112	8		T151	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T110	11		T112	12		T221	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T34	1		T216	7		T183	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T41	10		T40	8		T233	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T19	17		T35	2		T153	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T33	1		T113	12		T231	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T220	12		T304	11		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T249	2		T275	10		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T217	10		T171	4		T66	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T22	11		T50	9		T142	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T19	16		T118	1		T109	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T106	1		T250	5		T129	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T279	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T302	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T119	18		T217	7		T228	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T22	12		T50	10		T122	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T24	1		T58	3		T224	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T21	16		T101	1		T107	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T21	6		T107	7		T110	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T15	5		T116	1		T182	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T41	3		T106	1		T54	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T42	11		T108	16		T119	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T103	3		T148	7		T215	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T20	8		T106	1		T109	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T103	17		T112	1		T63	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T104	1		T105	1		T153	21
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T16	1		T112	1		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T53	1		T112	1		T148	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T21	10		T34	3		T59	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T20	12		T24	1		T110	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T21	4		T109	5		T104	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1225	1			T18	1		T23	3		T24	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15669	1			T7	2		T29	3		T36	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T19	17		T308	15		T309	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T306	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T302	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T217	10		T228	11		T171	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T22	11		T50	9		T122	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T58	1		T122	10		T189	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T21	14		T101	5		T110	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T21	9		T110	12		T114	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T116	14		T216	10		T113	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T41	13		T54	16		T108	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T42	11		T108	10		T114	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T148	5		T215	11		T249	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T105	8		T233	3		T310	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T103	14		T112	10		T63	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T105	2		T153	17		T137	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T112	8		T151	2		T238	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T112	12		T148	3		T234	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T21	10		T34	1		T59	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T110	11		T233	11		T154	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T35	2		T220	12		T153	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	969	1			T18	9		T23	19		T41	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20026

1

T7

2

T29

3

T36

1

auto[1]

auto[0]

3082

1

T18

9

T19

17

T21

33