Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23108

1

T7

2

T29

3

T36

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19969

1

T7

2

T29

3

T36

1

auto[ADC_CTRL_FILTER_COND_OUT]

3139

1

T15

5

T16

1

T20

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17966

1

T7

2

T29

3

T36

1

auto[1]

5142

1

T16

1

T18

10

T20

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19568

1

T15

1

T16

1

T17

15

auto[1]

3540

1

T7

2

T29

3

T36

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	530	1			T20	4		T38	8		T55	2
values[0]	22	1			T213	1		T277	1		T66	2
values[1]	638	1			T41	16		T54	35		T107	15
values[2]	2479	1			T18	10		T20	12		T23	22
values[3]	499	1			T19	33		T21	19		T24	1
values[4]	560	1			T21	30		T50	19		T107	7
values[5]	615	1			T106	1		T119	18		T148	12
values[6]	396	1			T40	9		T110	22		T175	19
values[7]	606	1			T15	5		T20	8		T24	1
values[8]	596	1			T16	1		T21	20		T24	1
values[9]	835	1			T22	23		T106	1		T101	6
minimum	15332	1			T7	2		T29	3		T36	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	546	1			T54	35		T107	15		T109	5
values[1]	2446	1			T18	10		T19	33		T20	12
values[2]	502	1			T21	19		T24	1		T41	28
values[3]	571	1			T21	30		T106	1		T50	19
values[4]	607	1			T40	9		T148	12		T224	15
values[5]	491	1			T15	5		T20	8		T110	22
values[6]	492	1			T24	1		T53	1		T111	2
values[7]	620	1			T16	1		T21	20		T24	1
values[8]	835	1			T22	23		T106	1		T33	7
values[9]	73	1			T34	4		T215	21		T278	11
minimum	15925	1			T7	2		T29	3		T36	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20026

1

T7

2

T29

3

T36

1

auto[1]

3082

1

T18

9

T19

17

T21

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T151	3		T105	3		T220	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T54	17		T107	1		T109	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1256	1			T18	10		T19	18		T20	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T111	1		T112	9		T184	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T21	1		T24	1		T103	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T21	10		T41	11		T110	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T21	15		T107	1		T105	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T106	1		T50	10		T108	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T40	9		T114	6		T180	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T148	6		T224	1		T189	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T171	12		T290	1		T279	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T15	1		T20	1		T110	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T53	1		T111	1		T216	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T24	1		T111	1		T104	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T63	13		T113	15		T303	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T16	1		T21	11		T24	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T106	1		T110	10		T112	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T22	12		T33	5		T103	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T278	1		T279	4		T311	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T34	3		T215	12		T280	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15597	1			T17	15		T20	158		T37	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T63	1		T225	1		T256	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T220	2		T216	2		T223	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T54	18		T107	14		T109	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	929	1			T19	15		T20	11		T42	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T182	8		T137	5		T125	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T21	3		T103	2		T109	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T21	5		T41	17		T110	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T21	15		T107	6		T114	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T50	9		T108	15		T119	28
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T114	5		T171	16		T232	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T148	6		T224	14		T189	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T171	10		T258	13		T312	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T15	4		T20	7		T110	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T216	16		T142	1		T62	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T153	15		T245	4		T61	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T63	9		T249	8		T298	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T21	9		T182	11		T153	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T110	2		T223	1		T121	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T22	11		T33	2		T103	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T278	10		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T34	1		T215	9		T283	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T7	2		T29	3		T36	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T63	8		T225	14		T256	6

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	382	1			T20	4		T38	8		T55	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T34	3		T215	12		T121	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T213	1		T293	3		T313	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T277	1		T66	2		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T41	14		T151	3		T220	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T54	17		T107	1		T109	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1247	1			T18	10		T20	1		T23	22
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T111	1		T184	1		T182	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T19	18		T21	1		T24	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T21	10		T41	11		T112	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T21	15		T107	1		T103	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T50	10		T108	11		T110	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T114	6		T180	1		T268	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T106	1		T119	1		T148	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T40	9		T171	12		T232	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T110	12		T175	10		T125	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T53	1		T111	1		T128	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T15	1		T20	1		T24	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T216	11		T63	13		T113	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T16	1		T21	11		T24	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T106	1		T110	10		T112	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T22	12		T101	6		T33	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15203	1			T17	15		T20	154		T37	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T223	1		T217	6		T230	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T34	1		T215	9		T121	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T293	1		T285	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T41	2		T220	2		T216	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T54	18		T107	14		T109	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	951	1			T20	11		T42	10		T108	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T182	8		T245	12		T221	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T19	15		T21	3		T109	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T21	5		T41	17		T224	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T21	15		T107	6		T103	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T50	9		T108	15		T110	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T114	5		T171	16		T222	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T119	17		T148	6		T224	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T171	10		T232	13		T312	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T110	10		T175	9		T125	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T142	1		T62	3		T258	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T15	4		T20	7		T153	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T216	16		T63	9		T249	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T21	9		T182	11		T153	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T110	2		T121	2		T154	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T22	11		T33	2		T103	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T7	2		T29	3		T36	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T151	1		T105	1		T220	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T54	19		T107	15		T109	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1235	1			T18	1		T19	16		T20	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T111	1		T112	1		T184	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T21	4		T24	1		T103	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T21	6		T41	18		T110	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T21	16		T107	7		T105	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T106	1		T50	10		T108	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T40	1		T114	6		T180	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T148	7		T224	15		T189	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T171	11		T290	1		T279	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T15	5		T20	8		T110	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T53	1		T111	1		T216	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T24	1		T111	1		T104	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T63	14		T113	1		T303	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T16	1		T21	10		T24	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T106	1		T110	3		T112	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T22	12		T33	6		T103	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T278	11		T279	1		T311	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T34	3		T215	10		T280	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15716	1			T7	2		T29	3		T36	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T63	9		T225	15		T256	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T151	2		T105	2		T220	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T54	16		T221	15		T61	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	950	1			T18	9		T19	17		T23	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T112	8		T137	5		T238	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T150	6		T113	12		T114	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T21	9		T41	10		T110	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T21	14		T105	8		T114	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T50	9		T108	10		T148	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T40	8		T114	5		T171	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T148	5		T189	6		T249	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T171	11		T279	14		T258	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T110	11		T175	9		T125	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T216	10		T142	1		T265	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T153	9		T213	14		T146	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T63	8		T113	14		T249	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T21	10		T101	5		T153	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T110	9		T112	12		T121	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T22	11		T33	1		T103	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T279	3		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T34	1		T215	11		T283	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T41	13		T233	3		T179	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T144	6		T314	3		T253	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	375	1			T20	4		T38	8		T55	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T34	3		T215	10		T121	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T213	1		T293	3		T313	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T277	1		T66	2		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T41	3		T151	1		T220	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T54	19		T107	15		T109	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1256	1			T18	1		T20	12		T23	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T111	1		T184	1		T182	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T19	16		T21	4		T24	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T21	6		T41	18		T112	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T21	16		T107	7		T103	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T50	10		T108	16		T110	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T114	6		T180	1		T268	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T106	1		T119	18		T148	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T40	1		T171	11		T232	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T110	11		T175	10		T125	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T53	1		T111	1		T128	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T15	5		T20	8		T24	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T216	17		T63	14		T113	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T16	1		T21	10		T24	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T106	1		T110	3		T112	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T22	12		T101	1		T33	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15332	1			T7	2		T29	3		T36	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T217	10		T230	11		T315	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T34	1		T215	11		T121	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T293	1		T285	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T41	13		T151	2		T220	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T54	16		T137	5		T61	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	942	1			T18	9		T23	19		T42	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T238	8		T126	2		T221	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T19	17		T150	6		T113	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T21	9		T41	10		T112	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T21	14		T105	8		T114	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T50	9		T108	10		T110	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T114	5		T171	4		T222	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T148	5		T189	6		T249	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T40	8		T171	11		T232	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T110	11		T175	9		T125	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T142	1		T265	8		T62	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T153	9		T213	14		T310	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T216	10		T63	8		T113	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T21	10		T153	17		T122	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T110	9		T112	12		T121	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T22	11		T101	5		T33	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20026

1

T7

2

T29

3

T36

1

auto[1]

auto[0]

3082

1

T18

9

T19

17

T21

33