Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23108

1

T7

2

T29

3

T36

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20348

1

T7

2

T29

3

T36

1

auto[ADC_CTRL_FILTER_COND_OUT]

2760

1

T15

5

T16

1

T20

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18384

1

T7

2

T29

3

T36

1

auto[1]

4724

1

T15

5

T16

1

T18

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19568

1

T15

1

T16

1

T17

15

auto[1]

3540

1

T7

2

T29

3

T36

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	180	1			T21	4		T136	1		T234	8
values[0]	19	1			T221	5		T169	13		T316	1
values[1]	601	1			T21	15		T42	22		T53	1
values[2]	469	1			T106	1		T34	4		T111	1
values[3]	591	1			T106	1		T40	9		T107	7
values[4]	545	1			T24	1		T101	6		T50	19
values[5]	2532	1			T15	5		T18	10		T20	8
values[6]	602	1			T58	4		T109	6		T104	1
values[7]	590	1			T20	12		T21	20		T24	1
values[8]	499	1			T16	1		T116	15		T107	15
values[9]	811	1			T19	33		T24	1		T54	35
minimum	15669	1			T7	2		T29	3		T36	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	576	1			T42	22		T53	1		T103	31
values[1]	497	1			T106	1		T34	4		T111	1
values[2]	577	1			T106	1		T40	9		T50	19
values[3]	2433	1			T15	5		T18	10		T23	22
values[4]	632	1			T20	8		T21	30		T22	23
values[5]	573	1			T108	26		T109	6		T104	1
values[6]	563	1			T16	1		T20	12		T21	20
values[7]	588	1			T116	15		T109	5		T110	28
values[8]	762	1			T19	33		T21	4		T24	1
values[9]	72	1			T146	14		T317	1		T292	8
minimum	15835	1			T7	2		T29	3		T36	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20026

1

T7

2

T29

3

T36

1

auto[1]

3082

1

T18

9

T19

17

T21

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T42	12		T53	1		T103	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T216	14		T238	9		T123	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T34	3		T150	7		T182	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T106	1		T111	1		T182	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T136	1		T225	1		T245	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T106	1		T40	9		T50	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1203	1			T18	10		T23	22		T24	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T15	1		T101	6		T122	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T20	1		T21	15		T41	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T22	12		T106	1		T33	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T109	1		T35	4		T105	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T108	11		T104	1		T233	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T21	11		T41	14		T103	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T16	1		T20	1		T24	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T116	15		T110	13		T112	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T109	1		T112	13		T224	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T19	18		T24	1		T54	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T21	1		T220	13		T233	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T295	9		-	-		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T146	14		T317	1		T292	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15574	1			T17	15		T20	158		T37	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T21	10		T121	15		T217	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T42	10		T103	16		T119	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T216	15		T230	7		T278	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T34	1		T150	3		T182	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T182	11		T224	14		T141	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T225	14		T245	14		T125	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T50	9		T107	6		T148	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	931	1			T110	2		T139	14		T149	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T15	4		T122	12		T217	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T20	7		T21	15		T41	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T22	11		T33	2		T58	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T109	5		T35	4		T63	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T108	15		T249	9		T141	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T21	9		T41	2		T103	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T20	11		T107	14		T110	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T110	15		T223	1		T245	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T109	4		T224	8		T114	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T19	15		T54	18		T119	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T21	3		T220	2		T183	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T295	5		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T292	7		T293	1		T260	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T7	2		T29	3		T36	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T21	5		T121	12		T217	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T136	1		T234	8		T318	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T21	1		T183	8		T319	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T316	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T221	3		T169	13		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T42	12		T53	1		T103	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T21	10		T216	14		T121	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T34	3		T182	1		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T106	1		T111	1		T182	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T150	7		T136	1		T225	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T106	1		T40	9		T107	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T24	1		T110	10		T153	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T101	6		T50	10		T148	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1192	1			T18	10		T20	1		T21	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T15	1		T22	12		T106	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T109	1		T35	4		T63	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T58	3		T104	1		T233	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T21	11		T41	14		T103	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T20	1		T24	1		T108	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T116	15		T110	13		T104	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T16	1		T107	1		T109	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T19	18		T24	1		T54	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T220	13		T233	12		T114	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15540	1			T17	15		T20	158		T37	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T191	3		T253	9		T267	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T21	3		T183	5		T319	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T221	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T42	10		T103	16		T119	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T21	5		T216	15		T121	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T34	1		T182	8		T228	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T182	11		T224	14		T141	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T150	3		T225	14		T245	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T107	6		T153	15		T216	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T110	2		T153	20		T189	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T50	9		T148	13		T122	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	949	1			T20	7		T21	15		T41	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T15	4		T22	11		T33	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T109	5		T35	4		T63	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T58	1		T175	9		T249	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T21	9		T41	2		T103	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T20	11		T108	15		T110	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T110	15		T59	2		T223	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T107	14		T109	4		T224	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T19	15		T54	18		T119	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T220	2		T114	5		T259	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T7	2		T29	3		T36	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T42	11		T53	1		T103	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T216	16		T238	1		T123	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T34	3		T150	4		T182	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T106	1		T111	1		T182	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T136	1		T225	15		T245	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T106	1		T40	1		T50	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1236	1			T18	1		T23	3		T24	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T15	5		T101	1		T122	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T20	8		T21	16		T41	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T22	12		T106	1		T33	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T109	6		T35	6		T105	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T108	16		T104	1		T233	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T21	10		T41	3		T103	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T16	1		T20	12		T24	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T116	1		T110	16		T112	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T109	5		T112	1		T224	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T19	16		T24	1		T54	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T21	4		T220	3		T233	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T295	11		-	-		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T146	1		T317	1		T292	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15701	1			T7	2		T29	3		T36	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T21	6		T121	13		T217	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T42	11		T103	14		T148	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T216	13		T238	8		T230	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T34	1		T150	6		T232	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T113	6		T141	2		T222	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T125	13		T239	9		T64	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T40	8		T50	9		T148	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	898	1			T18	9		T23	19		T166	34
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T101	5		T122	12		T217	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T21	14		T41	10		T105	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T22	11		T33	1		T58	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T35	2		T105	8		T137	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T108	10		T233	3		T249	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T21	10		T41	13		T108	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T110	11		T112	8		T230	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T116	14		T110	12		T112	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T112	12		T114	14		T279	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T19	17		T54	16		T151	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T220	12		T233	11		T183	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T295	3		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T146	13		T293	1		T320	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T215	11		T273	2		T321	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T21	9		T121	14		T217	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T136	1		T234	1		T318	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T21	4		T183	6		T319	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T316	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T221	3		T169	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T42	11		T53	1		T103	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T21	6		T216	16		T121	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T34	3		T182	9		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T106	1		T111	1		T182	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T150	4		T136	1		T225	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T106	1		T40	1		T107	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T24	1		T110	3		T153	21
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T101	1		T50	10		T148	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1253	1			T18	1		T20	8		T21	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T15	5		T22	12		T106	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T109	6		T35	6		T63	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T58	3		T104	1		T233	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T21	10		T41	3		T103	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T20	12		T24	1		T108	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T116	1		T110	16		T104	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T16	1		T107	15		T109	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T19	16		T24	1		T54	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T220	3		T233	1		T114	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15669	1			T7	2		T29	3		T36	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T234	7		T318	6		T253	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T183	7		T146	13		T235	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T221	2		T169	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T42	11		T103	14		T148	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T21	9		T216	13		T121	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T34	1		T228	2		T234	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T238	8		T141	2		T222	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T150	6		T125	13		T232	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T40	8		T153	9		T216	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T110	9		T153	17		T231	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T101	5		T50	9		T148	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	888	1			T18	9		T21	14		T23	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T22	11		T33	1		T148	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T35	2		T137	5		T114	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T58	1		T233	3		T175	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T21	10		T41	13		T108	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T108	10		T110	11		T112	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T116	14		T110	12		T112	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T112	12		T114	9		T146	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T19	17		T54	16		T151	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T220	12		T233	11		T114	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20026

1

T7

2

T29

3

T36

1

auto[1]

auto[0]

3082

1

T18

9

T19

17

T21

33