Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23108

1

T7

2

T29

3

T36

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19901

1

T7

2

T29

3

T36

1

auto[ADC_CTRL_FILTER_COND_OUT]

3207

1

T19

33

T20

12

T21

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18065

1

T7

2

T29

3

T36

1

auto[1]

5043

1

T16

1

T18

10

T19

33

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19568

1

T15

1

T16

1

T17

15

auto[1]

3540

1

T7

2

T29

3

T36

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	243	1			T33	7		T104	1		T105	3
values[0]	16	1			T220	15		T262	1		-	-
values[1]	689	1			T21	30		T103	34		T109	11
values[2]	591	1			T41	44		T106	1		T107	7
values[3]	488	1			T22	23		T108	26		T148	10
values[4]	2443	1			T18	10		T20	12		T23	22
values[5]	560	1			T21	4		T116	15		T118	1
values[6]	518	1			T16	1		T20	8		T106	1
values[7]	490	1			T24	1		T40	9		T107	15
values[8]	612	1			T21	35		T101	6		T108	17
values[9]	789	1			T15	5		T19	33		T24	2
minimum	15669	1			T7	2		T29	3		T36	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	591	1			T21	30		T107	7		T103	3
values[1]	630	1			T22	23		T41	44		T106	1
values[2]	599	1			T42	22		T148	10		T150	10
values[3]	2318	1			T18	10		T20	12		T21	4
values[4]	587	1			T116	15		T118	1		T34	4
values[5]	452	1			T16	1		T20	8		T106	1
values[6]	580	1			T24	1		T101	6		T40	9
values[7]	680	1			T19	33		T21	35		T24	1
values[8]	666	1			T15	5		T24	1		T50	19
values[9]	127	1			T225	15		T238	9		T232	28
minimum	15878	1			T7	2		T29	3		T36	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20026

1

T7

2

T29

3

T36

1

auto[1]

3082

1

T18

9

T19

17

T21

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T21	15		T107	1		T103	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T109	2		T110	12		T148	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T106	1		T153	18		T122	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T22	12		T41	25		T108	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T42	12		T150	7		T151	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T148	4		T63	13		T121	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1152	1			T18	10		T21	1		T23	22
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T20	1		T106	1		T104	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T118	1		T34	3		T104	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T116	15		T110	10		T215	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T16	1		T20	1		T106	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T109	1		T110	13		T111	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T101	6		T40	9		T107	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T24	1		T108	12		T119	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T21	11		T111	1		T216	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T19	18		T21	10		T24	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T15	1		T24	1		T33	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T50	10		T54	17		T104	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T238	9		T232	12		T256	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T225	1		T249	3		T65	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15607	1			T17	15		T20	158		T37	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T103	15		T141	3		T286	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T21	15		T107	6		T103	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T109	9		T110	10		T148	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T153	20		T122	12		T228	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T22	11		T41	19		T108	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T42	10		T150	3		T182	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T148	6		T63	9		T121	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	851	1			T21	3		T139	14		T149	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T20	11		T182	11		T114	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T34	1		T250	4		T183	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T110	2		T215	9		T189	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T20	7		T58	1		T59	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T109	4		T110	15		T153	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T107	14		T148	13		T258	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T108	5		T119	2		T216	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T21	9		T216	2		T114	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T19	15		T21	5		T119	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T15	4		T33	2		T228	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T50	9		T54	18		T223	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T232	16		T256	3		T145	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T225	14		T249	4		T322	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T7	2		T29	3		T36	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T103	16		T141	2		T286	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T33	5		T105	3		T232	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T104	1		T259	1		T230	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T220	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T262	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T21	15		T103	1		T112	24
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T103	15		T109	2		T110	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T106	1		T107	1		T153	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T41	25		T119	1		T35	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T151	3		T182	1		T123	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T22	12		T108	11		T148	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1181	1			T18	10		T23	22		T25	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T20	1		T106	1		T104	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T21	1		T118	1		T34	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T116	15		T110	10		T215	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T16	1		T20	1		T106	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T109	1		T110	13		T111	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T40	9		T107	1		T111	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T24	1		T119	1		T216	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T21	11		T101	6		T111	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T21	10		T108	12		T119	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T15	1		T24	1		T238	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T19	18		T24	1		T50	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15540	1			T17	15		T20	158		T37	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T33	2		T232	16		T256	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T259	10		T230	7		T172	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T220	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T21	15		T103	2		T63	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T103	16		T109	9		T110	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T107	6		T153	20		T122	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T41	19		T119	11		T35	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T182	8		T237	7		T222	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T22	11		T108	15		T148	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	869	1			T42	10		T139	14		T149	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T20	11		T63	9		T114	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T21	3		T34	1		T250	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T110	2		T215	9		T182	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T20	7		T58	1		T59	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T109	4		T110	15		T153	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T107	14		T148	13		T114	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T119	2		T216	15		T122	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T21	9		T216	2		T114	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T21	5		T108	5		T119	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T15	4		T228	2		T249	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T19	15		T50	9		T54	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T7	2		T29	3		T36	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T21	16		T107	7		T103	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T109	11		T110	11		T148	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T106	1		T153	21		T122	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T22	12		T41	21		T108	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T42	11		T150	4		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T148	7		T63	14		T121	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1141	1			T18	1		T21	4		T23	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T20	12		T106	1		T104	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T118	1		T34	3		T104	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T116	1		T110	3		T215	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T16	1		T20	8		T106	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T109	5		T110	16		T111	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T101	1		T40	1		T107	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T24	1		T108	6		T119	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T21	10		T111	1		T216	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T19	16		T21	6		T24	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T15	5		T24	1		T33	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T50	10		T54	19		T104	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T238	1		T232	17		T256	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T225	15		T249	5		T65	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15761	1			T7	2		T29	3		T36	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T103	17		T141	3		T286	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T21	14		T112	22		T232	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T110	11		T148	5		T105	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T153	17		T122	12		T228	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T22	11		T41	23		T108	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T42	11		T150	6		T151	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T148	3		T63	8		T121	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	862	1			T18	9		T23	19		T166	34
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T114	5		T179	15		T226	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T34	1		T112	8		T183	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T116	14		T110	9		T215	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T58	1		T59	2		T114	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T110	12		T153	9		T216	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T101	5		T40	8		T148	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T108	11		T216	13		T122	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T21	10		T216	7		T113	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T19	17		T21	9		T137	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T33	1		T105	2		T113	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T50	9		T54	16		T234	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T238	8		T232	11		T145	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T249	2		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T220	12		T221	13		T230	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T103	14		T141	2		T286	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T33	6		T105	1		T232	17
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T104	1		T259	11		T230	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T220	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T262	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T21	16		T103	3		T112	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T103	17		T109	11		T110	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T106	1		T107	7		T153	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T41	21		T119	12		T35	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T151	1		T182	9		T123	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T22	12		T108	16		T148	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1159	1			T18	1		T23	3		T25	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T20	12		T106	1		T104	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T21	4		T118	1		T34	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T116	1		T110	3		T215	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T16	1		T20	8		T106	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T109	5		T110	16		T111	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T40	1		T107	15		T111	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T24	1		T119	3		T216	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T21	10		T101	1		T111	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T21	6		T108	6		T119	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T15	5		T24	1		T238	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T19	16		T24	1		T50	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15669	1			T7	2		T29	3		T36	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T33	1		T105	2		T232	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T230	11		T235	12		T236	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T220	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T21	14		T112	22		T221	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T103	14		T110	11		T105	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T153	17		T122	12		T228	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T41	23		T35	2		T148	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T151	2		T237	7		T222	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T22	11		T108	10		T148	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	891	1			T18	9		T23	19		T42	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T63	8		T114	5		T179	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T34	1		T112	8		T154	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T116	14		T110	9		T215	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T58	1		T59	2		T177	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T110	12		T153	9		T216	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T40	8		T148	15		T233	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T216	13		T122	10		T179	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T21	10		T101	5		T216	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T21	9		T108	11		T137	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T238	8		T113	14		T228	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T19	17		T50	9		T54	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20026

1

T7

2

T29

3

T36

1

auto[1]

auto[0]

3082

1

T18

9

T19

17

T21

33