Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23108

1

T7

2

T29

3

T36

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20244

1

T7

2

T29

3

T36

1

auto[ADC_CTRL_FILTER_COND_OUT]

2864

1

T16

1

T19

33

T20

20

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17896

1

T7

2

T29

3

T36

1

auto[1]

5212

1

T16

1

T18

10

T19

33

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19568

1

T15

1

T16

1

T17

15

auto[1]

3540

1

T7

2

T29

3

T36

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	180	1			T108	17		T35	8		T184	1
values[0]	59	1			T50	19		T259	11		T143	17
values[1]	499	1			T33	7		T109	6		T34	4
values[2]	2395	1			T18	10		T23	22		T25	3
values[3]	639	1			T15	5		T22	23		T24	1
values[4]	682	1			T19	33		T21	50		T106	1
values[5]	641	1			T20	12		T41	28		T107	15
values[6]	602	1			T24	1		T107	7		T118	1
values[7]	565	1			T20	8		T24	1		T42	22
values[8]	508	1			T16	1		T21	19		T106	1
values[9]	669	1			T40	9		T54	35		T216	39
minimum	15669	1			T7	2		T29	3		T36	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	537	1			T101	6		T33	7		T109	6
values[1]	2458	1			T18	10		T23	22		T25	3
values[2]	653	1			T19	33		T22	23		T24	1
values[3]	674	1			T15	5		T20	12		T21	50
values[4]	722	1			T41	28		T107	15		T118	1
values[5]	509	1			T24	1		T42	22		T107	7
values[6]	508	1			T20	8		T24	1		T109	5
values[7]	484	1			T16	1		T21	19		T106	1
values[8]	690	1			T40	9		T54	35		T108	17
values[9]	67	1			T184	1		T123	1		T127	1
minimum	15806	1			T7	2		T29	3		T36	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20026

1

T7

2

T29

3

T36

1

auto[1]

3082

1

T18

9

T19

17

T21

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T101	6		T109	1		T34	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T33	5		T150	7		T215	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1262	1			T18	10		T23	22		T25	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T104	1		T182	1		T63	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T41	14		T58	3		T119	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T19	18		T22	12		T24	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T15	1		T21	11		T109	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T20	1		T21	15		T106	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T107	1		T118	1		T111	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T41	11		T103	15		T220	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T24	1		T42	12		T107	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T108	11		T59	7		T63	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T109	1		T238	9		T222	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T20	1		T24	1		T111	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T21	11		T106	1		T122	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T16	1		T119	1		T111	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T54	17		T108	12		T35	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T40	9		T216	14		T269	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T184	1		T123	1		T127	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T253	8		T276	14		T271	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15586	1			T17	15		T20	158		T37	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T50	10		T105	9		T323	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T109	5		T34	1		T114	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T33	2		T150	3		T215	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	950	1			T110	10		T119	2		T139	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T182	8		T63	9		T171	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T41	2		T58	1		T119	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T19	15		T22	11		T148	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T15	4		T21	9		T109	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T20	11		T21	15		T110	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T107	14		T148	6		T216	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T41	17		T103	16		T220	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T42	10		T107	6		T103	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T108	15		T59	2		T63	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T109	4		T222	12		T229	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T20	7		T148	13		T232	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T21	8		T122	12		T178	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T119	17		T232	13		T183	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T54	18		T108	5		T35	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T216	15		T228	2		T125	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T253	9		T271	2		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T7	2		T29	3		T36	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T50	9		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T108	12		T35	4		T184	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T228	3		T129	1		T324	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T259	1		T143	1		T267	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T50	10		T273	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T109	1		T34	3		T105	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T33	5		T150	7		T105	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1200	1			T18	10		T23	22		T25	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T104	1		T63	13		T234	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T15	1		T41	14		T58	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T22	12		T24	1		T53	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T21	11		T109	1		T110	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T19	18		T21	15		T106	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T107	1		T111	1		T112	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T20	1		T41	11		T103	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T24	1		T107	1		T118	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T108	11		T59	7		T153	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T42	12		T109	1		T238	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T20	1		T24	1		T111	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T21	11		T106	1		T122	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T16	1		T119	1		T111	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T54	17		T216	8		T114	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T40	9		T216	14		T269	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15540	1			T17	15		T20	158		T37	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T108	5		T35	4		T137	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T228	2		T324	5		T271	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T259	10		T143	16		T267	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T50	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T109	5		T34	1		T122	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T33	2		T150	3		T215	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	897	1			T119	2		T139	14		T149	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T63	9		T249	9		T61	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T15	4		T41	2		T58	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T22	11		T217	5		T171	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T21	9		T109	4		T110	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T19	15		T21	15		T110	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T107	14		T148	6		T216	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T20	11		T41	17		T103	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T107	6		T103	2		T245	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T108	15		T59	2		T153	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T42	10		T109	4		T229	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T20	7		T148	13		T141	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T21	8		T122	12		T178	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T119	17		T232	29		T259	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T54	18		T216	2		T114	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T216	15		T125	7		T60	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T7	2		T29	3		T36	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T101	1		T109	6		T34	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T33	6		T150	4		T215	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1252	1			T18	1		T23	3		T25	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T104	1		T182	9		T63	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T41	3		T58	3		T119	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T19	16		T22	12		T24	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T15	5		T21	10		T109	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T20	12		T21	16		T106	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T107	15		T118	1		T111	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T41	18		T103	17		T220	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T24	1		T42	11		T107	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T108	16		T59	7		T63	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T109	5		T238	1		T222	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T20	8		T24	1		T111	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T21	10		T106	1		T122	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T16	1		T119	18		T111	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T54	19		T108	6		T35	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T40	1		T216	16		T269	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T184	1		T123	1		T127	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T253	10		T276	1		T271	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15741	1			T7	2		T29	3		T36	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T50	10		T105	1		T323	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T101	5		T34	1		T105	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T33	1		T150	6		T215	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	960	1			T18	9		T23	19		T166	34
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T63	8		T113	14		T171	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T41	13		T58	1		T153	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T19	17		T22	11		T116	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T21	10		T110	12		T112	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T21	14		T110	9		T151	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T148	3		T216	10		T114	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T41	10		T103	14		T220	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T42	11		T112	10		T233	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T108	10		T59	2		T142	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T238	8		T222	9		T229	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T148	15		T232	11		T141	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T21	9		T122	12		T231	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T233	3		T179	15		T234	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T54	16		T108	11		T35	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T40	8		T216	13		T228	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T255	16		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T253	7		T276	13		T271	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T113	12		T122	10		T237	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T50	9		T105	8		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T108	6		T35	6		T184	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T228	3		T129	1		T324	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T259	11		T143	17		T267	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T50	10		T273	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T109	6		T34	3		T105	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T33	6		T150	4		T105	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1192	1			T18	1		T23	3		T25	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T104	1		T63	14		T234	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T15	5		T41	3		T58	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T22	12		T24	1		T53	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T21	10		T109	5		T110	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T19	16		T21	16		T106	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T107	15		T111	1		T112	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T20	12		T41	18		T103	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T24	1		T107	7		T118	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T108	16		T59	7		T153	21
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T42	11		T109	5		T238	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T20	8		T24	1		T111	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T21	10		T106	1		T122	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T16	1		T119	18		T111	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T54	19		T216	3		T114	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T40	1		T216	16		T269	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15669	1			T7	2		T29	3		T36	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T108	11		T35	2		T137	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T228	2		T324	8		T271	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T50	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T34	1		T105	2		T113	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T33	1		T150	6		T105	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	905	1			T18	9		T23	19		T166	34
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T63	8		T234	7		T249	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T41	13		T58	1		T110	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T22	11		T113	14		T217	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T21	10		T110	12		T217	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T19	17		T21	14		T116	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T112	8		T148	3		T216	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T41	10		T103	14		T220	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T112	10		T233	11		T126	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T108	10		T59	2		T153	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T42	11		T238	8		T229	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T148	15		T141	2		T218	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T21	9		T122	12		T234	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T179	15		T234	10		T232	23
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T54	16		T216	7		T114	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T40	8		T216	13		T233	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20026

1

T7

2

T29

3

T36

1

auto[1]

auto[0]

3082

1

T18

9

T19

17

T21

33