Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23108

1

T7

2

T29

3

T36

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20014

1

T7

2

T29

3

T36

1

auto[ADC_CTRL_FILTER_COND_OUT]

3094

1

T20

20

T21

20

T22

23

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18154

1

T7

2

T29

3

T36

1

auto[1]

4954

1

T16

1

T18

10

T19

33

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19568

1

T15

1

T16

1

T17

15

auto[1]

3540

1

T7

2

T29

3

T36

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	40	1			T229	14		T292	8		T325	18
values[0]	60	1			T15	5		T114	11		T128	1
values[1]	483	1			T50	19		T107	7		T103	3
values[2]	778	1			T20	12		T21	4		T108	17
values[3]	714	1			T24	1		T54	35		T110	28
values[4]	498	1			T16	1		T116	15		T53	1
values[5]	2405	1			T18	10		T19	33		T23	22
values[6]	628	1			T22	23		T41	16		T106	1
values[7]	450	1			T101	6		T103	31		T104	1
values[8]	467	1			T21	20		T24	1		T58	4
values[9]	916	1			T20	8		T21	45		T106	2
minimum	15669	1			T7	2		T29	3		T36	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	751	1			T15	5		T20	12		T50	19
values[1]	819	1			T21	4		T108	17		T109	5
values[2]	530	1			T16	1		T116	15		T54	35
values[3]	2348	1			T18	10		T23	22		T24	2
values[4]	548	1			T19	33		T41	44		T106	1
values[5]	760	1			T22	23		T42	22		T40	9
values[6]	308	1			T101	6		T105	9		T184	1
values[7]	537	1			T21	20		T24	1		T106	1
values[8]	663	1			T20	8		T108	26		T34	4
values[9]	157	1			T21	45		T106	1		T110	22
minimum	15687	1			T7	2		T29	3		T36	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20026

1

T7

2

T29

3

T36

1

auto[1]

3082

1

T18

9

T19

17

T21

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T15	1		T50	10		T107	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T20	1		T220	13		T182	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T21	1		T109	1		T119	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T108	12		T111	1		T215	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T16	1		T116	15		T54	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T110	13		T111	1		T123	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1176	1			T18	10		T23	22		T24	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T24	1		T53	1		T119	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T19	18		T41	14		T106	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T41	11		T109	1		T228	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T118	1		T104	1		T112	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T22	12		T42	12		T40	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T184	1		T269	1		T136	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T101	6		T105	9		T223	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T58	3		T148	6		T225	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T21	11		T24	1		T106	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T148	16		T231	3		T249	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T20	1		T108	11		T34	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T21	25		T106	1		T250	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T110	12		T125	14		T154	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15546	1			T17	15		T20	158		T37	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T326	1		T262	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T15	4		T50	9		T107	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T20	11		T220	2		T182	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T21	3		T109	4		T119	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T108	5		T215	9		T153	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T54	18		T216	15		T60	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T110	15		T141	14		T183	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	858	1			T107	14		T35	4		T139	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T119	11		T148	6		T137	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T19	15		T41	2		T33	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T41	17		T109	4		T228	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T63	9		T224	14		T175	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T22	11		T42	10		T103	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T121	2		T125	7		T244	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T223	1		T327	14		T328	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T58	1		T148	6		T225	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T21	9		T110	2		T150	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T148	13		T249	9		T286	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T20	7		T108	15		T34	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T21	20		T250	4		T191	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T110	10		T125	11		T229	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T7	2		T29	3		T36	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T326	4		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T325	12		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T229	11		T292	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T15	1		T114	6		T128	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T190	6		T329	6		T326	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T50	10		T107	1		T103	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T220	13		T182	1		T122	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T21	1		T109	2		T119	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T20	1		T108	12		T111	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T54	17		T111	1		T104	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T24	1		T110	13		T111	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T16	1		T116	15		T107	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T53	1		T148	4		T105	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1230	1			T18	10		T19	18		T23	22
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T41	11		T119	1		T153	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T41	14		T106	1		T118	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T22	12		T42	12		T40	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T104	1		T184	1		T269	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T101	6		T103	15		T105	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T58	3		T148	6		T225	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T21	11		T24	1		T110	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T21	25		T106	1		T148	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T20	1		T106	1		T108	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15540	1			T17	15		T20	158		T37	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T325	6		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T229	3		T292	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T15	4		T114	5		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T190	5		T329	9		T326	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T50	9		T107	6		T103	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T220	2		T182	8		T122	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T21	3		T109	9		T119	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T20	11		T108	5		T122	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T54	18		T216	15		T245	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T110	15		T215	9		T153	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T107	14		T35	4		T60	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T148	6		T137	5		T115	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	877	1			T19	15		T33	2		T139	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T41	17		T119	11		T153	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T41	2		T63	9		T175	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T22	11		T42	10		T109	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T121	2		T224	14		T125	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T103	16		T223	1		T171	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T58	1		T148	6		T225	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T21	9		T110	2		T119	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T21	20		T148	13		T250	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T20	7		T108	15		T34	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T7	2		T29	3		T36	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T15	5		T50	10		T107	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T20	12		T220	3		T182	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T21	4		T109	5		T119	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T108	6		T111	1		T215	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T16	1		T116	1		T54	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T110	16		T111	1		T123	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1154	1			T18	1		T23	3		T24	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T24	1		T53	1		T119	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T19	16		T41	3		T106	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T41	18		T109	5		T228	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T118	1		T104	1		T112	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T22	12		T42	11		T40	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T184	1		T269	1		T136	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T101	1		T105	1		T223	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T58	3		T148	7		T225	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T21	10		T24	1		T106	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T148	14		T231	1		T249	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T20	8		T108	16		T34	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T21	22		T106	1		T250	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T110	11		T125	12		T154	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15676	1			T7	2		T29	3		T36	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T326	5		T262	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T50	9		T114	14		T167	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T220	12		T122	22		T228	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T112	12		T216	7		T217	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T108	11		T215	11		T153	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T116	14		T54	16		T216	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T110	12		T141	10		T183	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	880	1			T18	9		T23	19		T166	34
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T148	3		T105	2		T137	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T19	17		T41	13		T33	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T41	10		T228	2		T221	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T112	8		T63	8		T175	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T22	11		T42	11		T40	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T121	3		T125	7		T169	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T101	5		T105	8		T265	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T58	1		T148	5		T330	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T21	10		T110	9		T150	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T148	15		T231	2		T249	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T108	10		T34	1		T112	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T21	23		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T110	11		T125	13		T229	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T237	5		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T325	7		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T229	4		T292	8		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T15	5		T114	6		T128	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T190	7		T329	10		T326	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T50	10		T107	7		T103	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T220	3		T182	9		T122	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T21	4		T109	11		T119	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T20	12		T108	6		T111	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T54	19		T111	1		T104	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T24	1		T110	16		T111	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T16	1		T116	1		T107	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T53	1		T148	7		T105	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1182	1			T18	1		T19	16		T23	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T41	18		T119	12		T153	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T41	3		T106	1		T118	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T22	12		T42	11		T40	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T104	1		T184	1		T269	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T101	1		T103	17		T105	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T58	3		T148	7		T225	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T21	10		T24	1		T110	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T21	22		T106	1		T148	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T20	8		T106	1		T108	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15669	1			T7	2		T29	3		T36	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T325	11		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T229	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T114	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T190	4		T329	5		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T50	9		T237	5		T167	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T220	12		T122	12		T179	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T112	12		T216	7		T114	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T108	11		T122	10		T228	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T54	16		T216	13		T179	28
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T110	12		T215	11		T153	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T116	14		T35	2		T60	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T148	3		T105	2		T137	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	925	1			T18	9		T19	17		T23	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T41	10		T153	9		T154	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T41	13		T112	8		T63	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T22	11		T42	11		T40	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T121	3		T125	7		T296	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T101	5		T103	14		T105	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T58	1		T148	5		T231	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T21	10		T110	9		T150	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T21	23		T148	15		T249	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T108	10		T34	1		T110	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20026

1

T7

2

T29

3

T36

1

auto[1]

auto[0]

3082

1

T18

9

T19

17

T21

33