Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

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Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T129	1		T241	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T167	9		T243	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T242	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T108	6		T177	17		T180	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T15	5		T116	1		T112	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T106	1		T50	10		T110	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T59	7		T215	10		T153	21
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T19	16		T20	12		T40	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T16	1		T22	12		T112	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T24	1		T109	6		T110	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T20	8		T21	10		T41	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T111	1		T216	16		T113	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T42	11		T33	6		T137	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T106	1		T182	12		T228	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T53	1		T54	19		T107	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T106	1		T151	1		T189	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T21	10		T103	3		T119	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T24	1		T35	6		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T41	18		T101	1		T104	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1362	1			T18	1		T23	3		T25	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T21	16		T24	1		T103	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15669	1			T7	2		T29	3		T36	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T167	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T108	11		T177	10		T221	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T116	14		T112	8		T122	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T50	9		T110	9		T126	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T59	2		T215	11		T153	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T19	17		T40	8		T114	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T22	11		T112	10		T238	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T110	11		T148	5		T233	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T21	10		T41	13		T105	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T216	13		T113	12		T226	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T42	11		T33	1		T137	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T228	2		T171	11		T141	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T54	16		T34	1		T112	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T151	2		T189	6		T171	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T21	9		T233	3		T113	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T35	2		T121	3		T230	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T41	10		T101	5		T148	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	976	1			T18	9		T23	19		T166	34
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T21	14		T103	14		T150	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20026

1

T7

2

T29

3

T36

1

auto[1]

auto[0]

3082

1

T18

9

T19

17

T21

33