Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23108

1

T7

2

T29

3

T36

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

18559

1

T7

2

T29

3

T36

1

auto[ADC_CTRL_FILTER_COND_OUT]

4549

1

T15

5

T18

10

T20

20

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18138

1

T7

2

T29

3

T36

1

auto[1]

4970

1

T16

1

T18

10

T20

20

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19568

1

T15

1

T16

1

T17

15

auto[1]

3540

1

T7

2

T29

3

T36

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	64	1			T50	19		T179	15		T234	7
values[1]	529	1			T22	23		T58	4		T119	18
values[2]	698	1			T21	30		T24	1		T101	6
values[3]	715	1			T15	5		T21	15		T42	22
values[4]	656	1			T41	16		T106	1		T54	35
values[5]	445	1			T20	8		T106	1		T103	3
values[6]	570	1			T103	31		T104	1		T112	11
values[7]	445	1			T53	1		T112	22		T148	10
values[8]	607	1			T16	1		T20	12		T21	20
values[9]	2710	1			T18	10		T19	33		T21	4
minimum	15669	1			T7	2		T29	3		T36	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	668	1			T22	23		T50	19		T107	15
values[1]	2616	1			T18	10		T21	45		T23	22
values[2]	698	1			T15	5		T42	22		T116	15
values[3]	518	1			T41	16		T106	2		T54	35
values[4]	584	1			T20	8		T103	34		T111	2
values[5]	570	1			T104	1		T112	11		T148	10
values[6]	426	1			T16	1		T20	12		T24	1
values[7]	608	1			T21	20		T24	1		T41	28
values[8]	610	1			T19	33		T106	1		T33	7
values[9]	117	1			T21	4		T220	15		T216	29
minimum	15693	1			T7	2		T29	3		T36	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20026

1

T7

2

T29

3

T36

1

auto[1]

3082

1

T18

9

T19

17

T21

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T119	1		T224	1		T217	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T22	12		T50	10		T107	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T21	10		T24	1		T58	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1265	1			T18	10		T21	15		T23	22
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T107	1		T110	13		T217	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T15	1		T42	12		T116	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T41	14		T106	1		T54	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T106	1		T108	11		T109	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T103	16		T148	6		T215	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T20	1		T111	2		T137	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T112	11		T153	18		T63	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T104	1		T148	4		T105	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T16	1		T151	3		T59	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T20	1		T24	1		T53	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T21	11		T34	3		T112	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T24	1		T41	11		T40	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T19	18		T33	5		T118	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T106	1		T113	13		T231	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T21	1		T220	13		T216	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T123	1		T179	16		T249	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15541	1			T17	15		T20	158		T37	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T179	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T119	17		T224	14		T217	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T22	11		T50	9		T107	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T21	5		T58	1		T122	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	934	1			T21	15		T110	2		T139	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T107	6		T110	15		T217	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T15	4		T42	10		T182	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T41	2		T54	18		T108	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T108	15		T109	5		T61	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T103	18		T148	6		T215	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T20	7		T137	5		T60	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T153	20		T63	9		T232	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T148	6		T141	4		T222	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T59	2		T216	2		T175	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T20	11		T110	10		T221	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T21	9		T34	1		T182	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T41	17		T245	12		T154	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T19	15		T33	2		T109	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T125	11		T250	4		T230	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T21	3		T220	2		T216	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T249	4		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T7	2		T29	3		T36	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T234	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T50	10		T179	15		T251	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T58	3		T119	1		T217	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T22	12		T122	13		T180	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T24	1		T224	1		T122	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T21	15		T101	6		T107	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T21	10		T107	1		T110	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T15	1		T42	12		T116	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T41	14		T106	1		T54	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T108	11		T111	1		T184	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T103	1		T119	1		T148	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T20	1		T106	1		T109	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T103	15		T112	11		T153	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T104	1		T105	3		T137	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T112	9		T151	3		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T53	1		T112	13		T148	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T16	1		T21	11		T34	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T20	1		T24	1		T40	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T19	18		T21	1		T33	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1280	1			T18	10		T23	22		T24	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15540	1			T17	15		T20	158		T37	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T50	9		T252	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T58	1		T119	17		T217	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T22	11		T122	12		T141	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T224	14		T122	9		T189	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T21	15		T107	14		T110	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T21	5		T107	6		T110	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T15	4		T42	10		T182	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T41	2		T54	18		T108	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T108	15		T216	16		T224	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T103	2		T119	11		T148	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T20	7		T109	5		T244	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T103	16		T153	20		T63	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T137	5		T60	4		T222	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T175	9		T232	16		T155	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T148	6		T221	2		T232	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T21	9		T34	1		T59	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T20	11		T110	10		T154	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T19	15		T21	3		T33	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	935	1			T41	17		T139	14		T149	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T7	2		T29	3		T36	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T119	18		T224	15		T217	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T22	12		T50	10		T107	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T21	6		T24	1		T58	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1235	1			T18	1		T21	16		T23	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T107	7		T110	16		T217	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T15	5		T42	11		T116	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T41	3		T106	1		T54	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T106	1		T108	16		T109	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T103	20		T148	7		T215	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T20	8		T111	2		T137	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T112	1		T153	21		T63	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T104	1		T148	7		T105	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T16	1		T151	1		T59	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T20	12		T24	1		T53	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T21	10		T34	3		T112	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T24	1		T41	18		T40	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T19	16		T33	6		T118	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T106	1		T113	1		T231	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T21	4		T220	3		T216	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T123	1		T179	1		T249	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15678	1			T7	2		T29	3		T36	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T179	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T217	10		T228	11		T171	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T22	11		T50	9		T122	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T21	9		T58	1		T122	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	964	1			T18	9		T21	14		T23	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T110	12		T217	5		T171	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T42	11		T116	14		T216	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T41	13		T54	16		T108	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T108	10		T105	8		T61	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T103	14		T148	5		T215	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T137	5		T233	3		T60	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T112	10		T153	17		T63	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T148	3		T105	2		T126	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T151	2		T59	2		T216	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T110	11		T112	12		T221	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T21	10		T34	1		T112	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T41	10		T40	8		T233	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T19	17		T33	1		T35	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T113	12		T231	2		T179	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T220	12		T216	13		T253	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T179	15		T249	2		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T179	14		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T234	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T50	10		T179	1		T251	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T58	3		T119	18		T217	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T22	12		T122	13		T180	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T24	1		T224	15		T122	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T21	16		T101	1		T107	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T21	6		T107	7		T110	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T15	5		T42	11		T116	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T41	3		T106	1		T54	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T108	16		T111	1		T184	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T103	3		T119	12		T148	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T20	8		T106	1		T109	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T103	17		T112	1		T153	21
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T104	1		T105	1		T137	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T112	1		T151	1		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T53	1		T112	1		T148	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T16	1		T21	10		T34	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T20	12		T24	1		T40	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T19	16		T21	4		T33	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1244	1			T18	1		T23	3		T24	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15669	1			T7	2		T29	3		T36	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T234	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T50	9		T179	14		T252	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T58	1		T217	10		T228	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T22	11		T122	12		T141	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T122	10		T189	6		T177	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T21	14		T101	5		T110	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T21	9		T110	12		T217	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T42	11		T116	14		T113	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T41	13		T54	16		T108	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T108	10		T216	10		T114	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T148	5		T215	11		T249	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T105	8		T233	3		T213	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T103	14		T112	10		T153	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T105	2		T137	5		T60	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T112	8		T151	2		T238	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T112	12		T148	3		T234	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T21	10		T34	1		T59	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T40	8		T110	11		T233	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T19	17		T33	1		T35	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	971	1			T18	9		T23	19		T41	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20026

1

T7

2

T29

3

T36

1

auto[1]

auto[0]

3082

1

T18

9

T19

17

T21

33