Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23108

1

T7

2

T29

3

T36

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19907

1

T7

2

T29

3

T36

1

auto[ADC_CTRL_FILTER_COND_OUT]

3201

1

T19

33

T20

12

T21

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18084

1

T7

2

T29

3

T36

1

auto[1]

5024

1

T16

1

T18

10

T19

33

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19568

1

T15

1

T16

1

T17

15

auto[1]

3540

1

T7

2

T29

3

T36

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	17	1			T65	3		T254	14		-	-
values[0]	27	1			T248	9		T202	5		T255	12
values[1]	607	1			T21	30		T103	31		T109	11
values[2]	648	1			T41	44		T106	1		T107	7
values[3]	514	1			T22	23		T108	26		T148	10
values[4]	2509	1			T18	10		T20	12		T21	4
values[5]	458	1			T116	15		T118	1		T34	4
values[6]	547	1			T16	1		T20	8		T24	1
values[7]	465	1			T107	15		T119	3		T111	1
values[8]	616	1			T19	33		T21	15		T101	6
values[9]	1031	1			T15	5		T21	20		T24	2
minimum	15669	1			T7	2		T29	3		T36	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	767	1			T21	30		T107	7		T103	34
values[1]	631	1			T22	23		T41	44		T106	1
values[2]	569	1			T42	22		T148	10		T150	10
values[3]	2391	1			T18	10		T20	12		T21	4
values[4]	592	1			T20	8		T116	15		T118	1
values[5]	467	1			T16	1		T106	1		T58	4
values[6]	523	1			T24	1		T101	6		T40	9
values[7]	699	1			T19	33		T21	35		T24	1
values[8]	641	1			T15	5		T24	1		T54	35
values[9]	150	1			T225	15		T238	9		T249	7
minimum	15678	1			T7	2		T29	3		T36	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20026

1

T7

2

T29

3

T36

1

auto[1]

3082

1

T18

9

T19

17

T21

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T21	15		T107	1		T103	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T103	15		T109	1		T110	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T106	1		T112	13		T153	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T22	12		T41	25		T108	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T42	12		T150	7		T151	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T148	4		T63	13		T121	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1160	1			T18	10		T21	1		T23	22
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T20	1		T106	1		T104	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T20	1		T118	1		T104	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T116	15		T110	10		T215	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T16	1		T106	1		T58	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T109	1		T110	13		T111	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T101	6		T40	9		T107	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T24	1		T108	12		T119	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T21	11		T111	1		T216	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T19	18		T21	10		T24	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T15	1		T24	1		T33	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T54	17		T104	1		T223	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T238	9		T256	1		T257	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T225	1		T249	3		T65	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15549	1			T17	15		T20	158		T37	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T21	15		T107	6		T103	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T103	16		T109	4		T110	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T153	20		T122	12		T219	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T22	11		T41	19		T108	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T42	10		T150	3		T182	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T148	6		T63	9		T121	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	872	1			T21	3		T34	1		T139	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T20	11		T182	11		T121	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T20	7		T250	4		T183	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T110	2		T215	9		T189	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T58	1		T59	2		T114	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T109	4		T110	15		T153	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T107	14		T148	13		T258	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T108	5		T119	2		T122	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T21	9		T216	2		T114	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T19	15		T21	5		T50	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T15	4		T33	2		T228	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T54	18		T223	1		T259	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T256	3		T257	19		T260	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T225	14		T249	4		T261	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T7	2		T29	3		T36	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T65	3		T254	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T248	9		T202	3		T255	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T262	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T21	15		T109	1		T112	24
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T103	15		T109	1		T110	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T106	1		T107	1		T103	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T41	25		T119	1		T148	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T151	3		T182	1		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T22	12		T108	11		T148	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1213	1			T18	10		T21	1		T23	22
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T20	1		T106	1		T104	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T118	1		T34	3		T124	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T116	15		T110	10		T182	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T16	1		T20	1		T106	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T24	1		T109	1		T110	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T107	1		T111	1		T148	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T119	1		T216	14		T122	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T101	6		T40	9		T111	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T19	18		T21	10		T108	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T15	1		T21	11		T24	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T24	1		T50	10		T54	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15540	1			T17	15		T20	158		T37	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T254	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T202	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T21	15		T109	5		T220	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T103	16		T109	4		T110	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T107	6		T103	2		T153	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T41	19		T119	11		T148	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T182	8		T237	7		T222	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T22	11		T108	15		T148	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	899	1			T21	3		T42	10		T139	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T20	11		T63	9		T114	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T34	1		T250	4		T154	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T110	2		T182	11		T115	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T20	7		T58	1		T59	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T109	4		T110	15		T215	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T107	14		T148	13		T114	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T119	2		T216	15		T122	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T216	2		T60	4		T141	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T19	15		T21	5		T108	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T15	4		T21	9		T33	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T50	9		T54	18		T223	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T7	2		T29	3		T36	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T21	16		T107	7		T103	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T103	17		T109	5		T110	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T106	1		T112	1		T153	21
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T22	12		T41	21		T108	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T42	11		T150	4		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T148	7		T63	14		T121	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1165	1			T18	1		T21	4		T23	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T20	12		T106	1		T104	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T20	8		T118	1		T104	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T116	1		T110	3		T215	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T16	1		T106	1		T58	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T109	5		T110	16		T111	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T101	1		T40	1		T107	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T24	1		T108	6		T119	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T21	10		T111	1		T216	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T19	16		T21	6		T24	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T15	5		T24	1		T33	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T54	19		T104	1		T223	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T238	1		T256	4		T257	21
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T225	15		T249	5		T65	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15670	1			T7	2		T29	3		T36	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T21	14		T112	10		T220	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T103	14		T110	11		T148	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T112	12		T153	17		T122	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T22	11		T41	23		T108	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T42	11		T150	6		T151	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T148	3		T63	8		T121	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	867	1			T18	9		T23	19		T166	34
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T121	3		T114	5		T179	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T112	8		T183	13		T263	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T116	14		T110	9		T215	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T58	1		T59	2		T114	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T110	12		T153	9		T216	23
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T101	5		T40	8		T148	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T108	11		T122	10		T179	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T21	10		T216	7		T113	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T19	17		T21	9		T50	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T33	1		T105	2		T113	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T54	16		T234	7		T218	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T238	8		T264	1		T255	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T249	2		T265	8		T261	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T146	8		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T65	3		T254	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T248	1		T202	5		T255	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T262	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T21	16		T109	6		T112	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T103	17		T109	5		T110	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T106	1		T107	7		T103	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T41	21		T119	12		T148	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T151	1		T182	9		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T22	12		T108	16		T148	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1195	1			T18	1		T21	4		T23	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T20	12		T106	1		T104	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T118	1		T34	3		T124	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T116	1		T110	3		T182	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T16	1		T20	8		T106	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T24	1		T109	5		T110	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T107	15		T111	1		T148	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T119	3		T216	16		T122	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T101	1		T40	1		T111	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T19	16		T21	6		T108	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T15	5		T21	10		T24	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	358	1			T24	1		T50	10		T54	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15669	1			T7	2		T29	3		T36	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T254	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T248	8		T255	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T21	14		T112	22		T220	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T103	14		T110	11		T35	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T153	17		T122	12		T228	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T41	23		T148	5		T171	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T151	2		T237	7		T222	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T22	11		T108	10		T148	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	917	1			T18	9		T23	19		T42	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T63	8		T114	5		T226	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T34	1		T154	5		T183	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T116	14		T110	9		T115	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T58	1		T112	8		T59	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T110	12		T215	11		T153	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T148	15		T233	3		T114	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T216	13		T122	10		T179	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T101	5		T40	8		T216	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T19	17		T21	9		T108	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T21	10		T33	1		T105	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T50	9		T54	16		T234	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20026

1

T7

2

T29

3

T36

1

auto[1]

auto[0]

3082

1

T18

9

T19

17

T21

33