Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23108

1

T7

2

T29

3

T36

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20267

1

T7

2

T29

3

T36

1

auto[ADC_CTRL_FILTER_COND_OUT]

2841

1

T16

1

T19

33

T20

20

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17867

1

T7

2

T29

3

T36

1

auto[1]

5241

1

T16

1

T18

10

T19

33

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19568

1

T15

1

T16

1

T17

15

auto[1]

3540

1

T7

2

T29

3

T36

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	8	1			T35	8		-	-		-	-
values[0]	41	1			T143	17		T266	8		T267	11
values[1]	507	1			T50	19		T33	7		T109	6
values[2]	2380	1			T18	10		T23	22		T25	3
values[3]	653	1			T15	5		T22	23		T24	1
values[4]	727	1			T19	33		T21	50		T41	28
values[5]	621	1			T20	12		T107	15		T103	31
values[6]	574	1			T20	8		T24	1		T118	1
values[7]	543	1			T24	1		T42	22		T107	7
values[8]	558	1			T16	1		T21	19		T106	1
values[9]	827	1			T40	9		T54	35		T108	17
minimum	15669	1			T7	2		T29	3		T36	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	713	1			T101	6		T50	19		T33	7
values[1]	2422	1			T18	10		T23	22		T25	3
values[2]	605	1			T15	5		T22	23		T24	1
values[3]	687	1			T19	33		T20	12		T21	50
values[4]	683	1			T41	28		T107	15		T103	31
values[5]	508	1			T20	8		T24	1		T42	22
values[6]	550	1			T21	4		T24	1		T109	5
values[7]	513	1			T16	1		T21	15		T106	1
values[8]	564	1			T40	9		T108	17		T35	8
values[9]	170	1			T54	35		T123	1		T268	1
minimum	15693	1			T7	2		T29	3		T36	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20026

1

T7

2

T29

3

T36

1

auto[1]

3082

1

T18

9

T19

17

T21

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T101	6		T109	1		T34	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T50	10		T33	5		T150	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1233	1			T18	10		T23	22		T25	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T53	1		T104	1		T63	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T15	1		T41	14		T58	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T22	12		T24	1		T116	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T21	11		T109	1		T110	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T19	18		T20	1		T21	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T107	1		T110	13		T111	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T41	11		T103	15		T153	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T24	1		T42	12		T107	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T20	1		T108	11		T59	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T21	1		T109	1		T238	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T24	1		T111	1		T148	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T21	10		T122	13		T231	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T16	1		T106	1		T119	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T108	12		T35	4		T184	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T40	9		T216	14		T269	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T54	17		T123	1		T268	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T159	1		T253	8		T270	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15554	1			T17	15		T20	158		T37	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T109	5		T34	1		T119	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T50	9		T33	2		T150	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	907	1			T110	10		T139	14		T149	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T63	9		T171	10		T61	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T15	4		T41	2		T58	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T22	11		T148	6		T217	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T21	9		T109	4		T110	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T19	15		T20	11		T21	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T107	14		T110	15		T148	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T41	17		T103	16		T153	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T42	10		T107	6		T103	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T20	7		T108	15		T59	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T21	3		T109	4		T245	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T148	13		T232	16		T141	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T21	5		T122	12		T178	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T119	17		T232	13		T183	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T108	5		T35	4		T216	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T216	15		T228	2		T125	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T54	18		T171	16		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T159	1		T253	9		T271	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T7	2		T29	3		T36	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T35	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T143	1		T267	1		T272	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T266	1		T273	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T109	1		T34	3		T105	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T50	10		T33	5		T105	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1197	1			T18	10		T23	22		T25	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T104	1		T150	7		T63	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T15	1		T41	14		T106	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T22	12		T24	1		T53	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T21	11		T110	10		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T19	18		T21	15		T41	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T107	1		T109	1		T110	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T20	1		T103	15		T108	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T24	1		T118	1		T103	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T20	1		T59	7		T153	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T42	12		T107	1		T109	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T24	1		T111	1		T148	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T21	11		T122	13		T178	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T16	1		T106	1		T119	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T54	17		T108	12		T184	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T40	9		T111	1		T216	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15540	1			T17	15		T20	158		T37	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T35	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T143	16		T267	10		T272	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T266	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T109	5		T34	1		T121	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T50	9		T33	2		T215	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	879	1			T119	2		T139	14		T149	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T150	3		T63	9		T249	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T15	4		T41	2		T58	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T22	11		T217	5		T171	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T21	9		T110	2		T224	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T19	15		T21	15		T41	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T107	14		T109	4		T110	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T20	11		T103	16		T108	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T103	2		T245	14		T141	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T20	7		T59	2		T153	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T42	10		T107	6		T109	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T148	13		T141	2		T230	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T21	8		T122	12		T178	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T119	17		T232	29		T259	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T54	18		T108	5		T216	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T216	15		T228	2		T125	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T7	2		T29	3		T36	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T101	1		T109	6		T34	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T50	10		T33	6		T150	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1204	1			T18	1		T23	3		T25	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T53	1		T104	1		T63	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T15	5		T41	3		T58	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T22	12		T24	1		T116	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T21	10		T109	5		T110	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T19	16		T20	12		T21	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T107	15		T110	16		T111	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T41	18		T103	17		T153	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T24	1		T42	11		T107	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T20	8		T108	16		T59	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T21	4		T109	5		T238	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T24	1		T111	1		T148	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T21	6		T122	13		T231	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T16	1		T106	1		T119	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T108	6		T35	6		T184	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T40	1		T216	16		T269	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T54	19		T123	1		T268	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T159	2		T253	10		T270	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15681	1			T7	2		T29	3		T36	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T101	5		T34	1		T105	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T50	9		T33	1		T150	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	936	1			T18	9		T23	19		T166	34
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T63	8		T113	14		T171	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T41	13		T58	1		T153	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T22	11		T116	14		T148	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T21	10		T110	9		T112	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T19	17		T21	14		T151	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T110	12		T148	3		T216	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T41	10		T103	14		T153	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T42	11		T112	10		T233	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T108	10		T59	2		T274	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T238	8		T222	9		T229	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T148	15		T232	11		T141	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T21	9		T122	12		T231	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T233	3		T179	15		T234	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T108	11		T35	2		T216	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T40	8		T216	13		T228	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T54	16		T171	4		T255	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T253	7		T275	10		T276	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T113	12		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T35	6		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T143	17		T267	11		T272	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T266	8		T273	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T109	6		T34	3		T105	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T50	10		T33	6		T105	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1174	1			T18	1		T23	3		T25	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T104	1		T150	4		T63	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T15	5		T41	3		T106	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T22	12		T24	1		T53	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T21	10		T110	3		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T19	16		T21	16		T41	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T107	15		T109	5		T110	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T20	12		T103	17		T108	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T24	1		T118	1		T103	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T20	8		T59	7		T153	21
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T42	11		T107	7		T109	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T24	1		T111	1		T148	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T21	10		T122	13		T178	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T16	1		T106	1		T119	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T54	19		T108	6		T184	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T40	1		T111	1		T216	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15669	1			T7	2		T29	3		T36	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T35	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T34	1		T105	2		T121	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T50	9		T33	1		T105	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	902	1			T18	9		T23	19		T166	34
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T150	6		T63	8		T234	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T41	13		T58	1		T110	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T22	11		T151	2		T113	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T21	10		T110	9		T217	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T19	17		T21	14		T41	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T110	12		T112	8		T148	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T103	14		T108	10		T220	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T112	10		T233	11		T141	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T59	2		T153	17		T175	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T42	11		T238	8		T126	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T148	15		T179	15		T141	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T21	9		T122	12		T234	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T234	10		T232	23		T218	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T54	16		T108	11		T216	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T40	8		T216	13		T233	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20026

1

T7

2

T29

3

T36

1

auto[1]

auto[0]

3082

1

T18

9

T19

17

T21

33