Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23108

1

T7

2

T29

3

T36

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19903

1

T7

2

T29

3

T36

1

auto[ADC_CTRL_FILTER_COND_OUT]

3205

1

T20

8

T24

2

T41

28

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17944

1

T7

2

T29

3

T36

1

auto[1]

5164

1

T15

5

T16

1

T18

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19568

1

T15

1

T16

1

T17

15

auto[1]

3540

1

T7

2

T29

3

T36

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	337	1			T20	4		T38	8		T55	2
values[0]	65	1			T61	25		T213	1		T277	1
values[1]	541	1			T41	16		T107	15		T109	5
values[2]	2560	1			T18	10		T19	33		T20	12
values[3]	494	1			T21	19		T24	1		T41	28
values[4]	569	1			T21	30		T107	7		T108	26
values[5]	523	1			T106	1		T119	18		T114	11
values[6]	465	1			T40	9		T110	22		T111	1
values[7]	581	1			T15	5		T20	8		T53	1
values[8]	607	1			T16	1		T21	20		T24	2
values[9]	1034	1			T22	23		T106	1		T101	6
minimum	15332	1			T7	2		T29	3		T36	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	723	1			T54	35		T107	15		T58	4
values[1]	2464	1			T18	10		T19	33		T20	12
values[2]	508	1			T21	19		T24	1		T41	28
values[3]	540	1			T21	30		T106	1		T107	7
values[4]	608	1			T40	9		T148	12		T224	15
values[5]	512	1			T15	5		T20	8		T110	22
values[6]	535	1			T21	20		T24	1		T53	1
values[7]	565	1			T16	1		T24	1		T101	6
values[8]	781	1			T22	23		T106	1		T33	7
values[9]	133	1			T34	4		T215	21		T234	7
minimum	15739	1			T7	2		T29	3		T36	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20026

1

T7

2

T29

3

T36

1

auto[1]

3082

1

T18

9

T19

17

T21

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T58	3		T151	3		T220	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T54	17		T107	1		T109	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1233	1			T18	10		T19	18		T20	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T111	1		T112	9		T148	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T21	11		T24	1		T103	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T41	11		T50	10		T110	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T21	15		T106	1		T105	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T107	1		T108	11		T119	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T114	6		T178	1		T180	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T40	9		T148	6		T224	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T15	1		T110	12		T171	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T20	1		T175	10		T125	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T21	11		T111	1		T104	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T24	1		T53	1		T111	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T16	1		T118	1		T110	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T24	1		T101	6		T104	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T22	12		T106	1		T35	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T33	5		T103	15		T109	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T34	3		T278	1		T279	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T215	12		T234	7		T280	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15567	1			T17	15		T20	158		T37	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T144	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T58	1		T220	2		T226	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T54	18		T107	14		T109	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	909	1			T19	15		T20	11		T42	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T148	13		T182	8		T125	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T21	8		T103	2		T109	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T41	17		T50	9		T110	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T21	15		T114	9		T228	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T107	6		T108	15		T119	28
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T114	5		T178	4		T171	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T148	6		T224	14		T189	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T15	4		T110	10		T171	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T20	7		T175	9		T125	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T21	9		T216	16		T142	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T153	15		T245	4		T61	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T110	2		T63	9		T249	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T153	20		T122	12		T228	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T22	11		T35	4		T217	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T33	2		T103	16		T109	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T34	1		T278	10		T281	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T215	9		T282	20		T283	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T7	2		T29	3		T36	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T144	14		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	337	1			T20	4		T38	8		T55	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T213	1		T284	11		T285	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T61	11		T277	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T41	14		T151	3		T220	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T107	1		T109	1		T216	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1233	1			T18	10		T19	18		T20	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T54	17		T111	1		T148	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T21	11		T24	1		T103	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T41	11		T50	10		T112	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T21	15		T113	7		T114	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T107	1		T108	11		T110	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T106	1		T114	6		T178	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T119	1		T189	13		T125	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T110	12		T111	1		T104	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T40	9		T148	6		T224	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T15	1		T142	2		T129	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T20	1		T53	1		T111	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T16	1		T21	11		T118	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T24	2		T104	1		T182	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T22	12		T106	1		T34	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T101	6		T33	5		T103	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15203	1			T17	15		T20	154		T37	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T284	9		T285	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T61	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T41	2		T220	2		T137	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T107	14		T109	4		T216	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	929	1			T19	15		T20	11		T42	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T54	18		T148	13		T150	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T21	8		T103	2		T109	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T41	17		T50	9		T224	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T21	15		T114	9		T228	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T107	6		T108	15		T110	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T114	5		T178	4		T171	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T119	17		T189	10		T125	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T110	10		T171	10		T232	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T148	6		T224	14		T175	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T15	4		T142	1		T62	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T20	7		T153	15		T245	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T21	9		T216	16		T63	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T182	11		T153	20		T122	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T22	11		T34	1		T110	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T33	2		T103	16		T109	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T7	2		T29	3		T36	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T58	3		T151	1		T220	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T54	19		T107	15		T109	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1214	1			T18	1		T19	16		T20	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T111	1		T112	1		T148	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T21	10		T24	1		T103	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T41	18		T50	10		T110	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T21	16		T106	1		T105	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T107	7		T108	16		T119	30
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T114	6		T178	5		T180	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T40	1		T148	7		T224	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T15	5		T110	11		T171	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T20	8		T175	10		T125	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T21	10		T111	1		T104	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T24	1		T53	1		T111	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T16	1		T118	1		T110	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T24	1		T101	1		T104	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T22	12		T106	1		T35	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T33	6		T103	17		T109	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T34	3		T278	11		T279	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T215	10		T234	1		T280	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15695	1			T7	2		T29	3		T36	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T144	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T58	1		T151	2		T220	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T54	16		T216	7		T221	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	928	1			T18	9		T19	17		T23	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T112	8		T148	15		T238	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T21	9		T233	11		T113	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T41	10		T50	9		T110	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T21	14		T105	8		T114	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T108	10		T148	3		T216	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T114	5		T171	4		T232	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T40	8		T148	5		T189	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T110	11		T171	11		T258	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T175	9		T125	13		T279	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T21	10		T216	10		T142	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T153	9		T286	5		T213	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T110	9		T63	8		T249	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T101	5		T153	17		T113	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T22	11		T35	2		T112	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T33	1		T103	14		T112	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T34	1		T279	3		T281	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T215	11		T234	6		T283	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T41	13		T284	10		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T144	6		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	337	1			T20	4		T38	8		T55	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T213	1		T284	10		T285	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T61	19		T277	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T41	3		T151	1		T220	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T107	15		T109	5		T216	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1233	1			T18	1		T19	16		T20	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T54	19		T111	1		T148	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T21	10		T24	1		T103	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T41	18		T50	10		T112	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T21	16		T113	1		T114	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T107	7		T108	16		T110	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T106	1		T114	6		T178	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T119	18		T189	17		T125	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T110	11		T111	1		T104	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T40	1		T148	7		T224	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T15	5		T142	2		T129	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T20	8		T53	1		T111	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T16	1		T21	10		T118	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T24	2		T104	1		T182	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T22	12		T106	1		T34	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T101	1		T33	6		T103	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15332	1			T7	2		T29	3		T36	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T284	10		T285	2		T287	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T61	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T41	13		T151	2		T220	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T216	7		T142	3		T190	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	929	1			T18	9		T19	17		T23	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T54	16		T148	15		T150	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T21	9		T105	8		T233	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T41	10		T50	9		T112	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T21	14		T113	6		T114	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T108	10		T110	12		T148	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T114	5		T171	4		T249	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T189	6		T125	13		T237	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T110	11		T171	11		T232	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T40	8		T148	5		T175	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T142	1		T62	4		T258	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T153	9		T179	14		T286	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T21	10		T216	10		T63	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T153	17		T113	14		T122	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T22	11		T34	1		T110	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T101	5		T33	1		T103	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20026

1

T7

2

T29

3

T36

1

auto[1]

auto[0]

3082

1

T18

9

T19

17

T21

33