Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23108

1

T7

2

T29

3

T36

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20147

1

T7

2

T29

3

T36

1

auto[ADC_CTRL_FILTER_COND_OUT]

2961

1

T15

5

T16

1

T20

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18381

1

T7

2

T29

3

T36

1

auto[1]

4727

1

T15

5

T16

1

T18

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19568

1

T15

1

T16

1

T17

15

auto[1]

3540

1

T7

2

T29

3

T36

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	2	1			T288	1		T289	1		-	-
values[0]	54	1			T103	31		T221	5		T127	1
values[1]	575	1			T21	15		T42	22		T53	1
values[2]	459	1			T106	1		T34	4		T111	1
values[3]	596	1			T24	1		T106	1		T107	7
values[4]	565	1			T101	6		T40	9		T50	19
values[5]	2539	1			T15	5		T18	10		T20	8
values[6]	587	1			T58	4		T109	6		T104	1
values[7]	540	1			T20	12		T21	20		T24	1
values[8]	503	1			T16	1		T116	15		T107	15
values[9]	1019	1			T19	33		T21	4		T24	1
minimum	15669	1			T7	2		T29	3		T36	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	731	1			T21	15		T42	22		T53	1
values[1]	459	1			T106	1		T107	7		T34	4
values[2]	592	1			T106	1		T40	9		T50	19
values[3]	2448	1			T15	5		T18	10		T23	22
values[4]	612	1			T20	8		T21	30		T22	23
values[5]	583	1			T103	3		T108	26		T109	6
values[6]	577	1			T16	1		T20	12		T21	20
values[7]	596	1			T116	15		T109	5		T110	28
values[8]	664	1			T19	33		T21	4		T24	1
values[9]	154	1			T119	21		T223	2		T63	22
minimum	15692	1			T7	2		T29	3		T36	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20026

1

T7

2

T29

3

T36

1

auto[1]

3082

1

T18

9

T19

17

T21

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T53	1		T103	15		T119	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T21	10		T42	12		T182	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T34	3		T150	7		T182	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T106	1		T107	1		T111	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T225	1		T245	2		T125	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T106	1		T40	9		T50	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1170	1			T18	10		T23	22		T24	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T15	1		T122	24		T217	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T20	1		T21	15		T41	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T22	12		T33	5		T58	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T103	1		T109	1		T35	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T108	11		T110	12		T104	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T21	11		T41	14		T108	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T16	1		T20	1		T24	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T109	1		T112	11		T113	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T116	15		T110	13		T112	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T19	18		T24	1		T104	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T21	1		T54	17		T220	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T119	1		T223	1		T63	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T119	1		T233	12		T290	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15549	1			T17	15		T20	158		T37	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T221	3		T140	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T103	16		T119	11		T148	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T21	5		T42	10		T182	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T34	1		T150	3		T182	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T107	6		T224	14		T141	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T225	14		T245	14		T125	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T50	9		T148	13		T153	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	888	1			T110	2		T139	14		T149	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T15	4		T122	21		T217	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T20	7		T21	15		T41	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T22	11		T33	2		T58	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T103	2		T109	5		T35	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T108	15		T110	10		T221	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T21	9		T41	2		T108	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T20	11		T107	14		T230	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T109	4		T245	4		T141	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T110	15		T224	8		T114	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T19	15		T227	12		T291	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T21	3		T54	18		T220	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T119	2		T223	1		T63	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T119	17		T292	7		T293	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T7	2		T29	3		T36	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T221	2		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T288	1		T289	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T103	15		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T221	3		T127	1		T248	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T53	1		T119	1		T148	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T21	10		T42	12		T121	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T34	3		T182	1		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T106	1		T111	1		T182	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T24	1		T150	7		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T106	1		T107	1		T118	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T101	6		T110	10		T153	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T40	9		T50	10		T148	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1170	1			T18	10		T20	1		T21	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T15	1		T22	12		T33	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T109	1		T35	4		T63	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T58	3		T104	1		T233	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T21	11		T41	14		T103	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T20	1		T24	1		T108	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T104	1		T112	11		T59	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T16	1		T116	15		T107	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T19	18		T24	1		T109	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T21	1		T54	17		T119	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15540	1			T17	15		T20	158		T37	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T103	16		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T221	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T119	11		T148	6		T215	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T21	5		T42	10		T121	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T34	1		T182	8		T228	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T182	11		T224	14		T141	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T150	3		T225	14		T245	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T107	6		T153	15		T216	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T110	2		T153	20		T245	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T50	9		T148	13		T122	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	930	1			T20	7		T21	15		T41	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T15	4		T22	11		T33	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T109	5		T35	4		T63	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T58	1		T249	9		T141	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T21	9		T41	2		T103	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T20	11		T108	15		T110	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T59	2		T223	1		T154	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T107	14		T110	15		T224	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T19	15		T109	4		T119	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T21	3		T54	18		T119	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T7	2		T29	3		T36	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T53	1		T103	17		T119	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T21	6		T42	11		T182	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T34	3		T150	4		T182	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T106	1		T107	7		T111	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T225	15		T245	16		T125	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T106	1		T40	1		T50	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1183	1			T18	1		T23	3		T24	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T15	5		T122	23		T217	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T20	8		T21	16		T41	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T22	12		T33	6		T58	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T103	3		T109	6		T35	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T108	16		T110	11		T104	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T21	10		T41	3		T108	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T16	1		T20	12		T24	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T109	5		T112	1		T113	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T116	1		T110	16		T112	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T19	16		T24	1		T104	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T21	4		T54	19		T220	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T119	3		T223	2		T63	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T119	18		T233	1		T290	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15678	1			T7	2		T29	3		T36	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T221	3		T140	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T103	14		T148	5		T215	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T21	9		T42	11		T121	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T34	1		T150	6		T60	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T113	6		T141	2		T248	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T125	13		T239	9		T145	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T40	8		T50	9		T148	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	875	1			T18	9		T23	19		T166	34
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T122	22		T217	10		T189	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T21	14		T41	10		T105	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T22	11		T33	1		T58	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T35	2		T105	8		T137	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T108	10		T110	11		T233	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T21	10		T41	13		T108	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T230	10		T190	4		T294	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T112	10		T113	14		T179	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T116	14		T110	12		T112	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T19	17		T151	2		T234	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T54	16		T220	12		T115	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T63	8		T237	7		T295	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T233	11		T146	13		T293	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T249	8		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T221	2		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T288	1		T289	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T103	17		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T221	3		T127	1		T248	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T53	1		T119	12		T148	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T21	6		T42	11		T121	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T34	3		T182	9		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T106	1		T111	1		T182	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T24	1		T150	4		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T106	1		T107	7		T118	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T101	1		T110	3		T153	21
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T40	1		T50	10		T148	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1233	1			T18	1		T20	8		T21	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T15	5		T22	12		T33	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T109	6		T35	6		T63	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T58	3		T104	1		T233	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T21	10		T41	3		T103	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T20	12		T24	1		T108	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T104	1		T112	1		T59	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T16	1		T116	1		T107	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T19	16		T24	1		T109	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	354	1			T21	4		T54	19		T119	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15669	1			T7	2		T29	3		T36	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T103	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T221	2		T248	3		T169	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T148	5		T215	11		T216	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T21	9		T42	11		T121	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T34	1		T228	2		T60	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T238	8		T141	2		T222	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T150	6		T232	12		T62	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T153	9		T216	17		T113	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T101	5		T110	9		T153	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T40	8		T50	9		T148	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	867	1			T18	9		T21	14		T23	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T22	11		T33	1		T148	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T35	2		T137	5		T114	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T58	1		T233	3		T249	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T21	10		T41	13		T108	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T108	10		T110	11		T190	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T112	10		T59	2		T113	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T116	14		T110	12		T112	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T19	17		T151	2		T63	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T54	16		T220	12		T233	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20026

1

T7

2

T29

3

T36

1

auto[1]

auto[0]

3082

1

T18

9

T19

17

T21

33